1/* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * [ Initialisation is based on Linus' ] 8 * [ uhci code and gregs ohci fragments ] 9 * [ (C) Copyright 1999 Linus Torvalds ] 10 * [ (C) Copyright 1999 Gregory P. Smith] 11 * 12 * PCI Bus Glue 13 * 14 * This file is licenced under the GPL. 15 */ 16 17#ifndef CONFIG_PCI 18#error "This file is PCI bus glue. CONFIG_PCI must be defined." 19#endif 20 21/*-------------------------------------------------------------------------*/ 22 23static int broken_suspend(struct usb_hcd *hcd) 24{ 25 device_init_wakeup(&hcd->self.root_hub->dev, 0); 26 return 0; 27} 28 29static int ohci_quirk_amd756(struct usb_hcd *hcd) 30{ 31 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 32 33 ohci->flags = OHCI_QUIRK_AMD756; 34 ohci_dbg (ohci, "AMD756 erratum 4 workaround\n"); 35 36 /* also erratum 10 (suspend/resume issues) */ 37 return broken_suspend(hcd); 38} 39 40/* Apple's OHCI driver has a lot of bizarre workarounds 41 * for this chip. Evidently control and bulk lists 42 * can get confused. (B&W G3 models, and ...) 43 */ 44static int ohci_quirk_opti(struct usb_hcd *hcd) 45{ 46 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 47 48 ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n"); 49 50 return 0; 51} 52 53/* Check for NSC87560. We have to look at the bridge (fn1) to 54 * identify the USB (fn2). This quirk might apply to more or 55 * even all NSC stuff. 56 */ 57static int ohci_quirk_ns(struct usb_hcd *hcd) 58{ 59 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 60 struct pci_dev *b; 61 62 b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1)); 63 if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO 64 && b->vendor == PCI_VENDOR_ID_NS) { 65 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 66 67 ohci->flags |= OHCI_QUIRK_SUPERIO; 68 ohci_dbg (ohci, "Using NSC SuperIO setup\n"); 69 } 70 pci_dev_put(b); 71 72 return 0; 73} 74 75/* Check for Compaq's ZFMicro chipset, which needs short 76 * delays before control or bulk queues get re-activated 77 * in finish_unlinks() 78 */ 79static int ohci_quirk_zfmicro(struct usb_hcd *hcd) 80{ 81 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 82 83 ohci->flags |= OHCI_QUIRK_ZFMICRO; 84 ohci_dbg (ohci, "enabled Compaq ZFMicro chipset quirk\n"); 85 86 return 0; 87} 88 89/* Check for Toshiba SCC OHCI which has big endian registers 90 * and little endian in memory data structures 91 */ 92static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd) 93{ 94 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 95 96 /* That chip is only present in the southbridge of some 97 * cell based platforms which are supposed to select 98 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if 99 * that was the case though. 100 */ 101#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO 102 ohci->flags |= OHCI_QUIRK_BE_MMIO; 103 ohci_dbg (ohci, "enabled big endian Toshiba quirk\n"); 104 return 0; 105#else 106 ohci_err (ohci, "unsupported big endian Toshiba quirk\n"); 107 return -ENXIO; 108#endif 109} 110 111/* List of quirks for OHCI */ 112static const struct pci_device_id ohci_pci_quirks[] = { 113 { 114 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c), 115 .driver_data = (unsigned long)ohci_quirk_amd756, 116 }, 117 { 118 PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861), 119 .driver_data = (unsigned long)ohci_quirk_opti, 120 }, 121 { 122 PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID), 123 .driver_data = (unsigned long)ohci_quirk_ns, 124 }, 125 { 126 PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8), 127 .driver_data = (unsigned long)ohci_quirk_zfmicro, 128 }, 129 { 130 PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6), 131 .driver_data = (unsigned long)ohci_quirk_toshiba_scc, 132 }, 133 { 134 /* Toshiba portege 4000 */ 135 .vendor = PCI_VENDOR_ID_AL, 136 .device = 0x5237, 137 .subvendor = PCI_VENDOR_ID_TOSHIBA, 138 .subdevice = 0x0004, 139 .driver_data = (unsigned long) broken_suspend, 140 }, 141 { 142 PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152), 143 .driver_data = (unsigned long) broken_suspend, 144 }, 145 146 {}, 147}; 148 149static int ohci_pci_reset (struct usb_hcd *hcd) 150{ 151 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 152 int ret = 0; 153 154 if (hcd->self.controller) { 155 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 156 const struct pci_device_id *quirk_id; 157 158 quirk_id = pci_match_id(ohci_pci_quirks, pdev); 159 if (quirk_id != NULL) { 160 int (*quirk)(struct usb_hcd *ohci); 161 quirk = (void *)quirk_id->driver_data; 162 ret = quirk(hcd); 163 } 164 } 165 if (ret == 0) { 166 ohci_hcd_init (ohci); 167 return ohci_init (ohci); 168 } 169 return ret; 170} 171 172 173static int __devinit ohci_pci_start (struct usb_hcd *hcd) 174{ 175 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 176 int ret; 177 178#ifdef CONFIG_PM /* avoid warnings about unused pdev */ 179 if (hcd->self.controller) { 180 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 181 182 /* RWC may not be set for add-in PCI cards, since boot 183 * firmware probably ignored them. This transfers PCI 184 * PM wakeup capabilities (once the PCI layer is fixed). 185 */ 186 if (device_may_wakeup(&pdev->dev)) 187 ohci->hc_control |= OHCI_CTRL_RWC; 188 } 189#endif /* CONFIG_PM */ 190 191 ret = ohci_run (ohci); 192 if (ret < 0) { 193 ohci_err (ohci, "can't start\n"); 194 ohci_stop (hcd); 195 } 196 return ret; 197} 198 199#ifdef CONFIG_PM 200 201static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message) 202{ 203 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 204 unsigned long flags; 205 int rc = 0; 206 207 /* Root hub was already suspended. Disable irq emission and 208 * mark HW unaccessible, bail out if RH has been resumed. Use 209 * the spinlock to properly synchronize with possible pending 210 * RH suspend or resume activity. 211 * 212 * This is still racy as hcd->state is manipulated outside of 213 * any locks =P But that will be a different fix. 214 */ 215 spin_lock_irqsave (&ohci->lock, flags); 216 if (hcd->state != HC_STATE_SUSPENDED) { 217 rc = -EINVAL; 218 goto bail; 219 } 220 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 221 (void)ohci_readl(ohci, &ohci->regs->intrdisable); 222 223 /* make sure snapshot being resumed re-enumerates everything */ 224 if (message.event == PM_EVENT_PRETHAW) 225 ohci_usb_reset(ohci); 226 227 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 228 bail: 229 spin_unlock_irqrestore (&ohci->lock, flags); 230 231 return rc; 232} 233 234 235static int ohci_pci_resume (struct usb_hcd *hcd) 236{ 237 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 238 usb_hcd_resume_root_hub(hcd); 239 return 0; 240} 241 242#endif /* CONFIG_PM */ 243 244 245/*-------------------------------------------------------------------------*/ 246 247static const struct hc_driver ohci_pci_hc_driver = { 248 .description = hcd_name, 249 .product_desc = "OHCI Host Controller", 250 .hcd_priv_size = sizeof(struct ohci_hcd), 251 252 /* 253 * generic hardware linkage 254 */ 255 .irq = ohci_irq, 256 .flags = HCD_MEMORY | HCD_USB11, 257 258 /* 259 * basic lifecycle operations 260 */ 261 .reset = ohci_pci_reset, 262 .start = ohci_pci_start, 263 .stop = ohci_stop, 264 .shutdown = ohci_shutdown, 265 266#ifdef CONFIG_PM 267 /* these suspend/resume entries are for upstream PCI glue ONLY */ 268 .suspend = ohci_pci_suspend, 269 .resume = ohci_pci_resume, 270#endif 271 272 /* 273 * managing i/o requests and associated device resources 274 */ 275 .urb_enqueue = ohci_urb_enqueue, 276 .urb_dequeue = ohci_urb_dequeue, 277 .endpoint_disable = ohci_endpoint_disable, 278 279 /* 280 * scheduling support 281 */ 282 .get_frame_number = ohci_get_frame, 283 284 /* 285 * root hub support 286 */ 287 .hub_status_data = ohci_hub_status_data, 288 .hub_control = ohci_hub_control, 289 .hub_irq_enable = ohci_rhsc_enable, 290#ifdef CONFIG_PM 291 .bus_suspend = ohci_bus_suspend, 292 .bus_resume = ohci_bus_resume, 293#endif 294 .start_port_reset = ohci_start_port_reset, 295}; 296 297/*-------------------------------------------------------------------------*/ 298 299 300static const struct pci_device_id pci_ids [] = { { 301 /* handle any USB OHCI controller */ 302 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0), 303 .driver_data = (unsigned long) &ohci_pci_hc_driver, 304 }, { /* end: all zeroes */ } 305}; 306MODULE_DEVICE_TABLE (pci, pci_ids); 307 308/* pci driver glue; this is a "new style" PCI driver module */ 309static struct pci_driver ohci_pci_driver = { 310 .name = (char *) hcd_name, 311 .id_table = pci_ids, 312 313 .probe = usb_hcd_pci_probe, 314 .remove = usb_hcd_pci_remove, 315 316#ifdef CONFIG_PM 317 .suspend = usb_hcd_pci_suspend, 318 .resume = usb_hcd_pci_resume, 319#endif 320 321 .shutdown = usb_hcd_pci_shutdown, 322}; 323