1/* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#ifndef __LINUX_EHCI_HCD_H 20#define __LINUX_EHCI_HCD_H 21 22/* definitions used for the EHCI driver */ 23 24/* statistics can be kept for for tuning/monitoring */ 25struct ehci_stats { 26 /* irq usage */ 27 unsigned long normal; 28 unsigned long error; 29 unsigned long reclaim; 30 unsigned long lost_iaa; 31 32 /* termination of urbs from core */ 33 unsigned long complete; 34 unsigned long unlink; 35}; 36 37/* qtdc message level */ 38#define QTDC_MSG_ERR (1<<0) 39#define QTDC_MSG_STATS (1<<1) 40#define QTDC_MSG_TRACE (1<<2) 41 42#ifdef EHCI_QTD_CACHE 43typedef struct ehci_qtdc { 44 void *ehci; /* pointer to ehci */ 45 int num; /* qtdc number */ 46 int ep; /* endpoint */ 47 int size; /* max qtd's in cache */ 48 int cnt; /* current qtd's in cache */ 49 int timeout; /* max time to stay in cache */ 50 struct list_head cache; /* the qtd cache list */ 51 struct timer_list watchdog; 52#ifdef EHCI_QTDC_DEBUG 53 unsigned long last_printed; /* last time when we printed stats */ 54 unsigned long cached_qtd; /* counter for cached qtd's */ 55 unsigned long timeout_qtd; /* counter for qtd's released in timeout */ 56 unsigned long timeout_qtd_max;/* max qtd's released in timeout */ 57 unsigned long timeout_cnt; /* counter for timeouts */ 58 unsigned long release_qtd; /* counter for qtd's released normally */ 59 unsigned long release_cnt; /* counter for normal release */ 60 unsigned int msglevel; 61#endif /* EHCI_QTDC_DEBUG */ 62} ehci_qtdc_t; 63 64#define NUM_QTD_CACHE 2 /* # of ep's supported (1 IN 1 OUT for now) */ 65 66#ifdef EHCI_QTDC_DEBUG 67#define QTDC_ERR(qtdc, msg) do { \ 68 if (qtdc->msglevel & QTDC_MSG_ERR) { \ 69 printk("qtdc ep 0x%x: ", qtdc->ep); \ 70 printk msg; \ 71 } \ 72 } while(0) 73#define QTDC_STATS(qtdc, msg) do { \ 74 if (qtdc->msglevel & QTDC_MSG_STATS) { \ 75 printk("qtdc ep 0x%x: ", qtdc->ep); \ 76 printk msg; \ 77 } \ 78 } while(0) 79#define QTDC_TRACE(qtdc, msg) do { \ 80 if (qtdc->msglevel & QTDC_MSG_TRACE) { \ 81 printk("qtdc ep 0x%x: ", qtdc->ep); \ 82 printk msg; \ 83 } \ 84 } while(0) 85#else 86#define QTDC_ERR(qtdc, msg) 87#define QTDC_STATS(qtdc, msg) 88#define QTDC_TRACE(qtdc, msg) 89#endif /* EHCI_QTDC_DEBUG */ 90#endif /* EHCI_QTD_CACHE */ 91 92/* ehci_hcd->lock guards shared data against other CPUs: 93 * ehci_hcd: async, reclaim, periodic (and shadow), ... 94 * usb_host_endpoint: hcpriv 95 * ehci_qh: qh_next, qtd_list 96 * ehci_qtd: qtd_list 97 * 98 * Also, hold this lock when talking to HC registers or 99 * when updating hw_* fields in shared qh/qtd/... structures. 100 */ 101 102#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 103 104struct ehci_hcd { /* one per controller */ 105 /* glue to PCI and HCD framework */ 106 struct ehci_caps __iomem *caps; 107 struct ehci_regs __iomem *regs; 108 struct ehci_dbg_port __iomem *debug; 109 110 __u32 hcs_params; /* cached register copy */ 111 spinlock_t lock; 112 113 /* async schedule support */ 114 struct ehci_qh *async; 115 struct ehci_qh *reclaim; 116 unsigned reclaim_ready : 1; 117 unsigned scanning : 1; 118 119 /* periodic schedule support */ 120#define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 121 unsigned periodic_size; 122 __le32 *periodic; /* hw periodic table */ 123 dma_addr_t periodic_dma; 124 unsigned i_thresh; /* uframes HC might cache */ 125 126 union ehci_shadow *pshadow; /* mirror hw periodic table */ 127 int next_uframe; /* scan periodic, start here */ 128 unsigned periodic_sched; /* periodic activity count */ 129 130 /* per root hub port */ 131 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 132 /* bit vectors (one bit per port) */ 133 unsigned long bus_suspended; /* which ports were 134 already suspended at the start of a bus suspend */ 135 unsigned long companion_ports; /* which ports are 136 dedicated to the companion controller */ 137 138 /* per-HC memory pools (could be per-bus, but ...) */ 139 struct dma_pool *qh_pool; /* qh per active urb */ 140 struct dma_pool *qtd_pool; /* one or more per qh */ 141 struct dma_pool *itd_pool; /* itd per iso urb */ 142 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 143 144 struct timer_list watchdog; 145 unsigned long actions; 146 unsigned stamp; 147 unsigned long next_statechange; 148 u32 command; 149 150 /* SILICON QUIRKS */ 151 unsigned is_tdi_rh_tt:1; /* TDI roothub with TT */ 152 unsigned no_selective_suspend:1; 153 unsigned has_fsl_port_bug:1; /* FreeScale */ 154 unsigned big_endian_mmio:1; 155 156 u8 sbrn; /* packed release number */ 157 158#ifdef EHCI_QTD_CACHE 159 int qtdc_pid; 160 int qtdc_vid; 161 struct usb_device *qtdc_dev; /* matched qtdc dev pointer */ 162 ehci_qtdc_t* qtdc[NUM_QTD_CACHE]; 163 struct timer_list qtdc_watchdog; 164#endif /* EHCI_QTD_CACHE */ 165 166 /* irq statistics */ 167#ifdef EHCI_STATS 168 struct ehci_stats stats; 169# define COUNT(x) do { (x)++; } while (0) 170#else 171# define COUNT(x) do {} while (0) 172#endif 173 /* EHCI fastpath acceleration */ 174 struct usb_device *bypass_device; 175 struct ehci_qh *ehci_pipes[3]; /* pointer to ep location with qh address */ 176 void (*ehci_bypass_callback)(int pipeindex, struct ehci_qh *, spinlock_t *lock); 177 struct dma_pool *fastpath_pool; /* fastpath qtd pool */ 178}; 179 180/* convert between an HCD pointer and the corresponding EHCI_HCD */ 181static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 182{ 183 return (struct ehci_hcd *) (hcd->hcd_priv); 184} 185static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 186{ 187 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 188} 189 190 191enum ehci_timer_action { 192 TIMER_IO_WATCHDOG, 193 TIMER_IAA_WATCHDOG, 194 TIMER_ASYNC_SHRINK, 195 TIMER_ASYNC_OFF, 196}; 197 198static inline void 199timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 200{ 201 clear_bit (action, &ehci->actions); 202} 203 204static inline void 205timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action) 206{ 207 if (!test_and_set_bit (action, &ehci->actions)) { 208 unsigned long t; 209 210 switch (action) { 211 case TIMER_IAA_WATCHDOG: 212 t = EHCI_IAA_JIFFIES; 213 break; 214 case TIMER_IO_WATCHDOG: 215 t = EHCI_IO_JIFFIES; 216 break; 217 case TIMER_ASYNC_OFF: 218 t = EHCI_ASYNC_JIFFIES; 219 break; 220 // case TIMER_ASYNC_SHRINK: 221 default: 222 t = EHCI_SHRINK_JIFFIES; 223 break; 224 } 225 t += jiffies; 226 // all timings except IAA watchdog can be overridden. 227 // async queue SHRINK often precedes IAA. while it's ready 228 // to go OFF neither can matter, and afterwards the IO 229 // watchdog stops unless there's still periodic traffic. 230 if (action != TIMER_IAA_WATCHDOG 231 && t > ehci->watchdog.expires 232 && timer_pending (&ehci->watchdog)) 233 return; 234 mod_timer (&ehci->watchdog, t); 235 } 236} 237 238/*-------------------------------------------------------------------------*/ 239 240/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ 241 242/* Section 2.2 Host Controller Capability Registers */ 243struct ehci_caps { 244 /* these fields are specified as 8 and 16 bit registers, 245 * but some hosts can't perform 8 or 16 bit PCI accesses. 246 */ 247 u32 hc_capbase; 248#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ 249#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ 250 u32 hcs_params; /* HCSPARAMS - offset 0x4 */ 251#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ 252#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ 253#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ 254#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ 255#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ 256#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 257#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ 258 259 u32 hcc_params; /* HCCPARAMS - offset 0x8 */ 260#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ 261#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ 262#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ 263#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ 264#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ 265#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ 266 u8 portroute [8]; /* nibbles for routing - offset 0xC */ 267} __attribute__ ((packed)); 268 269 270/* Section 2.3 Host Controller Operational Registers */ 271struct ehci_regs { 272 273 /* USBCMD: offset 0x00 */ 274 u32 command; 275/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ 276#define CMD_PARK (1<<11) /* enable "park" on async qh */ 277#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ 278#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ 279#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ 280#define CMD_ASE (1<<5) /* async schedule enable */ 281#define CMD_PSE (1<<4) /* periodic schedule enable */ 282/* 3:2 is periodic frame list size */ 283#define CMD_RESET (1<<1) /* reset HC not bus */ 284#define CMD_RUN (1<<0) /* start/stop HC */ 285 286 /* USBSTS: offset 0x04 */ 287 u32 status; 288#define STS_ASS (1<<15) /* Async Schedule Status */ 289#define STS_PSS (1<<14) /* Periodic Schedule Status */ 290#define STS_RECL (1<<13) /* Reclamation */ 291#define STS_HALT (1<<12) /* Not running (any reason) */ 292/* some bits reserved */ 293 /* these STS_* flags are also intr_enable bits (USBINTR) */ 294#define STS_IAA (1<<5) /* Interrupted on async advance */ 295#define STS_FATAL (1<<4) /* such as some PCI access errors */ 296#define STS_FLR (1<<3) /* frame list rolled over */ 297#define STS_PCD (1<<2) /* port change detect */ 298#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ 299#define STS_INT (1<<0) /* "normal" completion (short, ...) */ 300 301 /* USBINTR: offset 0x08 */ 302 u32 intr_enable; 303 304 /* FRINDEX: offset 0x0C */ 305 u32 frame_index; /* current microframe number */ 306 /* CTRLDSSEGMENT: offset 0x10 */ 307 u32 segment; /* address bits 63:32 if needed */ 308 /* PERIODICLISTBASE: offset 0x14 */ 309 u32 frame_list; /* points to periodic list */ 310 /* ASYNCLISTADDR: offset 0x18 */ 311 u32 async_next; /* address of next async queue head */ 312 313 u32 reserved [9]; 314 315 /* CONFIGFLAG: offset 0x40 */ 316 u32 configured_flag; 317#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ 318 319 /* PORTSC: offset 0x44 */ 320 u32 port_status [0]; /* up to N_PORTS */ 321/* 31:23 reserved */ 322#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ 323#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ 324#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ 325/* 19:16 for port testing */ 326#define PORT_LED_OFF (0<<14) 327#define PORT_LED_AMBER (1<<14) 328#define PORT_LED_GREEN (2<<14) 329#define PORT_LED_MASK (3<<14) 330#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ 331#define PORT_POWER (1<<12) /* true: has power (see PPC) */ 332#define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */ 333/* 11:10 for detecting lowspeed devices (reset vs release ownership) */ 334#define PORT_LINE_STATUS (3<<10) 335/* 9 reserved */ 336#define PORT_RESET (1<<8) /* reset port */ 337#define PORT_SUSPEND (1<<7) /* suspend port */ 338#define PORT_RESUME (1<<6) /* resume it */ 339#define PORT_OCC (1<<5) /* over current change */ 340#define PORT_OC (1<<4) /* over current active */ 341#define PORT_PEC (1<<3) /* port enable change */ 342#define PORT_PE (1<<2) /* port enable */ 343#define PORT_CSC (1<<1) /* connect status change */ 344#define PORT_CONNECT (1<<0) /* device connected */ 345#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) 346} __attribute__ ((packed)); 347 348/* Appendix C, Debug port ... intended for use with special "debug devices" 349 * that can help if there's no serial console. (nonstandard enumeration.) 350 */ 351struct ehci_dbg_port { 352 u32 control; 353#define DBGP_OWNER (1<<30) 354#define DBGP_ENABLED (1<<28) 355#define DBGP_DONE (1<<16) 356#define DBGP_INUSE (1<<10) 357#define DBGP_ERRCODE(x) (((x)>>7)&0x07) 358# define DBGP_ERR_BAD 1 359# define DBGP_ERR_SIGNAL 2 360#define DBGP_ERROR (1<<6) 361#define DBGP_GO (1<<5) 362#define DBGP_OUT (1<<4) 363#define DBGP_LEN(x) (((x)>>0)&0x0f) 364 u32 pids; 365#define DBGP_PID_GET(x) (((x)>>16)&0xff) 366#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok)) 367 u32 data03; 368 u32 data47; 369 u32 address; 370#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep)) 371} __attribute__ ((packed)); 372 373/*-------------------------------------------------------------------------*/ 374 375#define QTD_NEXT(dma) cpu_to_le32((u32)dma) 376 377/* 378 * EHCI Specification 0.95 Section 3.5 379 * QTD: describe data transfer components (buffer, direction, ...) 380 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 381 * 382 * These are associated only with "QH" (Queue Head) structures, 383 * used with control, bulk, and interrupt transfers. 384 */ 385struct ehci_qtd { 386 /* first part defined by EHCI spec */ 387 __le32 hw_next; /* see EHCI 3.5.1 */ 388 __le32 hw_alt_next; /* see EHCI 3.5.2 */ 389 __le32 hw_token; /* see EHCI 3.5.3 */ 390#define QTD_TOGGLE (1 << 31) /* data toggle */ 391#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 392#define QTD_IOC (1 << 15) /* interrupt on complete */ 393#define QTD_CERR(tok) (((tok)>>10) & 0x3) 394#define QTD_PID(tok) (((tok)>>8) & 0x3) 395#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 396#define QTD_STS_HALT (1 << 6) /* halted on error */ 397#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 398#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 399#define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 400#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 401#define QTD_STS_STS (1 << 1) /* split transaction state */ 402#define QTD_STS_PING (1 << 0) /* issue PING? */ 403 __le32 hw_buf [5]; /* see EHCI 3.5.4 */ 404 __le32 hw_buf_hi [5]; /* Appendix B */ 405 406 /* the rest is HCD-private */ 407 dma_addr_t qtd_dma; /* qtd address */ 408 struct list_head qtd_list; /* sw qtd list */ 409 struct urb *urb; /* qtd's urb */ 410 size_t length; /* length of buffer */ 411} __attribute__ ((aligned (32))); 412 413/* mask NakCnt+T in qh->hw_alt_next */ 414#define QTD_MASK __constant_cpu_to_le32 (~0x1f) 415 416#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 417 418/*-------------------------------------------------------------------------*/ 419 420/* type tag from {qh,itd,sitd,fstn}->hw_next */ 421#define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1)) 422 423/* values for that type tag */ 424#define Q_TYPE_ITD __constant_cpu_to_le32 (0 << 1) 425#define Q_TYPE_QH __constant_cpu_to_le32 (1 << 1) 426#define Q_TYPE_SITD __constant_cpu_to_le32 (2 << 1) 427#define Q_TYPE_FSTN __constant_cpu_to_le32 (3 << 1) 428 429/* next async queue entry, or pointer to interrupt/periodic QH */ 430#define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH) 431 432/* for periodic/async schedules and qtd lists, mark end of list */ 433#define EHCI_LIST_END __constant_cpu_to_le32(1) /* "null pointer" to hw */ 434 435/* 436 * Entries in periodic shadow table are pointers to one of four kinds 437 * of data structure. That's dictated by the hardware; a type tag is 438 * encoded in the low bits of the hardware's periodic schedule. Use 439 * Q_NEXT_TYPE to get the tag. 440 * 441 * For entries in the async schedule, the type tag always says "qh". 442 */ 443union ehci_shadow { 444 struct ehci_qh *qh; /* Q_TYPE_QH */ 445 struct ehci_itd *itd; /* Q_TYPE_ITD */ 446 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 447 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 448 __le32 *hw_next; /* (all types) */ 449 void *ptr; 450}; 451 452/*-------------------------------------------------------------------------*/ 453 454/* 455 * EHCI Specification 0.95 Section 3.6 456 * QH: describes control/bulk/interrupt endpoints 457 * See Fig 3-7 "Queue Head Structure Layout". 458 * 459 * These appear in both the async and (for interrupt) periodic schedules. 460 */ 461 462struct ehci_qh { 463 /* first part defined by EHCI spec */ 464 __le32 hw_next; /* see EHCI 3.6.1 */ 465 __le32 hw_info1; /* see EHCI 3.6.2 */ 466#define QH_HEAD 0x00008000 467 __le32 hw_info2; /* see EHCI 3.6.2 */ 468#define QH_SMASK 0x000000ff 469#define QH_CMASK 0x0000ff00 470#define QH_HUBADDR 0x007f0000 471#define QH_HUBPORT 0x3f800000 472#define QH_MULT 0xc0000000 473 __le32 hw_current; /* qtd list - see EHCI 3.6.4 */ 474 475 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 476 __le32 hw_qtd_next; 477 __le32 hw_alt_next; 478 __le32 hw_token; 479 __le32 hw_buf [5]; 480 __le32 hw_buf_hi [5]; 481 482 /* the rest is HCD-private */ 483 dma_addr_t qh_dma; /* address of qh */ 484 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 485 struct list_head qtd_list; /* sw qtd list */ 486 struct ehci_qtd *dummy; 487 struct ehci_qh *reclaim; /* next to reclaim */ 488 489 struct ehci_hcd *ehci; 490 struct kref kref; 491 unsigned stamp; 492 493 u8 qh_state; 494#define QH_STATE_LINKED 1 /* HC sees this */ 495#define QH_STATE_UNLINK 2 /* HC may still see this */ 496#define QH_STATE_IDLE 3 /* HC doesn't see this */ 497#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 498#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 499#define QH_STATE_DETACHED 6 /* detached for optimization */ 500 501 /* periodic schedule info */ 502 u8 usecs; /* intr bandwidth */ 503 u8 gap_uf; /* uframes split/csplit gap */ 504 u8 c_usecs; /* ... split completion bw */ 505 u16 tt_usecs; /* tt downstream bandwidth */ 506 unsigned short period; /* polling interval */ 507 unsigned short start; /* where polling starts */ 508#define NO_FRAME ((unsigned short)~0) /* pick new start */ 509 struct usb_device *dev; /* access to TT */ 510 struct ehci_qtd *first_qtd; /* optimized equivalent of the qtd_list */ 511} __attribute__ ((aligned (32))); 512 513/*-------------------------------------------------------------------------*/ 514 515/* description of one iso transaction (up to 3 KB data if highspeed) */ 516struct ehci_iso_packet { 517 /* These will be copied to iTD when scheduling */ 518 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 519 __le32 transaction; /* itd->hw_transaction[i] |= */ 520 u8 cross; /* buf crosses pages */ 521 /* for full speed OUT splits */ 522 u32 buf1; 523}; 524 525/* temporary schedule data for packets from iso urbs (both speeds) 526 * each packet is one logical usb transaction to the device (not TT), 527 * beginning at stream->next_uframe 528 */ 529struct ehci_iso_sched { 530 struct list_head td_list; 531 unsigned span; 532 struct ehci_iso_packet packet [0]; 533}; 534 535/* 536 * ehci_iso_stream - groups all (s)itds for this endpoint. 537 * acts like a qh would, if EHCI had them for ISO. 538 */ 539struct ehci_iso_stream { 540 /* first two fields match QH, but info1 == 0 */ 541 __le32 hw_next; 542 __le32 hw_info1; 543 544 u32 refcount; 545 u8 bEndpointAddress; 546 u8 highspeed; 547 u16 depth; /* depth in uframes */ 548 struct list_head td_list; /* queued itds/sitds */ 549 struct list_head free_list; /* list of unused itds/sitds */ 550 struct usb_device *udev; 551 struct usb_host_endpoint *ep; 552 553 /* output of (re)scheduling */ 554 unsigned long start; /* jiffies */ 555 unsigned long rescheduled; 556 int next_uframe; 557 __le32 splits; 558 559 /* the rest is derived from the endpoint descriptor, 560 * trusting urb->interval == f(epdesc->bInterval) and 561 * including the extra info for hw_bufp[0..2] 562 */ 563 u8 interval; 564 u8 usecs, c_usecs; 565 u16 tt_usecs; 566 u16 maxp; 567 u16 raw_mask; 568 unsigned bandwidth; 569 570 /* This is used to initialize iTD's hw_bufp fields */ 571 __le32 buf0; 572 __le32 buf1; 573 __le32 buf2; 574 575 /* this is used to initialize sITD's tt info */ 576 __le32 address; 577}; 578 579/*-------------------------------------------------------------------------*/ 580 581/* 582 * EHCI Specification 0.95 Section 3.3 583 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 584 * 585 * Schedule records for high speed iso xfers 586 */ 587struct ehci_itd { 588 /* first part defined by EHCI spec */ 589 __le32 hw_next; /* see EHCI 3.3.1 */ 590 __le32 hw_transaction [8]; /* see EHCI 3.3.2 */ 591#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 592#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 593#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 594#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 595#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 596#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 597 598#define ITD_ACTIVE __constant_cpu_to_le32(EHCI_ISOC_ACTIVE) 599 600 __le32 hw_bufp [7]; /* see EHCI 3.3.3 */ 601 __le32 hw_bufp_hi [7]; /* Appendix B */ 602 603 /* the rest is HCD-private */ 604 dma_addr_t itd_dma; /* for this itd */ 605 union ehci_shadow itd_next; /* ptr to periodic q entry */ 606 607 struct urb *urb; 608 struct ehci_iso_stream *stream; /* endpoint's queue */ 609 struct list_head itd_list; /* list of stream's itds */ 610 611 /* any/all hw_transactions here may be used by that urb */ 612 unsigned frame; /* where scheduled */ 613 unsigned pg; 614 unsigned index[8]; /* in urb->iso_frame_desc */ 615 u8 usecs[8]; 616} __attribute__ ((aligned (32))); 617 618/*-------------------------------------------------------------------------*/ 619 620/* 621 * EHCI Specification 0.95 Section 3.4 622 * siTD, aka split-transaction isochronous Transfer Descriptor 623 * ... describe full speed iso xfers through TT in hubs 624 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 625 */ 626struct ehci_sitd { 627 /* first part defined by EHCI spec */ 628 __le32 hw_next; 629/* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 630 __le32 hw_fullspeed_ep; /* EHCI table 3-9 */ 631 __le32 hw_uframe; /* EHCI table 3-10 */ 632 __le32 hw_results; /* EHCI table 3-11 */ 633#define SITD_IOC (1 << 31) /* interrupt on completion */ 634#define SITD_PAGE (1 << 30) /* buffer 0/1 */ 635#define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 636#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 637#define SITD_STS_ERR (1 << 6) /* error from TT */ 638#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 639#define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 640#define SITD_STS_XACT (1 << 3) /* illegal IN response */ 641#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 642#define SITD_STS_STS (1 << 1) /* split transaction state */ 643 644#define SITD_ACTIVE __constant_cpu_to_le32(SITD_STS_ACTIVE) 645 646 __le32 hw_buf [2]; /* EHCI table 3-12 */ 647 __le32 hw_backpointer; /* EHCI table 3-13 */ 648 __le32 hw_buf_hi [2]; /* Appendix B */ 649 650 /* the rest is HCD-private */ 651 dma_addr_t sitd_dma; 652 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 653 654 struct urb *urb; 655 struct ehci_iso_stream *stream; /* endpoint's queue */ 656 struct list_head sitd_list; /* list of stream's sitds */ 657 unsigned frame; 658 unsigned index; 659} __attribute__ ((aligned (32))); 660 661/*-------------------------------------------------------------------------*/ 662 663/* 664 * EHCI Specification 0.96 Section 3.7 665 * Periodic Frame Span Traversal Node (FSTN) 666 * 667 * Manages split interrupt transactions (using TT) that span frame boundaries 668 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 669 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 670 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 671 */ 672struct ehci_fstn { 673 __le32 hw_next; /* any periodic q entry */ 674 __le32 hw_prev; /* qh or EHCI_LIST_END */ 675 676 /* the rest is HCD-private */ 677 dma_addr_t fstn_dma; 678 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 679} __attribute__ ((aligned (32))); 680 681/*-------------------------------------------------------------------------*/ 682 683#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 684 685/* 686 * Some EHCI controllers have a Transaction Translator built into the 687 * root hub. This is a non-standard feature. Each controller will need 688 * to add code to the following inline functions, and call them as 689 * needed (mostly in root hub code). 690 */ 691 692#define ehci_is_TDI(e) ((e)->is_tdi_rh_tt) 693 694/* Returns the speed of a device attached to a port on the root hub. */ 695static inline unsigned int 696ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 697{ 698 if (ehci_is_TDI(ehci)) { 699 switch ((portsc>>26)&3) { 700 case 0: 701 return 0; 702 case 1: 703 return (1<<USB_PORT_FEAT_LOWSPEED); 704 case 2: 705 default: 706 return (1<<USB_PORT_FEAT_HIGHSPEED); 707 } 708 } 709 return (1<<USB_PORT_FEAT_HIGHSPEED); 710} 711 712#else 713 714#define ehci_is_TDI(e) (0) 715 716#define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED) 717#endif 718 719/*-------------------------------------------------------------------------*/ 720 721#ifdef CONFIG_PPC_83xx 722/* Some Freescale processors have an erratum in which the TT 723 * port number in the queue head was 0..N-1 instead of 1..N. 724 */ 725#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 726#else 727#define ehci_has_fsl_portno_bug(e) (0) 728#endif 729 730/* 731 * While most USB host controllers implement their registers in 732 * little-endian format, a minority (celleb companion chip) implement 733 * them in big endian format. 734 * 735 * This attempts to support either format at compile time without a 736 * runtime penalty, or both formats with the additional overhead 737 * of checking a flag bit. 738 */ 739 740#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 741#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 742#else 743#define ehci_big_endian_mmio(e) 0 744#endif 745 746static inline unsigned int ehci_readl (const struct ehci_hcd *ehci, 747 __u32 __iomem * regs) 748{ 749#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 750 return ehci_big_endian_mmio(ehci) ? 751 readl_be(regs) : 752 readl(regs); 753#else 754 return readl(regs); 755#endif 756} 757 758static inline void ehci_writel (const struct ehci_hcd *ehci, 759 const unsigned int val, __u32 __iomem *regs) 760{ 761#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 762 ehci_big_endian_mmio(ehci) ? 763 writel_be(val, regs) : 764 writel(val, regs); 765#else 766 writel(val, regs); 767#endif 768} 769 770/*-------------------------------------------------------------------------*/ 771 772#ifndef DEBUG 773#define STUB_DEBUG_FILES 774#endif /* DEBUG */ 775 776/*-------------------------------------------------------------------------*/ 777 778/* EHCI fastpath acceleration */ 779#define EHCI_FASTPATH 0x31 780#define EHCI_SET_EP_BYPASS (0x4300 | EHCI_FASTPATH) 781#define EHCI_SET_BYPASS_CB (0x4300 | (EHCI_FASTPATH+1)) 782#define EHCI_SET_BYPASS_DEV (0x4300 | (EHCI_FASTPATH+2)) 783#define EHCI_DUMP_STATE (0x4300 | (EHCI_FASTPATH+3)) 784#define EHCI_SET_BYPASS_POOL (0x4300 | (EHCI_FASTPATH+4)) 785#define EHCI_CLR_EP_BYPASS (0x4300 | (EHCI_FASTPATH+5)) 786 787#endif /* __LINUX_EHCI_HCD_H */ 788