1/************************************************************************ 2 * Copyright 2003 Digi International (www.digi.com) 3 * 4 * Copyright (C) 2004 IBM Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 14 * PURPOSE. See the GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston, 19 * MA 02111-1307, USA. 20 * 21 * Contact Information: 22 * Scott H Kilau <Scott_Kilau@digi.com> 23 * Wendy Xiong <wendyx@us.ibm.com> 24 * 25 ***********************************************************************/ 26#include <linux/delay.h> /* For udelay */ 27#include <linux/serial_reg.h> /* For the various UART offsets */ 28#include <linux/tty.h> 29#include <linux/pci.h> 30#include <asm/io.h> 31 32#include "jsm.h" /* Driver main header file */ 33 34static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; 35 36/* 37 * This function allows calls to ensure that all outstanding 38 * PCI writes have been completed, by doing a PCI read against 39 * a non-destructive, read-only location on the Neo card. 40 * 41 * In this case, we are reading the DVID (Read-only Device Identification) 42 * value of the Neo card. 43 */ 44static inline void neo_pci_posting_flush(struct jsm_board *bd) 45{ 46 readb(bd->re_map_membase + 0x8D); 47} 48 49static void neo_set_cts_flow_control(struct jsm_channel *ch) 50{ 51 u8 ier, efr; 52 ier = readb(&ch->ch_neo_uart->ier); 53 efr = readb(&ch->ch_neo_uart->efr); 54 55 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); 56 57 /* Turn on auto CTS flow control */ 58 ier |= (UART_17158_IER_CTSDSR); 59 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR); 60 61 /* Turn off auto Xon flow control */ 62 efr &= ~(UART_17158_EFR_IXON); 63 64 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 65 writeb(0, &ch->ch_neo_uart->efr); 66 67 /* Turn on UART enhanced bits */ 68 writeb(efr, &ch->ch_neo_uart->efr); 69 70 /* Turn on table D, with 8 char hi/low watermarks */ 71 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 72 73 /* Feed the UART our trigger levels */ 74 writeb(8, &ch->ch_neo_uart->tfifo); 75 ch->ch_t_tlevel = 8; 76 77 writeb(ier, &ch->ch_neo_uart->ier); 78} 79 80static void neo_set_rts_flow_control(struct jsm_channel *ch) 81{ 82 u8 ier, efr; 83 ier = readb(&ch->ch_neo_uart->ier); 84 efr = readb(&ch->ch_neo_uart->efr); 85 86 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n"); 87 88 /* Turn on auto RTS flow control */ 89 ier |= (UART_17158_IER_RTSDTR); 90 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR); 91 92 /* Turn off auto Xoff flow control */ 93 ier &= ~(UART_17158_IER_XOFF); 94 efr &= ~(UART_17158_EFR_IXOFF); 95 96 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 97 writeb(0, &ch->ch_neo_uart->efr); 98 99 /* Turn on UART enhanced bits */ 100 writeb(efr, &ch->ch_neo_uart->efr); 101 102 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 103 ch->ch_r_watermark = 4; 104 105 writeb(56, &ch->ch_neo_uart->rfifo); 106 ch->ch_r_tlevel = 56; 107 108 writeb(ier, &ch->ch_neo_uart->ier); 109 110 /* 111 * From the Neo UART spec sheet: 112 * The auto RTS/DTR function must be started by asserting 113 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after 114 * it is enabled. 115 */ 116 ch->ch_mostat |= (UART_MCR_RTS); 117} 118 119 120static void neo_set_ixon_flow_control(struct jsm_channel *ch) 121{ 122 u8 ier, efr; 123 ier = readb(&ch->ch_neo_uart->ier); 124 efr = readb(&ch->ch_neo_uart->efr); 125 126 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n"); 127 128 /* Turn off auto CTS flow control */ 129 ier &= ~(UART_17158_IER_CTSDSR); 130 efr &= ~(UART_17158_EFR_CTSDSR); 131 132 /* Turn on auto Xon flow control */ 133 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON); 134 135 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 136 writeb(0, &ch->ch_neo_uart->efr); 137 138 /* Turn on UART enhanced bits */ 139 writeb(efr, &ch->ch_neo_uart->efr); 140 141 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 142 ch->ch_r_watermark = 4; 143 144 writeb(32, &ch->ch_neo_uart->rfifo); 145 ch->ch_r_tlevel = 32; 146 147 /* Tell UART what start/stop chars it should be looking for */ 148 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 149 writeb(0, &ch->ch_neo_uart->xonchar2); 150 151 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 152 writeb(0, &ch->ch_neo_uart->xoffchar2); 153 154 writeb(ier, &ch->ch_neo_uart->ier); 155} 156 157static void neo_set_ixoff_flow_control(struct jsm_channel *ch) 158{ 159 u8 ier, efr; 160 ier = readb(&ch->ch_neo_uart->ier); 161 efr = readb(&ch->ch_neo_uart->efr); 162 163 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n"); 164 165 /* Turn off auto RTS flow control */ 166 ier &= ~(UART_17158_IER_RTSDTR); 167 efr &= ~(UART_17158_EFR_RTSDTR); 168 169 /* Turn on auto Xoff flow control */ 170 ier |= (UART_17158_IER_XOFF); 171 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 172 173 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 174 writeb(0, &ch->ch_neo_uart->efr); 175 176 /* Turn on UART enhanced bits */ 177 writeb(efr, &ch->ch_neo_uart->efr); 178 179 /* Turn on table D, with 8 char hi/low watermarks */ 180 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 181 182 writeb(8, &ch->ch_neo_uart->tfifo); 183 ch->ch_t_tlevel = 8; 184 185 /* Tell UART what start/stop chars it should be looking for */ 186 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 187 writeb(0, &ch->ch_neo_uart->xonchar2); 188 189 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 190 writeb(0, &ch->ch_neo_uart->xoffchar2); 191 192 writeb(ier, &ch->ch_neo_uart->ier); 193} 194 195static void neo_set_no_input_flow_control(struct jsm_channel *ch) 196{ 197 u8 ier, efr; 198 ier = readb(&ch->ch_neo_uart->ier); 199 efr = readb(&ch->ch_neo_uart->efr); 200 201 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n"); 202 203 /* Turn off auto RTS flow control */ 204 ier &= ~(UART_17158_IER_RTSDTR); 205 efr &= ~(UART_17158_EFR_RTSDTR); 206 207 /* Turn off auto Xoff flow control */ 208 ier &= ~(UART_17158_IER_XOFF); 209 if (ch->ch_c_iflag & IXON) 210 efr &= ~(UART_17158_EFR_IXOFF); 211 else 212 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 213 214 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 215 writeb(0, &ch->ch_neo_uart->efr); 216 217 /* Turn on UART enhanced bits */ 218 writeb(efr, &ch->ch_neo_uart->efr); 219 220 /* Turn on table D, with 8 char hi/low watermarks */ 221 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 222 223 ch->ch_r_watermark = 0; 224 225 writeb(16, &ch->ch_neo_uart->tfifo); 226 ch->ch_t_tlevel = 16; 227 228 writeb(16, &ch->ch_neo_uart->rfifo); 229 ch->ch_r_tlevel = 16; 230 231 writeb(ier, &ch->ch_neo_uart->ier); 232} 233 234static void neo_set_no_output_flow_control(struct jsm_channel *ch) 235{ 236 u8 ier, efr; 237 ier = readb(&ch->ch_neo_uart->ier); 238 efr = readb(&ch->ch_neo_uart->efr); 239 240 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n"); 241 242 /* Turn off auto CTS flow control */ 243 ier &= ~(UART_17158_IER_CTSDSR); 244 efr &= ~(UART_17158_EFR_CTSDSR); 245 246 /* Turn off auto Xon flow control */ 247 if (ch->ch_c_iflag & IXOFF) 248 efr &= ~(UART_17158_EFR_IXON); 249 else 250 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON); 251 252 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 253 writeb(0, &ch->ch_neo_uart->efr); 254 255 /* Turn on UART enhanced bits */ 256 writeb(efr, &ch->ch_neo_uart->efr); 257 258 /* Turn on table D, with 8 char hi/low watermarks */ 259 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 260 261 ch->ch_r_watermark = 0; 262 263 writeb(16, &ch->ch_neo_uart->tfifo); 264 ch->ch_t_tlevel = 16; 265 266 writeb(16, &ch->ch_neo_uart->rfifo); 267 ch->ch_r_tlevel = 16; 268 269 writeb(ier, &ch->ch_neo_uart->ier); 270} 271 272static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch) 273{ 274 275 /* if hardware flow control is set, then skip this whole thing */ 276 if (ch->ch_c_cflag & CRTSCTS) 277 return; 278 279 jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "start\n"); 280 281 /* Tell UART what start/stop chars it should be looking for */ 282 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 283 writeb(0, &ch->ch_neo_uart->xonchar2); 284 285 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 286 writeb(0, &ch->ch_neo_uart->xoffchar2); 287} 288 289static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch) 290{ 291 int qleft = 0; 292 u8 linestatus = 0; 293 u8 error_mask = 0; 294 int n = 0; 295 int total = 0; 296 u16 head; 297 u16 tail; 298 299 if (!ch) 300 return; 301 302 /* cache head and tail of queue */ 303 head = ch->ch_r_head & RQUEUEMASK; 304 tail = ch->ch_r_tail & RQUEUEMASK; 305 306 /* Get our cached LSR */ 307 linestatus = ch->ch_cached_lsr; 308 ch->ch_cached_lsr = 0; 309 310 /* Store how much space we have left in the queue */ 311 if ((qleft = tail - head - 1) < 0) 312 qleft += RQUEUEMASK + 1; 313 314 /* 315 * If the UART is not in FIFO mode, force the FIFO copy to 316 * NOT be run, by setting total to 0. 317 * 318 * On the other hand, if the UART IS in FIFO mode, then ask 319 * the UART to give us an approximation of data it has RX'ed. 320 */ 321 if (!(ch->ch_flags & CH_FIFO_ENABLED)) 322 total = 0; 323 else { 324 total = readb(&ch->ch_neo_uart->rfifo); 325 326 /* 327 * EXAR chip bug - RX FIFO COUNT - Fudge factor. 328 * 329 * This resolves a problem/bug with the Exar chip that sometimes 330 * returns a bogus value in the rfifo register. 331 * The count can be any where from 0-3 bytes "off". 332 * Bizarre, but true. 333 */ 334 total -= 3; 335 } 336 337 /* 338 * Finally, bound the copy to make sure we don't overflow 339 * our own queue... 340 * The byte by byte copy loop below this loop this will 341 * deal with the queue overflow possibility. 342 */ 343 total = min(total, qleft); 344 345 while (total > 0) { 346 /* 347 * Grab the linestatus register, we need to check 348 * to see if there are any errors in the FIFO. 349 */ 350 linestatus = readb(&ch->ch_neo_uart->lsr); 351 352 /* 353 * Break out if there is a FIFO error somewhere. 354 * This will allow us to go byte by byte down below, 355 * finding the exact location of the error. 356 */ 357 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 358 break; 359 360 /* Make sure we don't go over the end of our queue */ 361 n = min(((u32) total), (RQUEUESIZE - (u32) head)); 362 363 /* 364 * Cut down n even further if needed, this is to fix 365 * a problem with memcpy_fromio() with the Neo on the 366 * IBM pSeries platform. 367 * 15 bytes max appears to be the magic number. 368 */ 369 n = min((u32) n, (u32) 12); 370 371 /* 372 * Since we are grabbing the linestatus register, which 373 * will reset some bits after our read, we need to ensure 374 * we don't miss our TX FIFO emptys. 375 */ 376 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) 377 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 378 379 linestatus = 0; 380 381 /* Copy data from uart to the queue */ 382 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n); 383 /* 384 * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed 385 * that all the data currently in the FIFO is free of 386 * breaks and parity/frame/orun errors. 387 */ 388 memset(ch->ch_equeue + head, 0, n); 389 390 /* Add to and flip head if needed */ 391 head = (head + n) & RQUEUEMASK; 392 total -= n; 393 qleft -= n; 394 ch->ch_rxcount += n; 395 } 396 397 /* 398 * Create a mask to determine whether we should 399 * insert the character (if any) into our queue. 400 */ 401 if (ch->ch_c_iflag & IGNBRK) 402 error_mask |= UART_LSR_BI; 403 404 /* 405 * Now cleanup any leftover bytes still in the UART. 406 * Also deal with any possible queue overflow here as well. 407 */ 408 while (1) { 409 410 /* 411 * Its possible we have a linestatus from the loop above 412 * this, so we "OR" on any extra bits. 413 */ 414 linestatus |= readb(&ch->ch_neo_uart->lsr); 415 416 /* 417 * If the chip tells us there is no more data pending to 418 * be read, we can then leave. 419 * But before we do, cache the linestatus, just in case. 420 */ 421 if (!(linestatus & UART_LSR_DR)) { 422 ch->ch_cached_lsr = linestatus; 423 break; 424 } 425 426 /* No need to store this bit */ 427 linestatus &= ~UART_LSR_DR; 428 429 /* 430 * Since we are grabbing the linestatus register, which 431 * will reset some bits after our read, we need to ensure 432 * we don't miss our TX FIFO emptys. 433 */ 434 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) { 435 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR); 436 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 437 } 438 439 /* 440 * Discard character if we are ignoring the error mask. 441 */ 442 if (linestatus & error_mask) { 443 u8 discard; 444 linestatus = 0; 445 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1); 446 continue; 447 } 448 449 /* 450 * If our queue is full, we have no choice but to drop some data. 451 * The assumption is that HWFLOW or SWFLOW should have stopped 452 * things way way before we got to this point. 453 * 454 * I decided that I wanted to ditch the oldest data first, 455 * I hope thats okay with everyone? Yes? Good. 456 */ 457 while (qleft < 1) { 458 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, 459 "Queue full, dropping DATA:%x LSR:%x\n", 460 ch->ch_rqueue[tail], ch->ch_equeue[tail]); 461 462 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK; 463 ch->ch_err_overrun++; 464 qleft++; 465 } 466 467 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1); 468 ch->ch_equeue[head] = (u8) linestatus; 469 470 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, 471 "DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]); 472 473 /* Ditch any remaining linestatus value. */ 474 linestatus = 0; 475 476 /* Add to and flip head if needed */ 477 head = (head + 1) & RQUEUEMASK; 478 479 qleft--; 480 ch->ch_rxcount++; 481 } 482 483 /* 484 * Write new final heads to channel structure. 485 */ 486 ch->ch_r_head = head & RQUEUEMASK; 487 ch->ch_e_head = head & EQUEUEMASK; 488 jsm_input(ch); 489} 490 491static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch) 492{ 493 u16 head; 494 u16 tail; 495 int n; 496 int s; 497 int qlen; 498 u32 len_written = 0; 499 500 if (!ch) 501 return; 502 503 /* No data to write to the UART */ 504 if (ch->ch_w_tail == ch->ch_w_head) 505 return; 506 507 /* If port is "stopped", don't send any data to the UART */ 508 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) 509 return; 510 /* 511 * If FIFOs are disabled. Send data directly to txrx register 512 */ 513 if (!(ch->ch_flags & CH_FIFO_ENABLED)) { 514 u8 lsrbits = readb(&ch->ch_neo_uart->lsr); 515 516 ch->ch_cached_lsr |= lsrbits; 517 if (ch->ch_cached_lsr & UART_LSR_THRE) { 518 ch->ch_cached_lsr &= ~(UART_LSR_THRE); 519 520 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx); 521 jsm_printk(WRITE, INFO, &ch->ch_bd->pci_dev, 522 "Tx data: %x\n", ch->ch_wqueue[ch->ch_w_head]); 523 ch->ch_w_tail++; 524 ch->ch_w_tail &= WQUEUEMASK; 525 ch->ch_txcount++; 526 } 527 return; 528 } 529 530 /* 531 * We have to do it this way, because of the EXAR TXFIFO count bug. 532 */ 533 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) 534 return; 535 536 len_written = 0; 537 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; 538 539 /* cache head and tail of queue */ 540 head = ch->ch_w_head & WQUEUEMASK; 541 tail = ch->ch_w_tail & WQUEUEMASK; 542 qlen = (head - tail) & WQUEUEMASK; 543 544 /* Find minimum of the FIFO space, versus queue length */ 545 n = min(n, qlen); 546 547 while (n > 0) { 548 549 s = ((head >= tail) ? head : WQUEUESIZE) - tail; 550 s = min(s, n); 551 552 if (s <= 0) 553 break; 554 555 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s); 556 /* Add and flip queue if needed */ 557 tail = (tail + s) & WQUEUEMASK; 558 n -= s; 559 ch->ch_txcount += s; 560 len_written += s; 561 } 562 563 /* Update the final tail */ 564 ch->ch_w_tail = tail & WQUEUEMASK; 565 566 if (len_written >= ch->ch_t_tlevel) 567 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 568 569 if (!jsm_tty_write(&ch->uart_port)) 570 uart_write_wakeup(&ch->uart_port); 571} 572 573static void neo_parse_modem(struct jsm_channel *ch, u8 signals) 574{ 575 u8 msignals = signals; 576 577 jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev, 578 "neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals); 579 580 if (!ch) 581 return; 582 583 /* Scrub off lower bits. They signify delta's, which I don't care about */ 584 /* Keep DDCD and DDSR though */ 585 msignals &= 0xf8; 586 587 if (msignals & UART_MSR_DDCD) 588 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); 589 if (msignals & UART_MSR_DDSR) 590 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS); 591 if (msignals & UART_MSR_DCD) 592 ch->ch_mistat |= UART_MSR_DCD; 593 else 594 ch->ch_mistat &= ~UART_MSR_DCD; 595 596 if (msignals & UART_MSR_DSR) 597 ch->ch_mistat |= UART_MSR_DSR; 598 else 599 ch->ch_mistat &= ~UART_MSR_DSR; 600 601 if (msignals & UART_MSR_RI) 602 ch->ch_mistat |= UART_MSR_RI; 603 else 604 ch->ch_mistat &= ~UART_MSR_RI; 605 606 if (msignals & UART_MSR_CTS) 607 ch->ch_mistat |= UART_MSR_CTS; 608 else 609 ch->ch_mistat &= ~UART_MSR_CTS; 610 611 jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev, 612 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n", 613 ch->ch_portnum, 614 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), 615 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), 616 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), 617 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), 618 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), 619 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); 620} 621 622/* Make the UART raise any of the output signals we want up */ 623static void neo_assert_modem_signals(struct jsm_channel *ch) 624{ 625 u8 out; 626 627 if (!ch) 628 return; 629 630 out = ch->ch_mostat; 631 632 writeb(out, &ch->ch_neo_uart->mcr); 633 634 /* flush write operation */ 635 neo_pci_posting_flush(ch->ch_bd); 636} 637 638/* 639 * Flush the WRITE FIFO on the Neo. 640 * 641 * NOTE: Channel lock MUST be held before calling this function! 642 */ 643static void neo_flush_uart_write(struct jsm_channel *ch) 644{ 645 u8 tmp = 0; 646 int i = 0; 647 648 if (!ch) 649 return; 650 651 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 652 653 for (i = 0; i < 10; i++) { 654 655 /* Check to see if the UART feels it completely flushed the FIFO. */ 656 tmp = readb(&ch->ch_neo_uart->isr_fcr); 657 if (tmp & 4) { 658 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, 659 "Still flushing TX UART... i: %d\n", i); 660 udelay(10); 661 } 662 else 663 break; 664 } 665 666 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 667} 668 669 670/* 671 * Flush the READ FIFO on the Neo. 672 * 673 * NOTE: Channel lock MUST be held before calling this function! 674 */ 675static void neo_flush_uart_read(struct jsm_channel *ch) 676{ 677 u8 tmp = 0; 678 int i = 0; 679 680 if (!ch) 681 return; 682 683 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr); 684 685 for (i = 0; i < 10; i++) { 686 687 /* Check to see if the UART feels it completely flushed the FIFO. */ 688 tmp = readb(&ch->ch_neo_uart->isr_fcr); 689 if (tmp & 2) { 690 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, 691 "Still flushing RX UART... i: %d\n", i); 692 udelay(10); 693 } 694 else 695 break; 696 } 697} 698 699/* 700 * No locks are assumed to be held when calling this function. 701 */ 702static void neo_clear_break(struct jsm_channel *ch, int force) 703{ 704 unsigned long lock_flags; 705 706 spin_lock_irqsave(&ch->ch_lock, lock_flags); 707 708 /* Turn break off, and unset some variables */ 709 if (ch->ch_flags & CH_BREAK_SENDING) { 710 u8 temp = readb(&ch->ch_neo_uart->lcr); 711 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); 712 713 ch->ch_flags &= ~(CH_BREAK_SENDING); 714 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev, 715 "clear break Finishing UART_LCR_SBC! finished: %lx\n", jiffies); 716 717 /* flush write operation */ 718 neo_pci_posting_flush(ch->ch_bd); 719 } 720 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 721} 722 723/* 724 * Parse the ISR register. 725 */ 726static inline void neo_parse_isr(struct jsm_board *brd, u32 port) 727{ 728 struct jsm_channel *ch; 729 u8 isr; 730 u8 cause; 731 unsigned long lock_flags; 732 733 if (!brd) 734 return; 735 736 if (port > brd->maxports) 737 return; 738 739 ch = brd->channels[port]; 740 if (!ch) 741 return; 742 743 /* Here we try to figure out what caused the interrupt to happen */ 744 while (1) { 745 746 isr = readb(&ch->ch_neo_uart->isr_fcr); 747 748 /* Bail if no pending interrupt */ 749 if (isr & UART_IIR_NO_INT) 750 break; 751 752 /* 753 * Yank off the upper 2 bits, which just show that the FIFO's are enabled. 754 */ 755 isr &= ~(UART_17158_IIR_FIFO_ENABLED); 756 757 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 758 "%s:%d isr: %x\n", __FILE__, __LINE__, isr); 759 760 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) { 761 /* Read data from uart -> queue */ 762 neo_copy_data_from_uart_to_queue(ch); 763 764 /* Call our tty layer to enforce queue flow control if needed. */ 765 spin_lock_irqsave(&ch->ch_lock, lock_flags); 766 jsm_check_queue_flow_control(ch); 767 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 768 } 769 770 if (isr & UART_IIR_THRI) { 771 /* Transfer data (if any) from Write Queue -> UART. */ 772 spin_lock_irqsave(&ch->ch_lock, lock_flags); 773 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 774 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 775 neo_copy_data_from_queue_to_uart(ch); 776 } 777 778 if (isr & UART_17158_IIR_XONXOFF) { 779 cause = readb(&ch->ch_neo_uart->xoffchar1); 780 781 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 782 "Port %d. Got ISR_XONXOFF: cause:%x\n", port, cause); 783 784 /* 785 * Since the UART detected either an XON or 786 * XOFF match, we need to figure out which 787 * one it was, so we can suspend or resume data flow. 788 */ 789 spin_lock_irqsave(&ch->ch_lock, lock_flags); 790 if (cause == UART_17158_XON_DETECT) { 791 /* Is output stopped right now, if so, resume it */ 792 if (brd->channels[port]->ch_flags & CH_STOP) { 793 ch->ch_flags &= ~(CH_STOP); 794 } 795 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 796 "Port %d. XON detected in incoming data\n", port); 797 } 798 else if (cause == UART_17158_XOFF_DETECT) { 799 if (!(brd->channels[port]->ch_flags & CH_STOP)) { 800 ch->ch_flags |= CH_STOP; 801 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 802 "Setting CH_STOP\n"); 803 } 804 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 805 "Port: %d. XOFF detected in incoming data\n", port); 806 } 807 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 808 } 809 810 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) { 811 /* 812 * If we get here, this means the hardware is doing auto flow control. 813 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt. 814 */ 815 cause = readb(&ch->ch_neo_uart->mcr); 816 817 /* Which pin is doing auto flow? RTS or DTR? */ 818 spin_lock_irqsave(&ch->ch_lock, lock_flags); 819 if ((cause & 0x4) == 0) { 820 if (cause & UART_MCR_RTS) 821 ch->ch_mostat |= UART_MCR_RTS; 822 else 823 ch->ch_mostat &= ~(UART_MCR_RTS); 824 } else { 825 if (cause & UART_MCR_DTR) 826 ch->ch_mostat |= UART_MCR_DTR; 827 else 828 ch->ch_mostat &= ~(UART_MCR_DTR); 829 } 830 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 831 } 832 833 /* Parse any modem signal changes */ 834 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 835 "MOD_STAT: sending to parse_modem_sigs\n"); 836 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 837 } 838} 839 840static inline void neo_parse_lsr(struct jsm_board *brd, u32 port) 841{ 842 struct jsm_channel *ch; 843 int linestatus; 844 unsigned long lock_flags; 845 846 if (!brd) 847 return; 848 849 if (port > brd->maxports) 850 return; 851 852 ch = brd->channels[port]; 853 if (!ch) 854 return; 855 856 linestatus = readb(&ch->ch_neo_uart->lsr); 857 858 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev, 859 "%s:%d port: %d linestatus: %x\n", __FILE__, __LINE__, port, linestatus); 860 861 ch->ch_cached_lsr |= linestatus; 862 863 if (ch->ch_cached_lsr & UART_LSR_DR) { 864 /* Read data from uart -> queue */ 865 neo_copy_data_from_uart_to_queue(ch); 866 spin_lock_irqsave(&ch->ch_lock, lock_flags); 867 jsm_check_queue_flow_control(ch); 868 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 869 } 870 871 /* 872 * This is a special flag. It indicates that at least 1 873 * RX error (parity, framing, or break) has happened. 874 * Mark this in our struct, which will tell me that I have 875 *to do the special RX+LSR read for this FIFO load. 876 */ 877 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 878 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev, 879 "%s:%d Port: %d Got an RX error, need to parse LSR\n", 880 __FILE__, __LINE__, port); 881 882 /* 883 * The next 3 tests should *NOT* happen, as the above test 884 * should encapsulate all 3... At least, thats what Exar says. 885 */ 886 887 if (linestatus & UART_LSR_PE) { 888 ch->ch_err_parity++; 889 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev, 890 "%s:%d Port: %d. PAR ERR!\n", __FILE__, __LINE__, port); 891 } 892 893 if (linestatus & UART_LSR_FE) { 894 ch->ch_err_frame++; 895 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev, 896 "%s:%d Port: %d. FRM ERR!\n", __FILE__, __LINE__, port); 897 } 898 899 if (linestatus & UART_LSR_BI) { 900 ch->ch_err_break++; 901 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev, 902 "%s:%d Port: %d. BRK INTR!\n", __FILE__, __LINE__, port); 903 } 904 905 if (linestatus & UART_LSR_OE) { 906 /* 907 * Rx Oruns. Exar says that an orun will NOT corrupt 908 * the FIFO. It will just replace the holding register 909 * with this new data byte. So basically just ignore this. 910 * Probably we should eventually have an orun stat in our driver... 911 */ 912 ch->ch_err_overrun++; 913 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev, 914 "%s:%d Port: %d. Rx Overrun!\n", __FILE__, __LINE__, port); 915 } 916 917 if (linestatus & UART_LSR_THRE) { 918 spin_lock_irqsave(&ch->ch_lock, lock_flags); 919 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 920 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 921 922 /* Transfer data (if any) from Write Queue -> UART. */ 923 neo_copy_data_from_queue_to_uart(ch); 924 } 925 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) { 926 spin_lock_irqsave(&ch->ch_lock, lock_flags); 927 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 928 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 929 930 /* Transfer data (if any) from Write Queue -> UART. */ 931 neo_copy_data_from_queue_to_uart(ch); 932 } 933} 934 935/* 936 * neo_param() 937 * Send any/all changes to the line to the UART. 938 */ 939static void neo_param(struct jsm_channel *ch) 940{ 941 u8 lcr = 0; 942 u8 uart_lcr = 0; 943 u8 ier = 0; 944 u32 baud = 9600; 945 int quot = 0; 946 struct jsm_board *bd; 947 948 bd = ch->ch_bd; 949 if (!bd) 950 return; 951 952 /* 953 * If baud rate is zero, flush queues, and set mval to drop DTR. 954 */ 955 if ((ch->ch_c_cflag & (CBAUD)) == 0) { 956 ch->ch_r_head = ch->ch_r_tail = 0; 957 ch->ch_e_head = ch->ch_e_tail = 0; 958 ch->ch_w_head = ch->ch_w_tail = 0; 959 960 neo_flush_uart_write(ch); 961 neo_flush_uart_read(ch); 962 963 ch->ch_flags |= (CH_BAUD0); 964 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); 965 neo_assert_modem_signals(ch); 966 ch->ch_old_baud = 0; 967 return; 968 969 } else if (ch->ch_custom_speed) { 970 baud = ch->ch_custom_speed; 971 if (ch->ch_flags & CH_BAUD0) 972 ch->ch_flags &= ~(CH_BAUD0); 973 } else { 974 int i; 975 unsigned int cflag; 976 static struct { 977 unsigned int rate; 978 unsigned int cflag; 979 } baud_rates[] = { 980 { 921600, B921600 }, 981 { 460800, B460800 }, 982 { 230400, B230400 }, 983 { 115200, B115200 }, 984 { 57600, B57600 }, 985 { 38400, B38400 }, 986 { 19200, B19200 }, 987 { 9600, B9600 }, 988 { 4800, B4800 }, 989 { 2400, B2400 }, 990 { 1200, B1200 }, 991 { 600, B600 }, 992 { 300, B300 }, 993 { 200, B200 }, 994 { 150, B150 }, 995 { 134, B134 }, 996 { 110, B110 }, 997 { 75, B75 }, 998 { 50, B50 }, 999 }; 1000 1001 cflag = C_BAUD(ch->uart_port.info->tty); 1002 baud = 9600; 1003 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) { 1004 if (baud_rates[i].cflag == cflag) { 1005 baud = baud_rates[i].rate; 1006 break; 1007 } 1008 } 1009 1010 if (ch->ch_flags & CH_BAUD0) 1011 ch->ch_flags &= ~(CH_BAUD0); 1012 } 1013 1014 if (ch->ch_c_cflag & PARENB) 1015 lcr |= UART_LCR_PARITY; 1016 1017 if (!(ch->ch_c_cflag & PARODD)) 1018 lcr |= UART_LCR_EPAR; 1019 1020 /* 1021 * Not all platforms support mark/space parity, 1022 * so this will hide behind an ifdef. 1023 */ 1024#ifdef CMSPAR 1025 if (ch->ch_c_cflag & CMSPAR) 1026 lcr |= UART_LCR_SPAR; 1027#endif 1028 1029 if (ch->ch_c_cflag & CSTOPB) 1030 lcr |= UART_LCR_STOP; 1031 1032 switch (ch->ch_c_cflag & CSIZE) { 1033 case CS5: 1034 lcr |= UART_LCR_WLEN5; 1035 break; 1036 case CS6: 1037 lcr |= UART_LCR_WLEN6; 1038 break; 1039 case CS7: 1040 lcr |= UART_LCR_WLEN7; 1041 break; 1042 case CS8: 1043 default: 1044 lcr |= UART_LCR_WLEN8; 1045 break; 1046 } 1047 1048 ier = readb(&ch->ch_neo_uart->ier); 1049 uart_lcr = readb(&ch->ch_neo_uart->lcr); 1050 1051 if (baud == 0) 1052 baud = 9600; 1053 1054 quot = ch->ch_bd->bd_dividend / baud; 1055 1056 if (quot != 0) { 1057 ch->ch_old_baud = baud; 1058 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr); 1059 writeb((quot & 0xff), &ch->ch_neo_uart->txrx); 1060 writeb((quot >> 8), &ch->ch_neo_uart->ier); 1061 writeb(lcr, &ch->ch_neo_uart->lcr); 1062 } 1063 1064 if (uart_lcr != lcr) 1065 writeb(lcr, &ch->ch_neo_uart->lcr); 1066 1067 if (ch->ch_c_cflag & CREAD) 1068 ier |= (UART_IER_RDI | UART_IER_RLSI); 1069 1070 ier |= (UART_IER_THRI | UART_IER_MSI); 1071 1072 writeb(ier, &ch->ch_neo_uart->ier); 1073 1074 /* Set new start/stop chars */ 1075 neo_set_new_start_stop_chars(ch); 1076 1077 if (ch->ch_c_cflag & CRTSCTS) 1078 neo_set_cts_flow_control(ch); 1079 else if (ch->ch_c_iflag & IXON) { 1080 /* If start/stop is set to disable, then we should disable flow control */ 1081 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1082 neo_set_no_output_flow_control(ch); 1083 else 1084 neo_set_ixon_flow_control(ch); 1085 } 1086 else 1087 neo_set_no_output_flow_control(ch); 1088 1089 if (ch->ch_c_cflag & CRTSCTS) 1090 neo_set_rts_flow_control(ch); 1091 else if (ch->ch_c_iflag & IXOFF) { 1092 /* If start/stop is set to disable, then we should disable flow control */ 1093 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1094 neo_set_no_input_flow_control(ch); 1095 else 1096 neo_set_ixoff_flow_control(ch); 1097 } 1098 else 1099 neo_set_no_input_flow_control(ch); 1100 /* 1101 * Adjust the RX FIFO Trigger level if baud is less than 9600. 1102 * Not exactly elegant, but this is needed because of the Exar chip's 1103 * delay on firing off the RX FIFO interrupt on slower baud rates. 1104 */ 1105 if (baud < 9600) { 1106 writeb(1, &ch->ch_neo_uart->rfifo); 1107 ch->ch_r_tlevel = 1; 1108 } 1109 1110 neo_assert_modem_signals(ch); 1111 1112 /* Get current status of the modem signals now */ 1113 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 1114 return; 1115} 1116 1117/* 1118 * jsm_neo_intr() 1119 * 1120 * Neo specific interrupt handler. 1121 */ 1122static irqreturn_t neo_intr(int irq, void *voidbrd) 1123{ 1124 struct jsm_board *brd = voidbrd; 1125 struct jsm_channel *ch; 1126 int port = 0; 1127 int type = 0; 1128 int current_port; 1129 u32 tmp; 1130 u32 uart_poll; 1131 unsigned long lock_flags; 1132 unsigned long lock_flags2; 1133 int outofloop_count = 0; 1134 1135 brd->intr_count++; 1136 1137 /* Lock out the slow poller from running on this board. */ 1138 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); 1139 1140 /* 1141 * Read in "extended" IRQ information from the 32bit Neo register. 1142 * Bits 0-7: What port triggered the interrupt. 1143 * Bits 8-31: Each 3bits indicate what type of interrupt occurred. 1144 */ 1145 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET); 1146 1147 jsm_printk(INTR, INFO, &brd->pci_dev, 1148 "%s:%d uart_poll: %x\n", __FILE__, __LINE__, uart_poll); 1149 1150 if (!uart_poll) { 1151 jsm_printk(INTR, INFO, &brd->pci_dev, 1152 "Kernel interrupted to me, but no pending interrupts...\n"); 1153 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1154 return IRQ_NONE; 1155 } 1156 1157 /* At this point, we have at least SOMETHING to service, dig further... */ 1158 1159 current_port = 0; 1160 1161 /* Loop on each port */ 1162 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){ 1163 1164 tmp = uart_poll; 1165 outofloop_count++; 1166 1167 /* Check current port to see if it has interrupt pending */ 1168 if ((tmp & jsm_offset_table[current_port]) != 0) { 1169 port = current_port; 1170 type = tmp >> (8 + (port * 3)); 1171 type &= 0x7; 1172 } else { 1173 current_port++; 1174 continue; 1175 } 1176 1177 jsm_printk(INTR, INFO, &brd->pci_dev, 1178 "%s:%d port: %x type: %x\n", __FILE__, __LINE__, port, type); 1179 1180 /* Remove this port + type from uart_poll */ 1181 uart_poll &= ~(jsm_offset_table[port]); 1182 1183 if (!type) { 1184 /* If no type, just ignore it, and move onto next port */ 1185 jsm_printk(INTR, ERR, &brd->pci_dev, 1186 "Interrupt with no type! port: %d\n", port); 1187 continue; 1188 } 1189 1190 /* Switch on type of interrupt we have */ 1191 switch (type) { 1192 1193 case UART_17158_RXRDY_TIMEOUT: 1194 /* 1195 * RXRDY Time-out is cleared by reading data in the 1196 * RX FIFO until it falls below the trigger level. 1197 */ 1198 1199 /* Verify the port is in range. */ 1200 if (port > brd->nasync) 1201 continue; 1202 1203 ch = brd->channels[port]; 1204 neo_copy_data_from_uart_to_queue(ch); 1205 1206 /* Call our tty layer to enforce queue flow control if needed. */ 1207 spin_lock_irqsave(&ch->ch_lock, lock_flags2); 1208 jsm_check_queue_flow_control(ch); 1209 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2); 1210 1211 continue; 1212 1213 case UART_17158_RX_LINE_STATUS: 1214 /* 1215 * RXRDY and RX LINE Status (logic OR of LSR[4:1]) 1216 */ 1217 neo_parse_lsr(brd, port); 1218 continue; 1219 1220 case UART_17158_TXRDY: 1221 /* 1222 * TXRDY interrupt clears after reading ISR register for the UART channel. 1223 */ 1224 1225 /* 1226 * Yes, this is odd... 1227 * Why would I check EVERY possibility of type of 1228 * interrupt, when we know its TXRDY??? 1229 * Becuz for some reason, even tho we got triggered for TXRDY, 1230 * it seems to be occassionally wrong. Instead of TX, which 1231 * it should be, I was getting things like RXDY too. Weird. 1232 */ 1233 neo_parse_isr(brd, port); 1234 continue; 1235 1236 case UART_17158_MSR: 1237 /* 1238 * MSR or flow control was seen. 1239 */ 1240 neo_parse_isr(brd, port); 1241 continue; 1242 1243 default: 1244 /* 1245 * The UART triggered us with a bogus interrupt type. 1246 * It appears the Exar chip, when REALLY bogged down, will throw 1247 * these once and awhile. 1248 * Its harmless, just ignore it and move on. 1249 */ 1250 jsm_printk(INTR, ERR, &brd->pci_dev, 1251 "%s:%d Unknown Interrupt type: %x\n", __FILE__, __LINE__, type); 1252 continue; 1253 } 1254 } 1255 1256 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1257 1258 jsm_printk(INTR, INFO, &brd->pci_dev, "finish.\n"); 1259 return IRQ_HANDLED; 1260} 1261 1262/* 1263 * Neo specific way of turning off the receiver. 1264 * Used as a way to enforce queue flow control when in 1265 * hardware flow control mode. 1266 */ 1267static void neo_disable_receiver(struct jsm_channel *ch) 1268{ 1269 u8 tmp = readb(&ch->ch_neo_uart->ier); 1270 tmp &= ~(UART_IER_RDI); 1271 writeb(tmp, &ch->ch_neo_uart->ier); 1272 1273 /* flush write operation */ 1274 neo_pci_posting_flush(ch->ch_bd); 1275} 1276 1277 1278/* 1279 * Neo specific way of turning on the receiver. 1280 * Used as a way to un-enforce queue flow control when in 1281 * hardware flow control mode. 1282 */ 1283static void neo_enable_receiver(struct jsm_channel *ch) 1284{ 1285 u8 tmp = readb(&ch->ch_neo_uart->ier); 1286 tmp |= (UART_IER_RDI); 1287 writeb(tmp, &ch->ch_neo_uart->ier); 1288 1289 /* flush write operation */ 1290 neo_pci_posting_flush(ch->ch_bd); 1291} 1292 1293static void neo_send_start_character(struct jsm_channel *ch) 1294{ 1295 if (!ch) 1296 return; 1297 1298 if (ch->ch_startc != __DISABLED_CHAR) { 1299 ch->ch_xon_sends++; 1300 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx); 1301 1302 /* flush write operation */ 1303 neo_pci_posting_flush(ch->ch_bd); 1304 } 1305} 1306 1307static void neo_send_stop_character(struct jsm_channel *ch) 1308{ 1309 if (!ch) 1310 return; 1311 1312 if (ch->ch_stopc != __DISABLED_CHAR) { 1313 ch->ch_xoff_sends++; 1314 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx); 1315 1316 /* flush write operation */ 1317 neo_pci_posting_flush(ch->ch_bd); 1318 } 1319} 1320 1321/* 1322 * neo_uart_init 1323 */ 1324static void neo_uart_init(struct jsm_channel *ch) 1325{ 1326 writeb(0, &ch->ch_neo_uart->ier); 1327 writeb(0, &ch->ch_neo_uart->efr); 1328 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr); 1329 1330 /* Clear out UART and FIFO */ 1331 readb(&ch->ch_neo_uart->txrx); 1332 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 1333 readb(&ch->ch_neo_uart->lsr); 1334 readb(&ch->ch_neo_uart->msr); 1335 1336 ch->ch_flags |= CH_FIFO_ENABLED; 1337 1338 /* Assert any signals we want up */ 1339 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 1340} 1341 1342/* 1343 * Make the UART completely turn off. 1344 */ 1345static void neo_uart_off(struct jsm_channel *ch) 1346{ 1347 /* Turn off UART enhanced bits */ 1348 writeb(0, &ch->ch_neo_uart->efr); 1349 1350 /* Stop all interrupts from occurring. */ 1351 writeb(0, &ch->ch_neo_uart->ier); 1352} 1353 1354static u32 neo_get_uart_bytes_left(struct jsm_channel *ch) 1355{ 1356 u8 left = 0; 1357 u8 lsr = readb(&ch->ch_neo_uart->lsr); 1358 1359 /* We must cache the LSR as some of the bits get reset once read... */ 1360 ch->ch_cached_lsr |= lsr; 1361 1362 /* Determine whether the Transmitter is empty or not */ 1363 if (!(lsr & UART_LSR_TEMT)) 1364 left = 1; 1365 else { 1366 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1367 left = 0; 1368 } 1369 1370 return left; 1371} 1372 1373/* Channel lock MUST be held by the calling function! */ 1374static void neo_send_break(struct jsm_channel *ch) 1375{ 1376 /* 1377 * Set the time we should stop sending the break. 1378 * If we are already sending a break, toss away the existing 1379 * time to stop, and use this new value instead. 1380 */ 1381 1382 /* Tell the UART to start sending the break */ 1383 if (!(ch->ch_flags & CH_BREAK_SENDING)) { 1384 u8 temp = readb(&ch->ch_neo_uart->lcr); 1385 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr); 1386 ch->ch_flags |= (CH_BREAK_SENDING); 1387 1388 /* flush write operation */ 1389 neo_pci_posting_flush(ch->ch_bd); 1390 } 1391} 1392 1393/* 1394 * neo_send_immediate_char. 1395 * 1396 * Sends a specific character as soon as possible to the UART, 1397 * jumping over any bytes that might be in the write queue. 1398 * 1399 * The channel lock MUST be held by the calling function. 1400 */ 1401static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c) 1402{ 1403 if (!ch) 1404 return; 1405 1406 writeb(c, &ch->ch_neo_uart->txrx); 1407 1408 /* flush write operation */ 1409 neo_pci_posting_flush(ch->ch_bd); 1410} 1411 1412struct board_ops jsm_neo_ops = { 1413 .intr = neo_intr, 1414 .uart_init = neo_uart_init, 1415 .uart_off = neo_uart_off, 1416 .param = neo_param, 1417 .assert_modem_signals = neo_assert_modem_signals, 1418 .flush_uart_write = neo_flush_uart_write, 1419 .flush_uart_read = neo_flush_uart_read, 1420 .disable_receiver = neo_disable_receiver, 1421 .enable_receiver = neo_enable_receiver, 1422 .send_break = neo_send_break, 1423 .clear_break = neo_clear_break, 1424 .send_start_character = neo_send_start_character, 1425 .send_stop_character = neo_send_stop_character, 1426 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart, 1427 .get_uart_bytes_left = neo_get_uart_bytes_left, 1428 .send_immediate_char = neo_send_immediate_char 1429}; 1430