1/************************************************************************ 2 * Copyright 2003 Digi International (www.digi.com) 3 * 4 * Copyright (C) 2004 IBM Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 14 * PURPOSE. See the GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston, 19 * MA 02111-1307, USA. 20 * 21 * Contact Information: 22 * Scott H Kilau <Scott_Kilau@digi.com> 23 * Wendy Xiong <wendyx@us.ibm.com> 24 * 25 ***********************************************************************/ 26 27#ifndef __JSM_DRIVER_H 28#define __JSM_DRIVER_H 29 30#include <linux/kernel.h> 31#include <linux/types.h> /* To pick up the varions Linux types */ 32#include <linux/tty.h> 33#include <linux/serial_core.h> 34#include <linux/device.h> 35 36/* 37 * Debugging levels can be set using debug insmod variable 38 * They can also be compiled out completely. 39 */ 40enum { 41 DBG_INIT = 0x01, 42 DBG_BASIC = 0x02, 43 DBG_CORE = 0x04, 44 DBG_OPEN = 0x08, 45 DBG_CLOSE = 0x10, 46 DBG_READ = 0x20, 47 DBG_WRITE = 0x40, 48 DBG_IOCTL = 0x80, 49 DBG_PROC = 0x100, 50 DBG_PARAM = 0x200, 51 DBG_PSCAN = 0x400, 52 DBG_EVENT = 0x800, 53 DBG_DRAIN = 0x1000, 54 DBG_MSIGS = 0x2000, 55 DBG_MGMT = 0x4000, 56 DBG_INTR = 0x8000, 57 DBG_CARR = 0x10000, 58}; 59 60#define jsm_printk(nlevel, klevel, pdev, fmt, args...) \ 61 if ((DBG_##nlevel & jsm_debug)) \ 62 dev_printk(KERN_##klevel, pdev->dev, fmt, ## args) 63 64#define MAXPORTS 8 65#define MAX_STOPS_SENT 5 66 67/* Board type definitions */ 68 69#define T_NEO 0000 70#define T_CLASSIC 0001 71#define T_PCIBUS 0400 72 73/* Board State Definitions */ 74 75#define BD_RUNNING 0x0 76#define BD_REASON 0x7f 77#define BD_NOTFOUND 0x1 78#define BD_NOIOPORT 0x2 79#define BD_NOMEM 0x3 80#define BD_NOBIOS 0x4 81#define BD_NOFEP 0x5 82#define BD_FAILED 0x6 83#define BD_ALLOCATED 0x7 84#define BD_TRIBOOT 0x8 85#define BD_BADKME 0x80 86 87 88/* 4 extra for alignment play space */ 89#define WRITEBUFLEN ((4096) + 4) 90#define MYFLIPLEN N_TTY_BUF_SIZE 91 92#define JSM_VERSION "jsm: 1.2-1-INKERNEL" 93#define JSM_PARTNUM "40002438_A-INKERNEL" 94 95struct jsm_board; 96struct jsm_channel; 97 98/************************************************************************ 99 * Per board operations structure * 100 ************************************************************************/ 101struct board_ops { 102 irq_handler_t intr; 103 void (*uart_init) (struct jsm_channel *ch); 104 void (*uart_off) (struct jsm_channel *ch); 105 void (*param) (struct jsm_channel *ch); 106 void (*assert_modem_signals) (struct jsm_channel *ch); 107 void (*flush_uart_write) (struct jsm_channel *ch); 108 void (*flush_uart_read) (struct jsm_channel *ch); 109 void (*disable_receiver) (struct jsm_channel *ch); 110 void (*enable_receiver) (struct jsm_channel *ch); 111 void (*send_break) (struct jsm_channel *ch); 112 void (*clear_break) (struct jsm_channel *ch, int); 113 void (*send_start_character) (struct jsm_channel *ch); 114 void (*send_stop_character) (struct jsm_channel *ch); 115 void (*copy_data_from_queue_to_uart) (struct jsm_channel *ch); 116 u32 (*get_uart_bytes_left) (struct jsm_channel *ch); 117 void (*send_immediate_char) (struct jsm_channel *ch, unsigned char); 118}; 119 120 121/* 122 * Per-board information 123 */ 124struct jsm_board 125{ 126 int boardnum; /* Board number: 0-32 */ 127 128 int type; /* Type of board */ 129 u8 rev; /* PCI revision ID */ 130 struct pci_dev *pci_dev; 131 u32 maxports; /* MAX ports this board can handle */ 132 133 spinlock_t bd_lock; /* Used to protect board */ 134 135 spinlock_t bd_intr_lock; /* Used to protect the poller tasklet and 136 * the interrupt routine from each other. 137 */ 138 139 u32 nasync; /* Number of ports on card */ 140 141 u32 irq; /* Interrupt request number */ 142 u64 intr_count; /* Count of interrupts */ 143 144 u64 membase; /* Start of base memory of the card */ 145 u64 membase_end; /* End of base memory of the card */ 146 147 u8 __iomem *re_map_membase;/* Remapped memory of the card */ 148 149 u64 iobase; /* Start of io base of the card */ 150 u64 iobase_end; /* End of io base of the card */ 151 152 u32 bd_uart_offset; /* Space between each UART */ 153 154 struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */ 155 char *flipbuf; /* Our flip buffer, alloced if board is found */ 156 157 u32 bd_dividend; /* Board/UARTs specific dividend */ 158 159 struct board_ops *bd_ops; 160 161 struct list_head jsm_board_entry; 162}; 163 164/************************************************************************ 165 * Device flag definitions for ch_flags. 166 ************************************************************************/ 167#define CH_PRON 0x0001 /* Printer on string */ 168#define CH_STOP 0x0002 /* Output is stopped */ 169#define CH_STOPI 0x0004 /* Input is stopped */ 170#define CH_CD 0x0008 /* Carrier is present */ 171#define CH_FCAR 0x0010 /* Carrier forced on */ 172#define CH_HANGUP 0x0020 /* Hangup received */ 173 174#define CH_RECEIVER_OFF 0x0040 /* Receiver is off */ 175#define CH_OPENING 0x0080 /* Port in fragile open state */ 176#define CH_CLOSING 0x0100 /* Port in fragile close state */ 177#define CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */ 178#define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */ 179#define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */ 180#define CH_BREAK_SENDING 0x1000 /* Break is being sent */ 181#define CH_LOOPBACK 0x2000 /* Channel is in lookback mode */ 182#define CH_FLIPBUF_IN_USE 0x4000 /* Channel's flipbuf is in use */ 183#define CH_BAUD0 0x08000 /* Used for checking B0 transitions */ 184 185/* Our Read/Error/Write queue sizes */ 186#define RQUEUEMASK 0x1FFF /* 8 K - 1 */ 187#define EQUEUEMASK 0x1FFF /* 8 K - 1 */ 188#define WQUEUEMASK 0x0FFF /* 4 K - 1 */ 189#define RQUEUESIZE (RQUEUEMASK + 1) 190#define EQUEUESIZE RQUEUESIZE 191#define WQUEUESIZE (WQUEUEMASK + 1) 192 193 194/************************************************************************ 195 * Channel information structure. 196 ************************************************************************/ 197struct jsm_channel { 198 struct uart_port uart_port; 199 struct jsm_board *ch_bd; /* Board structure pointer */ 200 201 spinlock_t ch_lock; /* provide for serialization */ 202 wait_queue_head_t ch_flags_wait; 203 204 u32 ch_portnum; /* Port number, 0 offset. */ 205 u32 ch_open_count; /* open count */ 206 u32 ch_flags; /* Channel flags */ 207 208 u64 ch_close_delay; /* How long we should drop RTS/DTR for */ 209 210 u64 ch_cpstime; /* Time for CPS calculations */ 211 212 tcflag_t ch_c_iflag; /* channel iflags */ 213 tcflag_t ch_c_cflag; /* channel cflags */ 214 tcflag_t ch_c_oflag; /* channel oflags */ 215 tcflag_t ch_c_lflag; /* channel lflags */ 216 u8 ch_stopc; /* Stop character */ 217 u8 ch_startc; /* Start character */ 218 219 u32 ch_old_baud; /* Cache of the current baud */ 220 u32 ch_custom_speed;/* Custom baud, if set */ 221 222 u32 ch_wopen; /* Waiting for open process cnt */ 223 224 u8 ch_mostat; /* FEP output modem status */ 225 u8 ch_mistat; /* FEP input modem status */ 226 227 struct neo_uart_struct __iomem *ch_neo_uart; /* Pointer to the "mapped" UART struct */ 228 u8 ch_cached_lsr; /* Cached value of the LSR register */ 229 230 u8 *ch_rqueue; /* Our read queue buffer - malloc'ed */ 231 u16 ch_r_head; /* Head location of the read queue */ 232 u16 ch_r_tail; /* Tail location of the read queue */ 233 234 u8 *ch_equeue; /* Our error queue buffer - malloc'ed */ 235 u16 ch_e_head; /* Head location of the error queue */ 236 u16 ch_e_tail; /* Tail location of the error queue */ 237 238 u8 *ch_wqueue; /* Our write queue buffer - malloc'ed */ 239 u16 ch_w_head; /* Head location of the write queue */ 240 u16 ch_w_tail; /* Tail location of the write queue */ 241 242 u64 ch_rxcount; /* total of data received so far */ 243 u64 ch_txcount; /* total of data transmitted so far */ 244 245 u8 ch_r_tlevel; /* Receive Trigger level */ 246 u8 ch_t_tlevel; /* Transmit Trigger level */ 247 248 u8 ch_r_watermark; /* Receive Watermark */ 249 250 251 u32 ch_stops_sent; /* How many times I have sent a stop character 252 * to try to stop the other guy sending. 253 */ 254 u64 ch_err_parity; /* Count of parity errors on channel */ 255 u64 ch_err_frame; /* Count of framing errors on channel */ 256 u64 ch_err_break; /* Count of breaks on channel */ 257 u64 ch_err_overrun; /* Count of overruns on channel */ 258 259 u64 ch_xon_sends; /* Count of xons transmitted */ 260 u64 ch_xoff_sends; /* Count of xoffs transmitted */ 261}; 262 263 264/************************************************************************ 265 * Per channel/port NEO UART structure * 266 ************************************************************************ 267 * Base Structure Entries Usage Meanings to Host * 268 * * 269 * W = read write R = read only * 270 * U = Unused. * 271 ************************************************************************/ 272 273struct neo_uart_struct { 274 u8 txrx; /* WR RHR/THR - Holding Reg */ 275 u8 ier; /* WR IER - Interrupt Enable Reg */ 276 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */ 277 u8 lcr; /* WR LCR - Line Control Reg */ 278 u8 mcr; /* WR MCR - Modem Control Reg */ 279 u8 lsr; /* WR LSR - Line Status Reg */ 280 u8 msr; /* WR MSR - Modem Status Reg */ 281 u8 spr; /* WR SPR - Scratch Pad Reg */ 282 u8 fctr; /* WR FCTR - Feature Control Reg */ 283 u8 efr; /* WR EFR - Enhanced Function Reg */ 284 u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */ 285 u8 rfifo; /* WR RXCNT/RXTRG - Recieve FIFO Reg */ 286 u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */ 287 u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */ 288 u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */ 289 u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */ 290 291 u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */ 292 u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */ 293 u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */ 294 u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */ 295}; 296 297/* Where to read the extended interrupt register (32bits instead of 8bits) */ 298#define UART_17158_POLL_ADDR_OFFSET 0x80 299 300/* 301 * These are the redefinitions for the FCTR on the XR17C158, since 302 * Exar made them different than their earlier design. (XR16C854) 303 */ 304 305/* These are only applicable when table D is selected */ 306#define UART_17158_FCTR_RTS_NODELAY 0x00 307#define UART_17158_FCTR_RTS_4DELAY 0x01 308#define UART_17158_FCTR_RTS_6DELAY 0x02 309#define UART_17158_FCTR_RTS_8DELAY 0x03 310#define UART_17158_FCTR_RTS_12DELAY 0x12 311#define UART_17158_FCTR_RTS_16DELAY 0x05 312#define UART_17158_FCTR_RTS_20DELAY 0x13 313#define UART_17158_FCTR_RTS_24DELAY 0x06 314#define UART_17158_FCTR_RTS_28DELAY 0x14 315#define UART_17158_FCTR_RTS_32DELAY 0x07 316#define UART_17158_FCTR_RTS_36DELAY 0x16 317#define UART_17158_FCTR_RTS_40DELAY 0x08 318#define UART_17158_FCTR_RTS_44DELAY 0x09 319#define UART_17158_FCTR_RTS_48DELAY 0x10 320#define UART_17158_FCTR_RTS_52DELAY 0x11 321 322#define UART_17158_FCTR_RTS_IRDA 0x10 323#define UART_17158_FCTR_RS485 0x20 324#define UART_17158_FCTR_TRGA 0x00 325#define UART_17158_FCTR_TRGB 0x40 326#define UART_17158_FCTR_TRGC 0x80 327#define UART_17158_FCTR_TRGD 0xC0 328 329/* 17158 trigger table selects.. */ 330#define UART_17158_FCTR_BIT6 0x40 331#define UART_17158_FCTR_BIT7 0x80 332 333/* 17158 TX/RX memmapped buffer offsets */ 334#define UART_17158_RX_FIFOSIZE 64 335#define UART_17158_TX_FIFOSIZE 64 336 337/* 17158 Extended IIR's */ 338#define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */ 339#define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */ 340#define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */ 341#define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */ 342 343/* 344 * These are the extended interrupts that get sent 345 * back to us from the UART's 32bit interrupt register 346 */ 347#define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */ 348#define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */ 349#define UART_17158_TXRDY 0x3 /* TX Ready */ 350#define UART_17158_MSR 0x4 /* Modem State Change */ 351#define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */ 352#define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */ 353 354/* 355 * These are the EXTENDED definitions for the 17C158's Interrupt 356 * Enable Register. 357 */ 358#define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */ 359#define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */ 360#define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */ 361#define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ 362#define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */ 363 364#define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */ 365#define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */ 366 367#define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */ 368#define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */ 369#define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */ 370#define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */ 371 372#define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI" 373#define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator" 374#define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI" 375#define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator" 376 377/* 378 * Our Global Variables. 379 */ 380extern struct uart_driver jsm_uart_driver; 381extern struct board_ops jsm_neo_ops; 382extern int jsm_debug; 383 384/************************************************************************* 385 * 386 * Prototypes for non-static functions used in more than one module 387 * 388 *************************************************************************/ 389int jsm_tty_write(struct uart_port *port); 390int jsm_tty_init(struct jsm_board *); 391int jsm_uart_port_init(struct jsm_board *); 392int jsm_remove_uart_port(struct jsm_board *); 393void jsm_input(struct jsm_channel *ch); 394void jsm_check_queue_flow_control(struct jsm_channel *ch); 395 396#endif 397