1/* 2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family 3 * of PCI-SCSI IO processors. 4 * 5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 6 * 7 * This driver is derived from the Linux sym53c8xx driver. 8 * Copyright (C) 1998-2000 Gerard Roudier 9 * 10 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 11 * a port of the FreeBSD ncr driver to Linux-1.2.13. 12 * 13 * The original ncr driver has been written for 386bsd and FreeBSD by 14 * Wolfgang Stanglmeier <wolf@cologne.de> 15 * Stefan Esser <se@mi.Uni-Koeln.de> 16 * Copyright (C) 1994 Wolfgang Stanglmeier 17 * 18 * Other major contributions: 19 * 20 * NVRAM detection and reading. 21 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 22 * 23 *----------------------------------------------------------------------------- 24 * 25 * This program is free software; you can redistribute it and/or modify 26 * it under the terms of the GNU General Public License as published by 27 * the Free Software Foundation; either version 2 of the License, or 28 * (at your option) any later version. 29 * 30 * This program is distributed in the hope that it will be useful, 31 * but WITHOUT ANY WARRANTY; without even the implied warranty of 32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 33 * GNU General Public License for more details. 34 * 35 * You should have received a copy of the GNU General Public License 36 * along with this program; if not, write to the Free Software 37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 38 */ 39 40/* 41 * Scripts for SYMBIOS-Processor 42 * 43 * We have to know the offsets of all labels before we reach 44 * them (for forward jumps). Therefore we declare a struct 45 * here. If you make changes inside the script, 46 * 47 * DONT FORGET TO CHANGE THE LENGTHS HERE! 48 */ 49 50/* 51 * Script fragments which are loaded into the on-chip RAM 52 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips. 53 * Must not exceed 4K bytes. 54 */ 55struct SYM_FWA_SCR { 56 u32 start [ 11]; 57 u32 getjob_begin [ 4]; 58 u32 _sms_a10 [ 5]; 59 u32 getjob_end [ 4]; 60 u32 _sms_a20 [ 4]; 61#ifdef SYM_CONF_TARGET_ROLE_SUPPORT 62 u32 select [ 8]; 63#else 64 u32 select [ 6]; 65#endif 66 u32 _sms_a30 [ 5]; 67 u32 wf_sel_done [ 2]; 68 u32 send_ident [ 2]; 69#ifdef SYM_CONF_IARB_SUPPORT 70 u32 select2 [ 8]; 71#else 72 u32 select2 [ 2]; 73#endif 74 u32 command [ 2]; 75 u32 dispatch [ 28]; 76 u32 sel_no_cmd [ 10]; 77 u32 init [ 6]; 78 u32 clrack [ 4]; 79 u32 datai_done [ 11]; 80 u32 datai_done_wsr [ 20]; 81 u32 datao_done [ 11]; 82 u32 datao_done_wss [ 6]; 83 u32 datai_phase [ 5]; 84 u32 datao_phase [ 5]; 85 u32 msg_in [ 2]; 86 u32 msg_in2 [ 10]; 87#ifdef SYM_CONF_IARB_SUPPORT 88 u32 status [ 14]; 89#else 90 u32 status [ 10]; 91#endif 92 u32 complete [ 6]; 93 u32 complete2 [ 8]; 94 u32 _sms_a40 [ 12]; 95 u32 done [ 5]; 96 u32 _sms_a50 [ 5]; 97 u32 _sms_a60 [ 2]; 98 u32 done_end [ 4]; 99 u32 complete_error [ 5]; 100 u32 save_dp [ 11]; 101 u32 restore_dp [ 7]; 102 u32 disconnect [ 11]; 103 u32 disconnect2 [ 5]; 104 u32 _sms_a65 [ 3]; 105#ifdef SYM_CONF_IARB_SUPPORT 106 u32 idle [ 4]; 107#else 108 u32 idle [ 2]; 109#endif 110#ifdef SYM_CONF_IARB_SUPPORT 111 u32 ungetjob [ 7]; 112#else 113 u32 ungetjob [ 5]; 114#endif 115#ifdef SYM_CONF_TARGET_ROLE_SUPPORT 116 u32 reselect [ 4]; 117#else 118 u32 reselect [ 2]; 119#endif 120 u32 reselected [ 19]; 121 u32 _sms_a70 [ 6]; 122 u32 _sms_a80 [ 4]; 123 u32 reselected1 [ 25]; 124 u32 _sms_a90 [ 4]; 125 u32 resel_lun0 [ 7]; 126 u32 _sms_a100 [ 4]; 127 u32 resel_tag [ 8]; 128#if SYM_CONF_MAX_TASK*4 > 512 129 u32 _sms_a110 [ 23]; 130#elif SYM_CONF_MAX_TASK*4 > 256 131 u32 _sms_a110 [ 17]; 132#else 133 u32 _sms_a110 [ 13]; 134#endif 135 u32 _sms_a120 [ 2]; 136 u32 resel_go [ 4]; 137 u32 _sms_a130 [ 7]; 138 u32 resel_dsa [ 2]; 139 u32 resel_dsa1 [ 4]; 140 u32 _sms_a140 [ 7]; 141 u32 resel_no_tag [ 4]; 142 u32 _sms_a145 [ 7]; 143 u32 data_in [SYM_CONF_MAX_SG * 2]; 144 u32 data_in2 [ 4]; 145 u32 data_out [SYM_CONF_MAX_SG * 2]; 146 u32 data_out2 [ 4]; 147 u32 pm0_data [ 12]; 148 u32 pm0_data_out [ 6]; 149 u32 pm0_data_end [ 7]; 150 u32 pm_data_end [ 4]; 151 u32 _sms_a150 [ 4]; 152 u32 pm1_data [ 12]; 153 u32 pm1_data_out [ 6]; 154 u32 pm1_data_end [ 9]; 155}; 156 157/* 158 * Script fragments which stay in main memory for all chips 159 * except for chips that support 8K on-chip RAM. 160 */ 161struct SYM_FWB_SCR { 162 u32 no_data [ 2]; 163#ifdef SYM_CONF_TARGET_ROLE_SUPPORT 164 u32 sel_for_abort [ 18]; 165#else 166 u32 sel_for_abort [ 16]; 167#endif 168 u32 sel_for_abort_1 [ 2]; 169 u32 msg_in_etc [ 12]; 170 u32 msg_received [ 5]; 171 u32 msg_weird_seen [ 5]; 172 u32 msg_extended [ 17]; 173 u32 _sms_b10 [ 4]; 174 u32 msg_bad [ 6]; 175 u32 msg_weird [ 4]; 176 u32 msg_weird1 [ 8]; 177 u32 wdtr_resp [ 6]; 178 u32 send_wdtr [ 4]; 179 u32 sdtr_resp [ 6]; 180 u32 send_sdtr [ 4]; 181 u32 ppr_resp [ 6]; 182 u32 send_ppr [ 4]; 183 u32 nego_bad_phase [ 4]; 184 u32 msg_out [ 4]; 185 u32 msg_out_done [ 4]; 186 u32 data_ovrun [ 3]; 187 u32 data_ovrun1 [ 22]; 188 u32 data_ovrun2 [ 8]; 189 u32 abort_resel [ 16]; 190 u32 resend_ident [ 4]; 191 u32 ident_break [ 4]; 192 u32 ident_break_atn [ 4]; 193 u32 sdata_in [ 6]; 194 u32 resel_bad_lun [ 4]; 195 u32 bad_i_t_l [ 4]; 196 u32 bad_i_t_l_q [ 4]; 197 u32 bad_status [ 7]; 198 u32 wsr_ma_helper [ 4]; 199 200 /* Data area */ 201 u32 zero [ 1]; 202 u32 scratch [ 1]; 203 u32 scratch1 [ 1]; 204 u32 prev_done [ 1]; 205 u32 done_pos [ 1]; 206 u32 nextjob [ 1]; 207 u32 startpos [ 1]; 208 u32 targtbl [ 1]; 209}; 210 211/* 212 * Script fragments used at initialisations. 213 * Only runs out of main memory. 214 */ 215struct SYM_FWZ_SCR { 216 u32 snooptest [ 9]; 217 u32 snoopend [ 2]; 218}; 219 220static struct SYM_FWA_SCR SYM_FWA_SCR = { 221/*--------------------------< START >----------------------------*/ { 222 /* 223 * Switch the LED on. 224 * Will be patched with a NO_OP if LED 225 * not needed or not desired. 226 */ 227 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 228 0, 229 /* 230 * Clear SIGP. 231 */ 232 SCR_FROM_REG (ctest2), 233 0, 234 /* 235 * Stop here if the C code wants to perform 236 * some error recovery procedure manually. 237 * (Indicate this by setting SEM in ISTAT) 238 */ 239 SCR_FROM_REG (istat), 240 0, 241 /* 242 * Report to the C code the next position in 243 * the start queue the SCRIPTS will schedule. 244 * The C code must not change SCRATCHA. 245 */ 246 SCR_COPY (4), 247 PADDR_B (startpos), 248 RADDR_1 (scratcha), 249 SCR_INT ^ IFTRUE (MASK (SEM, SEM)), 250 SIR_SCRIPT_STOPPED, 251 /* 252 * Start the next job. 253 * 254 * @DSA = start point for this job. 255 * SCRATCHA = address of this job in the start queue. 256 * 257 * We will restore startpos with SCRATCHA if we fails the 258 * arbitration or if it is the idle job. 259 * 260 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS 261 * is a critical path. If it is partially executed, it then 262 * may happen that the job address is not yet in the DSA 263 * and the next queue position points to the next JOB. 264 */ 265}/*-------------------------< GETJOB_BEGIN >---------------------*/,{ 266 /* 267 * Copy to a fixed location both the next STARTPOS 268 * and the current JOB address, using self modifying 269 * SCRIPTS. 270 */ 271 SCR_COPY (4), 272 RADDR_1 (scratcha), 273 PADDR_A (_sms_a10), 274 SCR_COPY (8), 275}/*-------------------------< _SMS_A10 >-------------------------*/,{ 276 0, 277 PADDR_B (nextjob), 278 /* 279 * Move the start address to TEMP using self- 280 * modifying SCRIPTS and jump indirectly to 281 * that address. 282 */ 283 SCR_COPY (4), 284 PADDR_B (nextjob), 285 RADDR_1 (dsa), 286}/*-------------------------< GETJOB_END >-----------------------*/,{ 287 SCR_COPY (4), 288 RADDR_1 (dsa), 289 PADDR_A (_sms_a20), 290 SCR_COPY (4), 291}/*-------------------------< _SMS_A20 >-------------------------*/,{ 292 0, 293 RADDR_1 (temp), 294 SCR_RETURN, 295 0, 296}/*-------------------------< SELECT >---------------------------*/,{ 297 /* 298 * DSA contains the address of a scheduled 299 * data structure. 300 * 301 * SCRATCHA contains the address of the start queue 302 * entry which points to the next job. 303 * 304 * Set Initiator mode. 305 * 306 * (Target mode is left as an exercise for the reader) 307 */ 308#ifdef SYM_CONF_TARGET_ROLE_SUPPORT 309 SCR_CLR (SCR_TRG), 310 0, 311#endif 312 /* 313 * And try to select this target. 314 */ 315 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select), 316 PADDR_A (ungetjob), 317 /* 318 * Now there are 4 possibilities: 319 * 320 * (1) The chip loses arbitration. 321 * This is ok, because it will try again, 322 * when the bus becomes idle. 323 * (But beware of the timeout function!) 324 * 325 * (2) The chip is reselected. 326 * Then the script processor takes the jump 327 * to the RESELECT label. 328 * 329 * (3) The chip wins arbitration. 330 * Then it will execute SCRIPTS instruction until 331 * the next instruction that checks SCSI phase. 332 * Then will stop and wait for selection to be 333 * complete or selection time-out to occur. 334 * 335 * After having won arbitration, the SCRIPTS 336 * processor is able to execute instructions while 337 * the SCSI core is performing SCSI selection. 338 */ 339 340 /* 341 * Copy the CCB header to a fixed location 342 * in the HCB using self-modifying SCRIPTS. 343 */ 344 SCR_COPY (4), 345 RADDR_1 (dsa), 346 PADDR_A (_sms_a30), 347 SCR_COPY (sizeof(struct sym_ccbh)), 348}/*-------------------------< _SMS_A30 >-------------------------*/,{ 349 0, 350 HADDR_1 (ccb_head), 351 /* 352 * Initialize the status register 353 */ 354 SCR_COPY (4), 355 HADDR_1 (ccb_head.status), 356 RADDR_1 (scr0), 357}/*-------------------------< WF_SEL_DONE >----------------------*/,{ 358 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), 359 SIR_SEL_ATN_NO_MSG_OUT, 360}/*-------------------------< SEND_IDENT >-----------------------*/,{ 361 /* 362 * Selection complete. 363 * Send the IDENTIFY and possibly the TAG message 364 * and negotiation message if present. 365 */ 366 SCR_MOVE_TBL ^ SCR_MSG_OUT, 367 offsetof (struct sym_dsb, smsg), 368}/*-------------------------< SELECT2 >--------------------------*/,{ 369#ifdef SYM_CONF_IARB_SUPPORT 370 /* 371 * Set IMMEDIATE ARBITRATION if we have been given 372 * a hint to do so. (Some job to do after this one). 373 */ 374 SCR_FROM_REG (HF_REG), 375 0, 376 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), 377 8, 378 SCR_REG_REG (scntl1, SCR_OR, IARB), 379 0, 380#endif 381 /* 382 * Anticipate the COMMAND phase. 383 * This is the PHASE we expect at this point. 384 */ 385 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)), 386 PADDR_A (sel_no_cmd), 387}/*-------------------------< COMMAND >--------------------------*/,{ 388 /* 389 * ... and send the command 390 */ 391 SCR_MOVE_TBL ^ SCR_COMMAND, 392 offsetof (struct sym_dsb, cmd), 393}/*-------------------------< DISPATCH >-------------------------*/,{ 394 /* 395 * MSG_IN is the only phase that shall be 396 * entered at least once for each (re)selection. 397 * So we test it first. 398 */ 399 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 400 PADDR_A (msg_in), 401 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)), 402 PADDR_A (datao_phase), 403 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)), 404 PADDR_A (datai_phase), 405 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)), 406 PADDR_A (status), 407 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)), 408 PADDR_A (command), 409 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)), 410 PADDR_B (msg_out), 411 /* 412 * Discard as many illegal phases as 413 * required and tell the C code about. 414 */ 415 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)), 416 16, 417 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT, 418 HADDR_1 (scratch), 419 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)), 420 -16, 421 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)), 422 16, 423 SCR_MOVE_ABS (1) ^ SCR_ILG_IN, 424 HADDR_1 (scratch), 425 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)), 426 -16, 427 SCR_INT, 428 SIR_BAD_PHASE, 429 SCR_JUMP, 430 PADDR_A (dispatch), 431}/*-------------------------< SEL_NO_CMD >-----------------------*/,{ 432 /* 433 * The target does not switch to command 434 * phase after IDENTIFY has been sent. 435 * 436 * If it stays in MSG OUT phase send it 437 * the IDENTIFY again. 438 */ 439 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 440 PADDR_B (resend_ident), 441 /* 442 * If target does not switch to MSG IN phase 443 * and we sent a negotiation, assert the 444 * failure immediately. 445 */ 446 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 447 PADDR_A (dispatch), 448 SCR_FROM_REG (HS_REG), 449 0, 450 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), 451 SIR_NEGO_FAILED, 452 /* 453 * Jump to dispatcher. 454 */ 455 SCR_JUMP, 456 PADDR_A (dispatch), 457}/*-------------------------< INIT >-----------------------------*/,{ 458 /* 459 * Wait for the SCSI RESET signal to be 460 * inactive before restarting operations, 461 * since the chip may hang on SEL_ATN 462 * if SCSI RESET is active. 463 */ 464 SCR_FROM_REG (sstat0), 465 0, 466 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), 467 -16, 468 SCR_JUMP, 469 PADDR_A (start), 470}/*-------------------------< CLRACK >---------------------------*/,{ 471 /* 472 * Terminate possible pending message phase. 473 */ 474 SCR_CLR (SCR_ACK), 475 0, 476 SCR_JUMP, 477 PADDR_A (dispatch), 478}/*-------------------------< DATAI_DONE >-----------------------*/,{ 479 /* 480 * Save current pointer to LASTP. 481 */ 482 SCR_COPY (4), 483 RADDR_1 (temp), 484 HADDR_1 (ccb_head.lastp), 485 /* 486 * If the SWIDE is not full, jump to dispatcher. 487 * We anticipate a STATUS phase. 488 */ 489 SCR_FROM_REG (scntl2), 490 0, 491 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)), 492 PADDR_A (datai_done_wsr), 493 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), 494 PADDR_A (status), 495 SCR_JUMP, 496 PADDR_A (dispatch), 497}/*-------------------------< DATAI_DONE_WSR >-------------------*/,{ 498 /* 499 * The SWIDE is full. 500 * Clear this condition. 501 */ 502 SCR_REG_REG (scntl2, SCR_OR, WSR), 503 0, 504 /* 505 * We are expecting an IGNORE RESIDUE message 506 * from the device, otherwise we are in data 507 * overrun condition. Check against MSG_IN phase. 508 */ 509 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 510 SIR_SWIDE_OVERRUN, 511 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 512 PADDR_A (dispatch), 513 /* 514 * We are in MSG_IN phase, 515 * Read the first byte of the message. 516 * If it is not an IGNORE RESIDUE message, 517 * signal overrun and jump to message 518 * processing. 519 */ 520 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 521 HADDR_1 (msgin[0]), 522 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)), 523 SIR_SWIDE_OVERRUN, 524 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)), 525 PADDR_A (msg_in2), 526 /* 527 * We got the message we expected. 528 * Read the 2nd byte, and jump to dispatcher. 529 */ 530 SCR_CLR (SCR_ACK), 531 0, 532 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 533 HADDR_1 (msgin[1]), 534 SCR_CLR (SCR_ACK), 535 0, 536 SCR_JUMP, 537 PADDR_A (dispatch), 538}/*-------------------------< DATAO_DONE >-----------------------*/,{ 539 /* 540 * Save current pointer to LASTP. 541 */ 542 SCR_COPY (4), 543 RADDR_1 (temp), 544 HADDR_1 (ccb_head.lastp), 545 /* 546 * If the SODL is not full jump to dispatcher. 547 * We anticipate a STATUS phase. 548 */ 549 SCR_FROM_REG (scntl2), 550 0, 551 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)), 552 PADDR_A (datao_done_wss), 553 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), 554 PADDR_A (status), 555 SCR_JUMP, 556 PADDR_A (dispatch), 557}/*-------------------------< DATAO_DONE_WSS >-------------------*/,{ 558 /* 559 * The SODL is full, clear this condition. 560 */ 561 SCR_REG_REG (scntl2, SCR_OR, WSS), 562 0, 563 /* 564 * And signal a DATA UNDERRUN condition 565 * to the C code. 566 */ 567 SCR_INT, 568 SIR_SODL_UNDERRUN, 569 SCR_JUMP, 570 PADDR_A (dispatch), 571}/*-------------------------< DATAI_PHASE >----------------------*/,{ 572 /* 573 * Jump to current pointer. 574 */ 575 SCR_COPY (4), 576 HADDR_1 (ccb_head.lastp), 577 RADDR_1 (temp), 578 SCR_RETURN, 579 0, 580}/*-------------------------< DATAO_PHASE >----------------------*/,{ 581 /* 582 * Jump to current pointer. 583 */ 584 SCR_COPY (4), 585 HADDR_1 (ccb_head.lastp), 586 RADDR_1 (temp), 587 SCR_RETURN, 588 0, 589}/*-------------------------< MSG_IN >---------------------------*/,{ 590 /* 591 * Get the first byte of the message. 592 * 593 * The script processor doesn't negate the 594 * ACK signal after this transfer. 595 */ 596 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 597 HADDR_1 (msgin[0]), 598}/*-------------------------< MSG_IN2 >--------------------------*/,{ 599 /* 600 * Check first against 1 byte messages 601 * that we handle from SCRIPTS. 602 */ 603 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)), 604 PADDR_A (complete), 605 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)), 606 PADDR_A (disconnect), 607 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)), 608 PADDR_A (save_dp), 609 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)), 610 PADDR_A (restore_dp), 611 /* 612 * We handle all other messages from the 613 * C code, so no need to waste on-chip RAM 614 * for those ones. 615 */ 616 SCR_JUMP, 617 PADDR_B (msg_in_etc), 618}/*-------------------------< STATUS >---------------------------*/,{ 619 /* 620 * get the status 621 */ 622 SCR_MOVE_ABS (1) ^ SCR_STATUS, 623 HADDR_1 (scratch), 624#ifdef SYM_CONF_IARB_SUPPORT 625 /* 626 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION, 627 * since we may have to tamper the start queue from 628 * the C code. 629 */ 630 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)), 631 8, 632 SCR_REG_REG (scntl1, SCR_AND, ~IARB), 633 0, 634#endif 635 /* 636 * save status to scsi_status. 637 * mark as complete. 638 */ 639 SCR_TO_REG (SS_REG), 640 0, 641 SCR_LOAD_REG (HS_REG, HS_COMPLETE), 642 0, 643 /* 644 * Anticipate the MESSAGE PHASE for 645 * the TASK COMPLETE message. 646 */ 647 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 648 PADDR_A (msg_in), 649 SCR_JUMP, 650 PADDR_A (dispatch), 651}/*-------------------------< COMPLETE >-------------------------*/,{ 652 /* 653 * Complete message. 654 * 655 * When we terminate the cycle by clearing ACK, 656 * the target may disconnect immediately. 657 * 658 * We don't want to be told of an "unexpected disconnect", 659 * so we disable this feature. 660 */ 661 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 662 0, 663 /* 664 * Terminate cycle ... 665 */ 666 SCR_CLR (SCR_ACK|SCR_ATN), 667 0, 668 /* 669 * ... and wait for the disconnect. 670 */ 671 SCR_WAIT_DISC, 672 0, 673}/*-------------------------< COMPLETE2 >------------------------*/,{ 674 /* 675 * Save host status. 676 */ 677 SCR_COPY (4), 678 RADDR_1 (scr0), 679 HADDR_1 (ccb_head.status), 680 /* 681 * Move back the CCB header using self-modifying 682 * SCRIPTS. 683 */ 684 SCR_COPY (4), 685 RADDR_1 (dsa), 686 PADDR_A (_sms_a40), 687 SCR_COPY (sizeof(struct sym_ccbh)), 688 HADDR_1 (ccb_head), 689}/*-------------------------< _SMS_A40 >-------------------------*/,{ 690 0, 691 /* 692 * Some bridges may reorder DMA writes to memory. 693 * We donnot want the CPU to deal with completions 694 * without all the posted write having been flushed 695 * to memory. This DUMMY READ should flush posted 696 * buffers prior to the CPU having to deal with 697 * completions. 698 */ 699 SCR_COPY (4), /* DUMMY READ */ 700 HADDR_1 (ccb_head.status), 701 RADDR_1 (scr0), 702 /* 703 * If command resulted in not GOOD status, 704 * call the C code if needed. 705 */ 706 SCR_FROM_REG (SS_REG), 707 0, 708 SCR_CALL ^ IFFALSE (DATA (S_GOOD)), 709 PADDR_B (bad_status), 710 /* 711 * If we performed an auto-sense, call 712 * the C code to synchronyze task aborts 713 * with UNIT ATTENTION conditions. 714 */ 715 SCR_FROM_REG (HF_REG), 716 0, 717 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), 718 PADDR_A (complete_error), 719}/*-------------------------< DONE >-----------------------------*/,{ 720 /* 721 * Copy the DSA to the DONE QUEUE and 722 * signal completion to the host. 723 * If we are interrupted between DONE 724 * and DONE_END, we must reset, otherwise 725 * the completed CCB may be lost. 726 */ 727 SCR_COPY (4), 728 PADDR_B (done_pos), 729 PADDR_A (_sms_a50), 730 SCR_COPY (4), 731 RADDR_1 (dsa), 732}/*-------------------------< _SMS_A50 >-------------------------*/,{ 733 0, 734 SCR_COPY (4), 735 PADDR_B (done_pos), 736 PADDR_A (_sms_a60), 737 /* 738 * The instruction below reads the DONE QUEUE next 739 * free position from memory. 740 * In addition it ensures that all PCI posted writes 741 * are flushed and so the DSA value of the done 742 * CCB is visible by the CPU before INTFLY is raised. 743 */ 744 SCR_COPY (8), 745}/*-------------------------< _SMS_A60 >-------------------------*/,{ 746 0, 747 PADDR_B (prev_done), 748}/*-------------------------< DONE_END >-------------------------*/,{ 749 SCR_INT_FLY, 750 0, 751 SCR_JUMP, 752 PADDR_A (start), 753}/*-------------------------< COMPLETE_ERROR >-------------------*/,{ 754 SCR_COPY (4), 755 PADDR_B (startpos), 756 RADDR_1 (scratcha), 757 SCR_INT, 758 SIR_COMPLETE_ERROR, 759}/*-------------------------< SAVE_DP >--------------------------*/,{ 760 /* 761 * Clear ACK immediately. 762 * No need to delay it. 763 */ 764 SCR_CLR (SCR_ACK), 765 0, 766 /* 767 * Keep track we received a SAVE DP, so 768 * we will switch to the other PM context 769 * on the next PM since the DP may point 770 * to the current PM context. 771 */ 772 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 773 0, 774 /* 775 * SAVE_DP message: 776 * Copy LASTP to SAVEP. 777 */ 778 SCR_COPY (4), 779 HADDR_1 (ccb_head.lastp), 780 HADDR_1 (ccb_head.savep), 781 /* 782 * Anticipate the MESSAGE PHASE for 783 * the DISCONNECT message. 784 */ 785 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 786 PADDR_A (msg_in), 787 SCR_JUMP, 788 PADDR_A (dispatch), 789}/*-------------------------< RESTORE_DP >-----------------------*/,{ 790 /* 791 * Clear ACK immediately. 792 * No need to delay it. 793 */ 794 SCR_CLR (SCR_ACK), 795 0, 796 /* 797 * Copy SAVEP to LASTP. 798 */ 799 SCR_COPY (4), 800 HADDR_1 (ccb_head.savep), 801 HADDR_1 (ccb_head.lastp), 802 SCR_JUMP, 803 PADDR_A (dispatch), 804}/*-------------------------< DISCONNECT >-----------------------*/,{ 805 /* 806 * DISCONNECTing ... 807 * 808 * disable the "unexpected disconnect" feature, 809 * and remove the ACK signal. 810 */ 811 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 812 0, 813 SCR_CLR (SCR_ACK|SCR_ATN), 814 0, 815 /* 816 * Wait for the disconnect. 817 */ 818 SCR_WAIT_DISC, 819 0, 820 /* 821 * Status is: DISCONNECTED. 822 */ 823 SCR_LOAD_REG (HS_REG, HS_DISCONNECT), 824 0, 825 /* 826 * Save host status. 827 */ 828 SCR_COPY (4), 829 RADDR_1 (scr0), 830 HADDR_1 (ccb_head.status), 831}/*-------------------------< DISCONNECT2 >----------------------*/,{ 832 /* 833 * Move back the CCB header using self-modifying 834 * SCRIPTS. 835 */ 836 SCR_COPY (4), 837 RADDR_1 (dsa), 838 PADDR_A (_sms_a65), 839 SCR_COPY (sizeof(struct sym_ccbh)), 840 HADDR_1 (ccb_head), 841}/*-------------------------< _SMS_A65 >-------------------------*/,{ 842 0, 843 SCR_JUMP, 844 PADDR_A (start), 845}/*-------------------------< IDLE >-----------------------------*/,{ 846 /* 847 * Nothing to do? 848 * Switch the LED off and wait for reselect. 849 * Will be patched with a NO_OP if LED 850 * not needed or not desired. 851 */ 852 SCR_REG_REG (gpreg, SCR_OR, 0x01), 853 0, 854#ifdef SYM_CONF_IARB_SUPPORT 855 SCR_JUMPR, 856 8, 857#endif 858}/*-------------------------< UNGETJOB >-------------------------*/,{ 859#ifdef SYM_CONF_IARB_SUPPORT 860 /* 861 * Set IMMEDIATE ARBITRATION, for the next time. 862 * This will give us better chance to win arbitration 863 * for the job we just wanted to do. 864 */ 865 SCR_REG_REG (scntl1, SCR_OR, IARB), 866 0, 867#endif 868 /* 869 * We are not able to restart the SCRIPTS if we are 870 * interrupted and these instruction haven't been 871 * all executed. BTW, this is very unlikely to 872 * happen, but we check that from the C code. 873 */ 874 SCR_LOAD_REG (dsa, 0xff), 875 0, 876 SCR_COPY (4), 877 RADDR_1 (scratcha), 878 PADDR_B (startpos), 879}/*-------------------------< RESELECT >-------------------------*/,{ 880#ifdef SYM_CONF_TARGET_ROLE_SUPPORT 881 /* 882 * Make sure we are in initiator mode. 883 */ 884 SCR_CLR (SCR_TRG), 885 0, 886#endif 887 /* 888 * Sleep waiting for a reselection. 889 */ 890 SCR_WAIT_RESEL, 891 PADDR_A(start), 892}/*-------------------------< RESELECTED >-----------------------*/,{ 893 /* 894 * Switch the LED on. 895 * Will be patched with a NO_OP if LED 896 * not needed or not desired. 897 */ 898 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 899 0, 900 /* 901 * load the target id into the sdid 902 */ 903 SCR_REG_SFBR (ssid, SCR_AND, 0x8F), 904 0, 905 SCR_TO_REG (sdid), 906 0, 907 /* 908 * Load the target control block address 909 */ 910 SCR_COPY (4), 911 PADDR_B (targtbl), 912 RADDR_1 (dsa), 913 SCR_SFBR_REG (dsa, SCR_SHL, 0), 914 0, 915 SCR_REG_REG (dsa, SCR_SHL, 0), 916 0, 917 SCR_REG_REG (dsa, SCR_AND, 0x3c), 918 0, 919 SCR_COPY (4), 920 RADDR_1 (dsa), 921 PADDR_A (_sms_a70), 922 SCR_COPY (4), 923}/*-------------------------< _SMS_A70 >-------------------------*/,{ 924 0, 925 RADDR_1 (dsa), 926 /* 927 * Copy the TCB header to a fixed place in 928 * the HCB. 929 */ 930 SCR_COPY (4), 931 RADDR_1 (dsa), 932 PADDR_A (_sms_a80), 933 SCR_COPY (sizeof(struct sym_tcbh)), 934}/*-------------------------< _SMS_A80 >-------------------------*/,{ 935 0, 936 HADDR_1 (tcb_head), 937 /* 938 * We expect MESSAGE IN phase. 939 * If not, get help from the C code. 940 */ 941 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 942 SIR_RESEL_NO_MSG_IN, 943}/*-------------------------< RESELECTED1 >----------------------*/,{ 944 /* 945 * Load the synchronous transfer registers. 946 */ 947 SCR_COPY (1), 948 HADDR_1 (tcb_head.wval), 949 RADDR_1 (scntl3), 950 SCR_COPY (1), 951 HADDR_1 (tcb_head.sval), 952 RADDR_1 (sxfer), 953 /* 954 * Get the IDENTIFY message. 955 */ 956 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 957 HADDR_1 (msgin), 958 /* 959 * If IDENTIFY LUN #0, use a faster path 960 * to find the LCB structure. 961 */ 962 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), 963 PADDR_A (resel_lun0), 964 /* 965 * If message isn't an IDENTIFY, 966 * tell the C code about. 967 */ 968 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), 969 SIR_RESEL_NO_IDENTIFY, 970 /* 971 * It is an IDENTIFY message, 972 * Load the LUN control block address. 973 */ 974 SCR_COPY (4), 975 HADDR_1 (tcb_head.luntbl_sa), 976 RADDR_1 (dsa), 977 SCR_SFBR_REG (dsa, SCR_SHL, 0), 978 0, 979 SCR_REG_REG (dsa, SCR_SHL, 0), 980 0, 981 SCR_REG_REG (dsa, SCR_AND, 0xfc), 982 0, 983 SCR_COPY (4), 984 RADDR_1 (dsa), 985 PADDR_A (_sms_a90), 986 SCR_COPY (4), 987}/*-------------------------< _SMS_A90 >-------------------------*/,{ 988 0, 989 RADDR_1 (dsa), 990 SCR_JUMPR, 991 12, 992}/*-------------------------< RESEL_LUN0 >-----------------------*/,{ 993 /* 994 * LUN 0 special case (but usual one :)) 995 */ 996 SCR_COPY (4), 997 HADDR_1 (tcb_head.lun0_sa), 998 RADDR_1 (dsa), 999 /* 1000 * Jump indirectly to the reselect action for this LUN. 1001 * (lcb.head.resel_sa assumed at offset zero of lcb). 1002 */ 1003 SCR_COPY (4), 1004 RADDR_1 (dsa), 1005 PADDR_A (_sms_a100), 1006 SCR_COPY (4), 1007}/*-------------------------< _SMS_A100 >------------------------*/,{ 1008 0, 1009 RADDR_1 (temp), 1010 SCR_RETURN, 1011 0, 1012 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */ 1013}/*-------------------------< RESEL_TAG >------------------------*/,{ 1014 /* 1015 * ACK the IDENTIFY previously received. 1016 */ 1017 SCR_CLR (SCR_ACK), 1018 0, 1019 /* 1020 * It shall be a tagged command. 1021 * Read SIMPLE+TAG. 1022 * The C code will deal with errors. 1023 * Aggressive optimization, isn't it? :) 1024 */ 1025 SCR_MOVE_ABS (2) ^ SCR_MSG_IN, 1026 HADDR_1 (msgin), 1027 /* 1028 * Copy the LCB header to a fixed place in 1029 * the HCB using self-modifying SCRIPTS. 1030 */ 1031 SCR_COPY (4), 1032 RADDR_1 (dsa), 1033 PADDR_A (_sms_a110), 1034 SCR_COPY (sizeof(struct sym_lcbh)), 1035}/*-------------------------< _SMS_A110 >------------------------*/,{ 1036 0, 1037 HADDR_1 (lcb_head), 1038 /* 1039 * Load the pointer to the tagged task 1040 * table for this LUN. 1041 */ 1042 SCR_COPY (4), 1043 HADDR_1 (lcb_head.itlq_tbl_sa), 1044 RADDR_1 (dsa), 1045 /* 1046 * The SIDL still contains the TAG value. 1047 * Aggressive optimization, isn't it? :):) 1048 */ 1049 SCR_REG_SFBR (sidl, SCR_SHL, 0), 1050 0, 1051#if SYM_CONF_MAX_TASK*4 > 512 1052 SCR_JUMPR ^ IFFALSE (CARRYSET), 1053 8, 1054 SCR_REG_REG (dsa1, SCR_OR, 2), 1055 0, 1056 SCR_REG_REG (sfbr, SCR_SHL, 0), 1057 0, 1058 SCR_JUMPR ^ IFFALSE (CARRYSET), 1059 8, 1060 SCR_REG_REG (dsa1, SCR_OR, 1), 1061 0, 1062#elif SYM_CONF_MAX_TASK*4 > 256 1063 SCR_JUMPR ^ IFFALSE (CARRYSET), 1064 8, 1065 SCR_REG_REG (dsa1, SCR_OR, 1), 1066 0, 1067#endif 1068 /* 1069 * Retrieve the DSA of this task. 1070 * JUMP indirectly to the restart point of the CCB. 1071 */ 1072 SCR_SFBR_REG (dsa, SCR_AND, 0xfc), 1073 0, 1074 SCR_COPY (4), 1075 RADDR_1 (dsa), 1076 PADDR_A (_sms_a120), 1077 SCR_COPY (4), 1078}/*-------------------------< _SMS_A120 >------------------------*/,{ 1079 0, 1080 RADDR_1 (dsa), 1081}/*-------------------------< RESEL_GO >-------------------------*/,{ 1082 SCR_COPY (4), 1083 RADDR_1 (dsa), 1084 PADDR_A (_sms_a130), 1085 /* 1086 * Move 'ccb.phys.head.go' action to 1087 * scratch/scratch1. So scratch1 will 1088 * contain the 'restart' field of the 1089 * 'go' structure. 1090 */ 1091 SCR_COPY (8), 1092}/*-------------------------< _SMS_A130 >------------------------*/,{ 1093 0, 1094 PADDR_B (scratch), 1095 SCR_COPY (4), 1096 PADDR_B (scratch1), /* phys.head.go.restart */ 1097 RADDR_1 (temp), 1098 SCR_RETURN, 1099 0, 1100 /* In normal situations we branch to RESEL_DSA */ 1101}/*-------------------------< RESEL_DSA >------------------------*/,{ 1102 /* 1103 * ACK the IDENTIFY or TAG previously received. 1104 */ 1105 SCR_CLR (SCR_ACK), 1106 0, 1107}/*-------------------------< RESEL_DSA1 >-----------------------*/,{ 1108 /* 1109 * Copy the CCB header to a fixed location 1110 * in the HCB using self-modifying SCRIPTS. 1111 */ 1112 SCR_COPY (4), 1113 RADDR_1 (dsa), 1114 PADDR_A (_sms_a140), 1115 SCR_COPY (sizeof(struct sym_ccbh)), 1116}/*-------------------------< _SMS_A140 >------------------------*/,{ 1117 0, 1118 HADDR_1 (ccb_head), 1119 /* 1120 * Initialize the status register 1121 */ 1122 SCR_COPY (4), 1123 HADDR_1 (ccb_head.status), 1124 RADDR_1 (scr0), 1125 /* 1126 * Jump to dispatcher. 1127 */ 1128 SCR_JUMP, 1129 PADDR_A (dispatch), 1130}/*-------------------------< RESEL_NO_TAG >---------------------*/,{ 1131 /* 1132 * Copy the LCB header to a fixed place in 1133 * the HCB using self-modifying SCRIPTS. 1134 */ 1135 SCR_COPY (4), 1136 RADDR_1 (dsa), 1137 PADDR_A (_sms_a145), 1138 SCR_COPY (sizeof(struct sym_lcbh)), 1139}/*-------------------------< _SMS_A145 >------------------------*/,{ 1140 0, 1141 HADDR_1 (lcb_head), 1142 /* 1143 * Load the DSA with the unique ITL task. 1144 */ 1145 SCR_COPY (4), 1146 HADDR_1 (lcb_head.itl_task_sa), 1147 RADDR_1 (dsa), 1148 SCR_JUMP, 1149 PADDR_A (resel_go), 1150}/*-------------------------< DATA_IN >--------------------------*/,{ 1151/* 1152 * Because the size depends on the 1153 * #define SYM_CONF_MAX_SG parameter, 1154 * it is filled in at runtime. 1155 * 1156 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1157 * || SCR_CHMOV_TBL ^ SCR_DATA_IN, 1158 * || offsetof (struct sym_dsb, data[ i]), 1159 * ##========================================== 1160 */ 11610 1162}/*-------------------------< DATA_IN2 >-------------------------*/,{ 1163 SCR_CALL, 1164 PADDR_A (datai_done), 1165 SCR_JUMP, 1166 PADDR_B (data_ovrun), 1167}/*-------------------------< DATA_OUT >-------------------------*/,{ 1168/* 1169 * Because the size depends on the 1170 * #define SYM_CONF_MAX_SG parameter, 1171 * it is filled in at runtime. 1172 * 1173 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1174 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1175 * || offsetof (struct sym_dsb, data[ i]), 1176 * ##========================================== 1177 */ 11780 1179}/*-------------------------< DATA_OUT2 >------------------------*/,{ 1180 SCR_CALL, 1181 PADDR_A (datao_done), 1182 SCR_JUMP, 1183 PADDR_B (data_ovrun), 1184}/*-------------------------< PM0_DATA >-------------------------*/,{ 1185 /* 1186 * Read our host flags to SFBR, so we will be able 1187 * to check against the data direction we expect. 1188 */ 1189 SCR_FROM_REG (HF_REG), 1190 0, 1191 /* 1192 * Check against actual DATA PHASE. 1193 */ 1194 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1195 PADDR_A (pm0_data_out), 1196 /* 1197 * Actual phase is DATA IN. 1198 * Check against expected direction. 1199 */ 1200 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1201 PADDR_B (data_ovrun), 1202 /* 1203 * Keep track we are moving data from the 1204 * PM0 DATA mini-script. 1205 */ 1206 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1207 0, 1208 /* 1209 * Move the data to memory. 1210 */ 1211 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1212 offsetof (struct sym_ccb, phys.pm0.sg), 1213 SCR_JUMP, 1214 PADDR_A (pm0_data_end), 1215}/*-------------------------< PM0_DATA_OUT >---------------------*/,{ 1216 /* 1217 * Actual phase is DATA OUT. 1218 * Check against expected direction. 1219 */ 1220 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1221 PADDR_B (data_ovrun), 1222 /* 1223 * Keep track we are moving data from the 1224 * PM0 DATA mini-script. 1225 */ 1226 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1227 0, 1228 /* 1229 * Move the data from memory. 1230 */ 1231 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1232 offsetof (struct sym_ccb, phys.pm0.sg), 1233}/*-------------------------< PM0_DATA_END >---------------------*/,{ 1234 /* 1235 * Clear the flag that told we were moving 1236 * data from the PM0 DATA mini-script. 1237 */ 1238 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)), 1239 0, 1240 /* 1241 * Return to the previous DATA script which 1242 * is guaranteed by design (if no bug) to be 1243 * the main DATA script for this transfer. 1244 */ 1245 SCR_COPY (4), 1246 RADDR_1 (dsa), 1247 RADDR_1 (scratcha), 1248 SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm0.ret)), 1249 0, 1250}/*-------------------------< PM_DATA_END >----------------------*/,{ 1251 SCR_COPY (4), 1252 RADDR_1 (scratcha), 1253 PADDR_A (_sms_a150), 1254 SCR_COPY (4), 1255}/*-------------------------< _SMS_A150 >------------------------*/,{ 1256 0, 1257 RADDR_1 (temp), 1258 SCR_RETURN, 1259 0, 1260}/*-------------------------< PM1_DATA >-------------------------*/,{ 1261 /* 1262 * Read our host flags to SFBR, so we will be able 1263 * to check against the data direction we expect. 1264 */ 1265 SCR_FROM_REG (HF_REG), 1266 0, 1267 /* 1268 * Check against actual DATA PHASE. 1269 */ 1270 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1271 PADDR_A (pm1_data_out), 1272 /* 1273 * Actual phase is DATA IN. 1274 * Check against expected direction. 1275 */ 1276 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1277 PADDR_B (data_ovrun), 1278 /* 1279 * Keep track we are moving data from the 1280 * PM1 DATA mini-script. 1281 */ 1282 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1283 0, 1284 /* 1285 * Move the data to memory. 1286 */ 1287 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1288 offsetof (struct sym_ccb, phys.pm1.sg), 1289 SCR_JUMP, 1290 PADDR_A (pm1_data_end), 1291}/*-------------------------< PM1_DATA_OUT >---------------------*/,{ 1292 /* 1293 * Actual phase is DATA OUT. 1294 * Check against expected direction. 1295 */ 1296 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1297 PADDR_B (data_ovrun), 1298 /* 1299 * Keep track we are moving data from the 1300 * PM1 DATA mini-script. 1301 */ 1302 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1303 0, 1304 /* 1305 * Move the data from memory. 1306 */ 1307 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1308 offsetof (struct sym_ccb, phys.pm1.sg), 1309}/*-------------------------< PM1_DATA_END >---------------------*/,{ 1310 /* 1311 * Clear the flag that told we were moving 1312 * data from the PM1 DATA mini-script. 1313 */ 1314 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)), 1315 0, 1316 /* 1317 * Return to the previous DATA script which 1318 * is guaranteed by design (if no bug) to be 1319 * the main DATA script for this transfer. 1320 */ 1321 SCR_COPY (4), 1322 RADDR_1 (dsa), 1323 RADDR_1 (scratcha), 1324 SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm1.ret)), 1325 0, 1326 SCR_JUMP, 1327 PADDR_A (pm_data_end), 1328}/*--------------------------<>----------------------------------*/ 1329}; 1330 1331static struct SYM_FWB_SCR SYM_FWB_SCR = { 1332/*-------------------------< NO_DATA >--------------------------*/ { 1333 SCR_JUMP, 1334 PADDR_B (data_ovrun), 1335}/*-------------------------< SEL_FOR_ABORT >--------------------*/,{ 1336 /* 1337 * We are jumped here by the C code, if we have 1338 * some target to reset or some disconnected 1339 * job to abort. Since error recovery is a serious 1340 * busyness, we will really reset the SCSI BUS, if 1341 * case of a SCSI interrupt occurring in this path. 1342 */ 1343 1344#ifdef SYM_CONF_TARGET_ROLE_SUPPORT 1345 /* 1346 * Set initiator mode. 1347 */ 1348 SCR_CLR (SCR_TRG), 1349 0, 1350#endif 1351 /* 1352 * And try to select this target. 1353 */ 1354 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel), 1355 PADDR_A (reselect), 1356 /* 1357 * Wait for the selection to complete or 1358 * the selection to time out. 1359 */ 1360 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1361 -8, 1362 /* 1363 * Call the C code. 1364 */ 1365 SCR_INT, 1366 SIR_TARGET_SELECTED, 1367 /* 1368 * The C code should let us continue here. 1369 * Send the 'kiss of death' message. 1370 * We expect an immediate disconnect once 1371 * the target has eaten the message. 1372 */ 1373 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1374 0, 1375 SCR_MOVE_TBL ^ SCR_MSG_OUT, 1376 offsetof (struct sym_hcb, abrt_tbl), 1377 SCR_CLR (SCR_ACK|SCR_ATN), 1378 0, 1379 SCR_WAIT_DISC, 1380 0, 1381 /* 1382 * Tell the C code that we are done. 1383 */ 1384 SCR_INT, 1385 SIR_ABORT_SENT, 1386}/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{ 1387 /* 1388 * Jump at scheduler. 1389 */ 1390 SCR_JUMP, 1391 PADDR_A (start), 1392}/*-------------------------< MSG_IN_ETC >-----------------------*/,{ 1393 /* 1394 * If it is an EXTENDED (variable size message) 1395 * Handle it. 1396 */ 1397 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)), 1398 PADDR_B (msg_extended), 1399 /* 1400 * Let the C code handle any other 1401 * 1 byte message. 1402 */ 1403 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)), 1404 PADDR_B (msg_received), 1405 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)), 1406 PADDR_B (msg_received), 1407 /* 1408 * We donnot handle 2 bytes messages from SCRIPTS. 1409 * So, let the C code deal with these ones too. 1410 */ 1411 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)), 1412 PADDR_B (msg_weird_seen), 1413 SCR_CLR (SCR_ACK), 1414 0, 1415 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1416 HADDR_1 (msgin[1]), 1417}/*-------------------------< MSG_RECEIVED >---------------------*/,{ 1418 SCR_COPY (4), /* DUMMY READ */ 1419 HADDR_1 (scratch), 1420 RADDR_1 (scratcha), 1421 SCR_INT, 1422 SIR_MSG_RECEIVED, 1423}/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{ 1424 SCR_COPY (4), /* DUMMY READ */ 1425 HADDR_1 (scratch), 1426 RADDR_1 (scratcha), 1427 SCR_INT, 1428 SIR_MSG_WEIRD, 1429}/*-------------------------< MSG_EXTENDED >---------------------*/,{ 1430 /* 1431 * Clear ACK and get the next byte 1432 * assumed to be the message length. 1433 */ 1434 SCR_CLR (SCR_ACK), 1435 0, 1436 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1437 HADDR_1 (msgin[1]), 1438 /* 1439 * Try to catch some unlikely situations as 0 length 1440 * or too large the length. 1441 */ 1442 SCR_JUMP ^ IFTRUE (DATA (0)), 1443 PADDR_B (msg_weird_seen), 1444 SCR_TO_REG (scratcha), 1445 0, 1446 SCR_REG_REG (sfbr, SCR_ADD, (256-8)), 1447 0, 1448 SCR_JUMP ^ IFTRUE (CARRYSET), 1449 PADDR_B (msg_weird_seen), 1450 /* 1451 * We donnot handle extended messages from SCRIPTS. 1452 * Read the amount of data correponding to the 1453 * message length and call the C code. 1454 */ 1455 SCR_COPY (1), 1456 RADDR_1 (scratcha), 1457 PADDR_B (_sms_b10), 1458 SCR_CLR (SCR_ACK), 1459 0, 1460}/*-------------------------< _SMS_B10 >-------------------------*/,{ 1461 SCR_MOVE_ABS (0) ^ SCR_MSG_IN, 1462 HADDR_1 (msgin[2]), 1463 SCR_JUMP, 1464 PADDR_B (msg_received), 1465}/*-------------------------< MSG_BAD >--------------------------*/,{ 1466 /* 1467 * unimplemented message - reject it. 1468 */ 1469 SCR_INT, 1470 SIR_REJECT_TO_SEND, 1471 SCR_SET (SCR_ATN), 1472 0, 1473 SCR_JUMP, 1474 PADDR_A (clrack), 1475}/*-------------------------< MSG_WEIRD >------------------------*/,{ 1476 /* 1477 * weird message received 1478 * ignore all MSG IN phases and reject it. 1479 */ 1480 SCR_INT, 1481 SIR_REJECT_TO_SEND, 1482 SCR_SET (SCR_ATN), 1483 0, 1484}/*-------------------------< MSG_WEIRD1 >-----------------------*/,{ 1485 SCR_CLR (SCR_ACK), 1486 0, 1487 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 1488 PADDR_A (dispatch), 1489 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1490 HADDR_1 (scratch), 1491 SCR_JUMP, 1492 PADDR_B (msg_weird1), 1493}/*-------------------------< WDTR_RESP >------------------------*/,{ 1494 /* 1495 * let the target fetch our answer. 1496 */ 1497 SCR_SET (SCR_ATN), 1498 0, 1499 SCR_CLR (SCR_ACK), 1500 0, 1501 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1502 PADDR_B (nego_bad_phase), 1503}/*-------------------------< SEND_WDTR >------------------------*/,{ 1504 /* 1505 * Send the M_X_WIDE_REQ 1506 */ 1507 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT, 1508 HADDR_1 (msgout), 1509 SCR_JUMP, 1510 PADDR_B (msg_out_done), 1511}/*-------------------------< SDTR_RESP >------------------------*/,{ 1512 /* 1513 * let the target fetch our answer. 1514 */ 1515 SCR_SET (SCR_ATN), 1516 0, 1517 SCR_CLR (SCR_ACK), 1518 0, 1519 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1520 PADDR_B (nego_bad_phase), 1521}/*-------------------------< SEND_SDTR >------------------------*/,{ 1522 /* 1523 * Send the M_X_SYNC_REQ 1524 */ 1525 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT, 1526 HADDR_1 (msgout), 1527 SCR_JUMP, 1528 PADDR_B (msg_out_done), 1529}/*-------------------------< PPR_RESP >-------------------------*/,{ 1530 /* 1531 * let the target fetch our answer. 1532 */ 1533 SCR_SET (SCR_ATN), 1534 0, 1535 SCR_CLR (SCR_ACK), 1536 0, 1537 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1538 PADDR_B (nego_bad_phase), 1539}/*-------------------------< SEND_PPR >-------------------------*/,{ 1540 /* 1541 * Send the M_X_PPR_REQ 1542 */ 1543 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT, 1544 HADDR_1 (msgout), 1545 SCR_JUMP, 1546 PADDR_B (msg_out_done), 1547}/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{ 1548 SCR_INT, 1549 SIR_NEGO_PROTO, 1550 SCR_JUMP, 1551 PADDR_A (dispatch), 1552}/*-------------------------< MSG_OUT >--------------------------*/,{ 1553 /* 1554 * The target requests a message. 1555 * We donnot send messages that may 1556 * require the device to go to bus free. 1557 */ 1558 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1559 HADDR_1 (msgout), 1560 /* 1561 * ... wait for the next phase 1562 * if it's a message out, send it again, ... 1563 */ 1564 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 1565 PADDR_B (msg_out), 1566}/*-------------------------< MSG_OUT_DONE >---------------------*/,{ 1567 /* 1568 * Let the C code be aware of the 1569 * sent message and clear the message. 1570 */ 1571 SCR_INT, 1572 SIR_MSG_OUT_DONE, 1573 /* 1574 * ... and process the next phase 1575 */ 1576 SCR_JUMP, 1577 PADDR_A (dispatch), 1578}/*-------------------------< DATA_OVRUN >-----------------------*/,{ 1579 /* 1580 * Zero scratcha that will count the 1581 * extras bytes. 1582 */ 1583 SCR_COPY (4), 1584 PADDR_B (zero), 1585 RADDR_1 (scratcha), 1586}/*-------------------------< DATA_OVRUN1 >----------------------*/,{ 1587 /* 1588 * The target may want to transfer too much data. 1589 * 1590 * If phase is DATA OUT write 1 byte and count it. 1591 */ 1592 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)), 1593 16, 1594 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT, 1595 HADDR_1 (scratch), 1596 SCR_JUMP, 1597 PADDR_B (data_ovrun2), 1598 /* 1599 * If WSR is set, clear this condition, and 1600 * count this byte. 1601 */ 1602 SCR_FROM_REG (scntl2), 1603 0, 1604 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), 1605 16, 1606 SCR_REG_REG (scntl2, SCR_OR, WSR), 1607 0, 1608 SCR_JUMP, 1609 PADDR_B (data_ovrun2), 1610 /* 1611 * Finally check against DATA IN phase. 1612 * Signal data overrun to the C code 1613 * and jump to dispatcher if not so. 1614 * Read 1 byte otherwise and count it. 1615 */ 1616 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)), 1617 16, 1618 SCR_INT, 1619 SIR_DATA_OVERRUN, 1620 SCR_JUMP, 1621 PADDR_A (dispatch), 1622 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN, 1623 HADDR_1 (scratch), 1624}/*-------------------------< DATA_OVRUN2 >----------------------*/,{ 1625 /* 1626 * Count this byte. 1627 * This will allow to return a negative 1628 * residual to user. 1629 */ 1630 SCR_REG_REG (scratcha, SCR_ADD, 0x01), 1631 0, 1632 SCR_REG_REG (scratcha1, SCR_ADDC, 0), 1633 0, 1634 SCR_REG_REG (scratcha2, SCR_ADDC, 0), 1635 0, 1636 /* 1637 * .. and repeat as required. 1638 */ 1639 SCR_JUMP, 1640 PADDR_B (data_ovrun1), 1641}/*-------------------------< ABORT_RESEL >----------------------*/,{ 1642 SCR_SET (SCR_ATN), 1643 0, 1644 SCR_CLR (SCR_ACK), 1645 0, 1646 /* 1647 * send the abort/abortag/reset message 1648 * we expect an immediate disconnect 1649 */ 1650 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1651 0, 1652 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1653 HADDR_1 (msgout), 1654 SCR_CLR (SCR_ACK|SCR_ATN), 1655 0, 1656 SCR_WAIT_DISC, 1657 0, 1658 SCR_INT, 1659 SIR_RESEL_ABORTED, 1660 SCR_JUMP, 1661 PADDR_A (start), 1662}/*-------------------------< RESEND_IDENT >---------------------*/,{ 1663 /* 1664 * The target stays in MSG OUT phase after having acked 1665 * Identify [+ Tag [+ Extended message ]]. Targets shall 1666 * behave this way on parity error. 1667 * We must send it again all the messages. 1668 */ 1669 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */ 1670 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */ 1671 SCR_JUMP, 1672 PADDR_A (send_ident), 1673}/*-------------------------< IDENT_BREAK >----------------------*/,{ 1674 SCR_CLR (SCR_ATN), 1675 0, 1676 SCR_JUMP, 1677 PADDR_A (select2), 1678}/*-------------------------< IDENT_BREAK_ATN >------------------*/,{ 1679 SCR_SET (SCR_ATN), 1680 0, 1681 SCR_JUMP, 1682 PADDR_A (select2), 1683}/*-------------------------< SDATA_IN >-------------------------*/,{ 1684 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1685 offsetof (struct sym_dsb, sense), 1686 SCR_CALL, 1687 PADDR_A (datai_done), 1688 SCR_JUMP, 1689 PADDR_B (data_ovrun), 1690}/*-------------------------< RESEL_BAD_LUN >--------------------*/,{ 1691 /* 1692 * Message is an IDENTIFY, but lun is unknown. 1693 * Signal problem to C code for logging the event. 1694 * Send a M_ABORT to clear all pending tasks. 1695 */ 1696 SCR_INT, 1697 SIR_RESEL_BAD_LUN, 1698 SCR_JUMP, 1699 PADDR_B (abort_resel), 1700}/*-------------------------< BAD_I_T_L >------------------------*/,{ 1701 /* 1702 * We donnot have a task for that I_T_L. 1703 * Signal problem to C code for logging the event. 1704 * Send a M_ABORT message. 1705 */ 1706 SCR_INT, 1707 SIR_RESEL_BAD_I_T_L, 1708 SCR_JUMP, 1709 PADDR_B (abort_resel), 1710}/*-------------------------< BAD_I_T_L_Q >----------------------*/,{ 1711 /* 1712 * We donnot have a task that matches the tag. 1713 * Signal problem to C code for logging the event. 1714 * Send a M_ABORTTAG message. 1715 */ 1716 SCR_INT, 1717 SIR_RESEL_BAD_I_T_L_Q, 1718 SCR_JUMP, 1719 PADDR_B (abort_resel), 1720}/*-------------------------< BAD_STATUS >-----------------------*/,{ 1721 /* 1722 * Anything different from INTERMEDIATE 1723 * CONDITION MET should be a bad SCSI status, 1724 * given that GOOD status has already been tested. 1725 * Call the C code. 1726 */ 1727 SCR_COPY (4), 1728 PADDR_B (startpos), 1729 RADDR_1 (scratcha), 1730 SCR_INT ^ IFFALSE (DATA (S_COND_MET)), 1731 SIR_BAD_SCSI_STATUS, 1732 SCR_RETURN, 1733 0, 1734}/*-------------------------< WSR_MA_HELPER >--------------------*/,{ 1735 /* 1736 * Helper for the C code when WSR bit is set. 1737 * Perform the move of the residual byte. 1738 */ 1739 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1740 offsetof (struct sym_ccb, phys.wresid), 1741 SCR_JUMP, 1742 PADDR_A (dispatch), 1743 1744}/*-------------------------< ZERO >-----------------------------*/,{ 1745 SCR_DATA_ZERO, 1746}/*-------------------------< SCRATCH >--------------------------*/,{ 1747 SCR_DATA_ZERO, /* MUST BE BEFORE SCRATCH1 */ 1748}/*-------------------------< SCRATCH1 >-------------------------*/,{ 1749 SCR_DATA_ZERO, 1750}/*-------------------------< PREV_DONE >------------------------*/,{ 1751 SCR_DATA_ZERO, /* MUST BE BEFORE DONE_POS ! */ 1752}/*-------------------------< DONE_POS >-------------------------*/,{ 1753 SCR_DATA_ZERO, 1754}/*-------------------------< NEXTJOB >--------------------------*/,{ 1755 SCR_DATA_ZERO, /* MUST BE BEFORE STARTPOS ! */ 1756}/*-------------------------< STARTPOS >-------------------------*/,{ 1757 SCR_DATA_ZERO, 1758}/*-------------------------< TARGTBL >--------------------------*/,{ 1759 SCR_DATA_ZERO, 1760}/*--------------------------<>----------------------------------*/ 1761}; 1762 1763static struct SYM_FWZ_SCR SYM_FWZ_SCR = { 1764 /*-------------------------< SNOOPTEST >------------------------*/{ 1765 /* 1766 * Read the variable. 1767 */ 1768 SCR_COPY (4), 1769 HADDR_1 (scratch), 1770 RADDR_1 (scratcha), 1771 /* 1772 * Write the variable. 1773 */ 1774 SCR_COPY (4), 1775 RADDR_1 (temp), 1776 HADDR_1 (scratch), 1777 /* 1778 * Read back the variable. 1779 */ 1780 SCR_COPY (4), 1781 HADDR_1 (scratch), 1782 RADDR_1 (temp), 1783}/*-------------------------< SNOOPEND >-------------------------*/,{ 1784 /* 1785 * And stop. 1786 */ 1787 SCR_INT, 1788 99, 1789}/*--------------------------<>----------------------------------*/ 1790}; 1791