1/* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: aic7xxx_pci.c,v 1.1.1.1 2007/08/03 18:52:58 Exp $ 43 */ 44 45#ifdef __linux__ 46#include "aic7xxx_osm.h" 47#include "aic7xxx_inline.h" 48#include "aic7xxx_93cx6.h" 49#else 50#include <dev/aic7xxx/aic7xxx_osm.h> 51#include <dev/aic7xxx/aic7xxx_inline.h> 52#include <dev/aic7xxx/aic7xxx_93cx6.h> 53#endif 54 55#include "aic7xxx_pci.h" 56 57static __inline uint64_t 58ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 59{ 60 uint64_t id; 61 62 id = subvendor 63 | (subdevice << 16) 64 | ((uint64_t)vendor << 32) 65 | ((uint64_t)device << 48); 66 67 return (id); 68} 69 70#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 71#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 72 73#define DEVID_9005_TYPE(id) ((id) & 0xF) 74#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 75#define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 76#define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 77#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 78 79#define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 80#define DEVID_9005_MAXRATE_U160 0x0 81#define DEVID_9005_MAXRATE_ULTRA2 0x1 82#define DEVID_9005_MAXRATE_ULTRA 0x2 83#define DEVID_9005_MAXRATE_FAST 0x3 84 85#define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 86 87#define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 88#define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 89 90#define SUBID_9005_TYPE(id) ((id) & 0xF) 91#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 92#define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 93#define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 94#define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 95 96#define SUBID_9005_TYPE_KNOWN(id) \ 97 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 98 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 99 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 100 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 101 102#define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 103#define SUBID_9005_MAXRATE_ULTRA2 0x0 104#define SUBID_9005_MAXRATE_ULTRA 0x1 105#define SUBID_9005_MAXRATE_U160 0x2 106#define SUBID_9005_MAXRATE_RESERVED 0x3 107 108#define SUBID_9005_SEEPTYPE(id) \ 109 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 110 ? ((id) & 0xC0) >> 6 \ 111 : ((id) & 0x300) >> 8) 112#define SUBID_9005_SEEPTYPE_NONE 0x0 113#define SUBID_9005_SEEPTYPE_1K 0x1 114#define SUBID_9005_SEEPTYPE_2K_4K 0x2 115#define SUBID_9005_SEEPTYPE_RESERVED 0x3 116#define SUBID_9005_AUTOTERM(id) \ 117 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 118 ? (((id) & 0x400) >> 10) == 0 \ 119 : (((id) & 0x40) >> 6) == 0) 120 121#define SUBID_9005_NUMCHAN(id) \ 122 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 123 ? ((id) & 0x300) >> 8 \ 124 : ((id) & 0xC00) >> 10) 125 126#define SUBID_9005_LEGACYCONN(id) \ 127 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 128 ? 0 \ 129 : ((id) & 0x80) >> 7) 130 131#define SUBID_9005_MFUNCENB(id) \ 132 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 133 ? ((id) & 0x800) >> 11 \ 134 : ((id) & 0x1000) >> 12) 135/* 136 * Informational only. Should use chip register to be 137 * certain, but may be use in identification strings. 138 */ 139#define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 140#define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 141#define SUBID_9005_CARD_SEDIFF_MASK 0x8000 142 143static ahc_device_setup_t ahc_aic785X_setup; 144static ahc_device_setup_t ahc_aic7860_setup; 145static ahc_device_setup_t ahc_apa1480_setup; 146static ahc_device_setup_t ahc_aic7870_setup; 147static ahc_device_setup_t ahc_aic7870h_setup; 148static ahc_device_setup_t ahc_aha394X_setup; 149static ahc_device_setup_t ahc_aha394Xh_setup; 150static ahc_device_setup_t ahc_aha494X_setup; 151static ahc_device_setup_t ahc_aha494Xh_setup; 152static ahc_device_setup_t ahc_aha398X_setup; 153static ahc_device_setup_t ahc_aic7880_setup; 154static ahc_device_setup_t ahc_aic7880h_setup; 155static ahc_device_setup_t ahc_aha2940Pro_setup; 156static ahc_device_setup_t ahc_aha394XU_setup; 157static ahc_device_setup_t ahc_aha394XUh_setup; 158static ahc_device_setup_t ahc_aha398XU_setup; 159static ahc_device_setup_t ahc_aic7890_setup; 160static ahc_device_setup_t ahc_aic7892_setup; 161static ahc_device_setup_t ahc_aic7895_setup; 162static ahc_device_setup_t ahc_aic7895h_setup; 163static ahc_device_setup_t ahc_aic7896_setup; 164static ahc_device_setup_t ahc_aic7899_setup; 165static ahc_device_setup_t ahc_aha29160C_setup; 166static ahc_device_setup_t ahc_raid_setup; 167static ahc_device_setup_t ahc_aha394XX_setup; 168static ahc_device_setup_t ahc_aha494XX_setup; 169static ahc_device_setup_t ahc_aha398XX_setup; 170 171static struct ahc_pci_identity ahc_pci_ident_table [] = 172{ 173 /* aic7850 based controllers */ 174 { 175 ID_AHA_2902_04_10_15_20C_30C, 176 ID_ALL_MASK, 177 "Adaptec 2902/04/10/15/20C/30C SCSI adapter", 178 ahc_aic785X_setup 179 }, 180 /* aic7860 based controllers */ 181 { 182 ID_AHA_2930CU, 183 ID_ALL_MASK, 184 "Adaptec 2930CU SCSI adapter", 185 ahc_aic7860_setup 186 }, 187 { 188 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 189 ID_DEV_VENDOR_MASK, 190 "Adaptec 1480A Ultra SCSI adapter", 191 ahc_apa1480_setup 192 }, 193 { 194 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 195 ID_DEV_VENDOR_MASK, 196 "Adaptec 2940A Ultra SCSI adapter", 197 ahc_aic7860_setup 198 }, 199 { 200 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 201 ID_DEV_VENDOR_MASK, 202 "Adaptec 2940A/CN Ultra SCSI adapter", 203 ahc_aic7860_setup 204 }, 205 { 206 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 207 ID_DEV_VENDOR_MASK, 208 "Adaptec 2930C Ultra SCSI adapter (VAR)", 209 ahc_aic7860_setup 210 }, 211 /* aic7870 based controllers */ 212 { 213 ID_AHA_2940, 214 ID_ALL_MASK, 215 "Adaptec 2940 SCSI adapter", 216 ahc_aic7870_setup 217 }, 218 { 219 ID_AHA_3940, 220 ID_ALL_MASK, 221 "Adaptec 3940 SCSI adapter", 222 ahc_aha394X_setup 223 }, 224 { 225 ID_AHA_398X, 226 ID_ALL_MASK, 227 "Adaptec 398X SCSI RAID adapter", 228 ahc_aha398X_setup 229 }, 230 { 231 ID_AHA_2944, 232 ID_ALL_MASK, 233 "Adaptec 2944 SCSI adapter", 234 ahc_aic7870h_setup 235 }, 236 { 237 ID_AHA_3944, 238 ID_ALL_MASK, 239 "Adaptec 3944 SCSI adapter", 240 ahc_aha394Xh_setup 241 }, 242 { 243 ID_AHA_4944, 244 ID_ALL_MASK, 245 "Adaptec 4944 SCSI adapter", 246 ahc_aha494Xh_setup 247 }, 248 /* aic7880 based controllers */ 249 { 250 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 251 ID_DEV_VENDOR_MASK, 252 "Adaptec 2940 Ultra SCSI adapter", 253 ahc_aic7880_setup 254 }, 255 { 256 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 257 ID_DEV_VENDOR_MASK, 258 "Adaptec 3940 Ultra SCSI adapter", 259 ahc_aha394XU_setup 260 }, 261 { 262 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 263 ID_DEV_VENDOR_MASK, 264 "Adaptec 2944 Ultra SCSI adapter", 265 ahc_aic7880h_setup 266 }, 267 { 268 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 269 ID_DEV_VENDOR_MASK, 270 "Adaptec 3944 Ultra SCSI adapter", 271 ahc_aha394XUh_setup 272 }, 273 { 274 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 275 ID_DEV_VENDOR_MASK, 276 "Adaptec 398X Ultra SCSI RAID adapter", 277 ahc_aha398XU_setup 278 }, 279 { 280 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 281 ID_DEV_VENDOR_MASK, 282 "Adaptec 4944 Ultra SCSI adapter", 283 ahc_aic7880h_setup 284 }, 285 { 286 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 287 ID_DEV_VENDOR_MASK, 288 "Adaptec 2930 Ultra SCSI adapter", 289 ahc_aic7880_setup 290 }, 291 { 292 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 293 ID_DEV_VENDOR_MASK, 294 "Adaptec 2940 Pro Ultra SCSI adapter", 295 ahc_aha2940Pro_setup 296 }, 297 { 298 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 299 ID_DEV_VENDOR_MASK, 300 "Adaptec 2940/CN Ultra SCSI adapter", 301 ahc_aic7880_setup 302 }, 303 /* Ignore all SISL (AAC on MB) based controllers. */ 304 { 305 ID_9005_SISL_ID, 306 ID_9005_SISL_MASK, 307 NULL, 308 NULL 309 }, 310 /* aic7890 based controllers */ 311 { 312 ID_AHA_2930U2, 313 ID_ALL_MASK, 314 "Adaptec 2930 Ultra2 SCSI adapter", 315 ahc_aic7890_setup 316 }, 317 { 318 ID_AHA_2940U2B, 319 ID_ALL_MASK, 320 "Adaptec 2940B Ultra2 SCSI adapter", 321 ahc_aic7890_setup 322 }, 323 { 324 ID_AHA_2940U2_OEM, 325 ID_ALL_MASK, 326 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 327 ahc_aic7890_setup 328 }, 329 { 330 ID_AHA_2940U2, 331 ID_ALL_MASK, 332 "Adaptec 2940 Ultra2 SCSI adapter", 333 ahc_aic7890_setup 334 }, 335 { 336 ID_AHA_2950U2B, 337 ID_ALL_MASK, 338 "Adaptec 2950 Ultra2 SCSI adapter", 339 ahc_aic7890_setup 340 }, 341 { 342 ID_AIC7890_ARO, 343 ID_ALL_MASK, 344 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 345 ahc_aic7890_setup 346 }, 347 { 348 ID_AAA_131U2, 349 ID_ALL_MASK, 350 "Adaptec AAA-131 Ultra2 RAID adapter", 351 ahc_aic7890_setup 352 }, 353 /* aic7892 based controllers */ 354 { 355 ID_AHA_29160, 356 ID_ALL_MASK, 357 "Adaptec 29160 Ultra160 SCSI adapter", 358 ahc_aic7892_setup 359 }, 360 { 361 ID_AHA_29160_CPQ, 362 ID_ALL_MASK, 363 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 364 ahc_aic7892_setup 365 }, 366 { 367 ID_AHA_29160N, 368 ID_ALL_MASK, 369 "Adaptec 29160N Ultra160 SCSI adapter", 370 ahc_aic7892_setup 371 }, 372 { 373 ID_AHA_29160C, 374 ID_ALL_MASK, 375 "Adaptec 29160C Ultra160 SCSI adapter", 376 ahc_aha29160C_setup 377 }, 378 { 379 ID_AHA_29160B, 380 ID_ALL_MASK, 381 "Adaptec 29160B Ultra160 SCSI adapter", 382 ahc_aic7892_setup 383 }, 384 { 385 ID_AHA_19160B, 386 ID_ALL_MASK, 387 "Adaptec 19160B Ultra160 SCSI adapter", 388 ahc_aic7892_setup 389 }, 390 { 391 ID_AIC7892_ARO, 392 ID_ALL_MASK, 393 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 394 ahc_aic7892_setup 395 }, 396 { 397 ID_AHA_2915_30LP, 398 ID_ALL_MASK, 399 "Adaptec 2915/30LP Ultra160 SCSI adapter", 400 ahc_aic7892_setup 401 }, 402 /* aic7895 based controllers */ 403 { 404 ID_AHA_2940U_DUAL, 405 ID_ALL_MASK, 406 "Adaptec 2940/DUAL Ultra SCSI adapter", 407 ahc_aic7895_setup 408 }, 409 { 410 ID_AHA_3940AU, 411 ID_ALL_MASK, 412 "Adaptec 3940A Ultra SCSI adapter", 413 ahc_aic7895_setup 414 }, 415 { 416 ID_AHA_3944AU, 417 ID_ALL_MASK, 418 "Adaptec 3944A Ultra SCSI adapter", 419 ahc_aic7895h_setup 420 }, 421 { 422 ID_AIC7895_ARO, 423 ID_AIC7895_ARO_MASK, 424 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 425 ahc_aic7895_setup 426 }, 427 /* aic7896/97 based controllers */ 428 { 429 ID_AHA_3950U2B_0, 430 ID_ALL_MASK, 431 "Adaptec 3950B Ultra2 SCSI adapter", 432 ahc_aic7896_setup 433 }, 434 { 435 ID_AHA_3950U2B_1, 436 ID_ALL_MASK, 437 "Adaptec 3950B Ultra2 SCSI adapter", 438 ahc_aic7896_setup 439 }, 440 { 441 ID_AHA_3950U2D_0, 442 ID_ALL_MASK, 443 "Adaptec 3950D Ultra2 SCSI adapter", 444 ahc_aic7896_setup 445 }, 446 { 447 ID_AHA_3950U2D_1, 448 ID_ALL_MASK, 449 "Adaptec 3950D Ultra2 SCSI adapter", 450 ahc_aic7896_setup 451 }, 452 { 453 ID_AIC7896_ARO, 454 ID_ALL_MASK, 455 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 456 ahc_aic7896_setup 457 }, 458 /* aic7899 based controllers */ 459 { 460 ID_AHA_3960D, 461 ID_ALL_MASK, 462 "Adaptec 3960D Ultra160 SCSI adapter", 463 ahc_aic7899_setup 464 }, 465 { 466 ID_AHA_3960D_CPQ, 467 ID_ALL_MASK, 468 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 469 ahc_aic7899_setup 470 }, 471 { 472 ID_AIC7899_ARO, 473 ID_ALL_MASK, 474 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 475 ahc_aic7899_setup 476 }, 477 /* Generic chip probes for devices we don't know 'exactly' */ 478 { 479 ID_AIC7850 & ID_DEV_VENDOR_MASK, 480 ID_DEV_VENDOR_MASK, 481 "Adaptec aic7850 SCSI adapter", 482 ahc_aic785X_setup 483 }, 484 { 485 ID_AIC7855 & ID_DEV_VENDOR_MASK, 486 ID_DEV_VENDOR_MASK, 487 "Adaptec aic7855 SCSI adapter", 488 ahc_aic785X_setup 489 }, 490 { 491 ID_AIC7859 & ID_DEV_VENDOR_MASK, 492 ID_DEV_VENDOR_MASK, 493 "Adaptec aic7859 SCSI adapter", 494 ahc_aic7860_setup 495 }, 496 { 497 ID_AIC7860 & ID_DEV_VENDOR_MASK, 498 ID_DEV_VENDOR_MASK, 499 "Adaptec aic7860 Ultra SCSI adapter", 500 ahc_aic7860_setup 501 }, 502 { 503 ID_AIC7870 & ID_DEV_VENDOR_MASK, 504 ID_DEV_VENDOR_MASK, 505 "Adaptec aic7870 SCSI adapter", 506 ahc_aic7870_setup 507 }, 508 { 509 ID_AIC7880 & ID_DEV_VENDOR_MASK, 510 ID_DEV_VENDOR_MASK, 511 "Adaptec aic7880 Ultra SCSI adapter", 512 ahc_aic7880_setup 513 }, 514 { 515 ID_AIC7890 & ID_9005_GENERIC_MASK, 516 ID_9005_GENERIC_MASK, 517 "Adaptec aic7890/91 Ultra2 SCSI adapter", 518 ahc_aic7890_setup 519 }, 520 { 521 ID_AIC7892 & ID_9005_GENERIC_MASK, 522 ID_9005_GENERIC_MASK, 523 "Adaptec aic7892 Ultra160 SCSI adapter", 524 ahc_aic7892_setup 525 }, 526 { 527 ID_AIC7895 & ID_DEV_VENDOR_MASK, 528 ID_DEV_VENDOR_MASK, 529 "Adaptec aic7895 Ultra SCSI adapter", 530 ahc_aic7895_setup 531 }, 532 { 533 ID_AIC7896 & ID_9005_GENERIC_MASK, 534 ID_9005_GENERIC_MASK, 535 "Adaptec aic7896/97 Ultra2 SCSI adapter", 536 ahc_aic7896_setup 537 }, 538 { 539 ID_AIC7899 & ID_9005_GENERIC_MASK, 540 ID_9005_GENERIC_MASK, 541 "Adaptec aic7899 Ultra160 SCSI adapter", 542 ahc_aic7899_setup 543 }, 544 { 545 ID_AIC7810 & ID_DEV_VENDOR_MASK, 546 ID_DEV_VENDOR_MASK, 547 "Adaptec aic7810 RAID memory controller", 548 ahc_raid_setup 549 }, 550 { 551 ID_AIC7815 & ID_DEV_VENDOR_MASK, 552 ID_DEV_VENDOR_MASK, 553 "Adaptec aic7815 RAID memory controller", 554 ahc_raid_setup 555 } 556}; 557 558static const u_int ahc_num_pci_devs = ARRAY_SIZE(ahc_pci_ident_table); 559 560#define AHC_394X_SLOT_CHANNEL_A 4 561#define AHC_394X_SLOT_CHANNEL_B 5 562 563#define AHC_398X_SLOT_CHANNEL_A 4 564#define AHC_398X_SLOT_CHANNEL_B 8 565#define AHC_398X_SLOT_CHANNEL_C 12 566 567#define AHC_494X_SLOT_CHANNEL_A 4 568#define AHC_494X_SLOT_CHANNEL_B 5 569#define AHC_494X_SLOT_CHANNEL_C 6 570#define AHC_494X_SLOT_CHANNEL_D 7 571 572#define DEVCONFIG 0x40 573#define PCIERRGENDIS 0x80000000ul 574#define SCBSIZE32 0x00010000ul /* aic789X only */ 575#define REXTVALID 0x00001000ul /* ultra cards only */ 576#define MPORTMODE 0x00000400ul /* aic7870+ only */ 577#define RAMPSM 0x00000200ul /* aic7870+ only */ 578#define VOLSENSE 0x00000100ul 579#define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 580#define SCBRAMSEL 0x00000080ul 581#define MRDCEN 0x00000040ul 582#define EXTSCBTIME 0x00000020ul /* aic7870 only */ 583#define EXTSCBPEN 0x00000010ul /* aic7870 only */ 584#define BERREN 0x00000008ul 585#define DACEN 0x00000004ul 586#define STPWLEVEL 0x00000002ul 587#define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 588 589#define CSIZE_LATTIME 0x0c 590#define CACHESIZE 0x0000003ful /* only 5 bits */ 591#define LATTIME 0x0000ff00ul 592 593/* PCI STATUS definitions */ 594#define DPE 0x80 595#define SSE 0x40 596#define RMA 0x20 597#define RTA 0x10 598#define STA 0x08 599#define DPR 0x01 600 601static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 602 uint16_t subvendor, uint16_t subdevice); 603static int ahc_ext_scbram_present(struct ahc_softc *ahc); 604static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 605 int pcheck, int fast, int large); 606static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 607static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 608static void ahc_parse_pci_eeprom(struct ahc_softc *ahc, 609 struct seeprom_config *sc); 610static void configure_termination(struct ahc_softc *ahc, 611 struct seeprom_descriptor *sd, 612 u_int adapter_control, 613 u_int *sxfrctl1); 614 615static void ahc_new_term_detect(struct ahc_softc *ahc, 616 int *enableSEC_low, 617 int *enableSEC_high, 618 int *enablePRI_low, 619 int *enablePRI_high, 620 int *eeprom_present); 621static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 622 int *internal68_present, 623 int *externalcable_present, 624 int *eeprom_present); 625static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 626 int *externalcable_present, 627 int *eeprom_present); 628static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 629static uint8_t read_brdctl(struct ahc_softc *ahc); 630static void ahc_pci_intr(struct ahc_softc *ahc); 631static int ahc_pci_chip_init(struct ahc_softc *ahc); 632static int ahc_pci_suspend(struct ahc_softc *ahc); 633static int ahc_pci_resume(struct ahc_softc *ahc); 634 635static int 636ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 637 uint16_t subdevice, uint16_t subvendor) 638{ 639 int result; 640 641 /* Default to invalid. */ 642 result = 0; 643 if (vendor == 0x9005 644 && subvendor == 0x9005 645 && subdevice != device 646 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 647 648 switch (SUBID_9005_TYPE(subdevice)) { 649 case SUBID_9005_TYPE_MB: 650 break; 651 case SUBID_9005_TYPE_CARD: 652 case SUBID_9005_TYPE_LCCARD: 653 /* 654 * Currently only trust Adaptec cards to 655 * get the sub device info correct. 656 */ 657 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 658 result = 1; 659 break; 660 case SUBID_9005_TYPE_RAID: 661 break; 662 default: 663 break; 664 } 665 } 666 return (result); 667} 668 669struct ahc_pci_identity * 670ahc_find_pci_device(ahc_dev_softc_t pci) 671{ 672 uint64_t full_id; 673 uint16_t device; 674 uint16_t vendor; 675 uint16_t subdevice; 676 uint16_t subvendor; 677 struct ahc_pci_identity *entry; 678 u_int i; 679 680 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 681 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 682 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 683 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 684 full_id = ahc_compose_id(device, vendor, subdevice, subvendor); 685 686 /* 687 * If the second function is not hooked up, ignore it. 688 * Unfortunately, not all MB vendors implement the 689 * subdevice ID as per the Adaptec spec, so do our best 690 * to sanity check it prior to accepting the subdevice 691 * ID as valid. 692 */ 693 if (ahc_get_pci_function(pci) > 0 694 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice) 695 && SUBID_9005_MFUNCENB(subdevice) == 0) 696 return (NULL); 697 698 for (i = 0; i < ahc_num_pci_devs; i++) { 699 entry = &ahc_pci_ident_table[i]; 700 if (entry->full_id == (full_id & entry->id_mask)) { 701 /* Honor exclusion entries. */ 702 if (entry->name == NULL) 703 return (NULL); 704 return (entry); 705 } 706 } 707 return (NULL); 708} 709 710int 711ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 712{ 713 u_int command; 714 u_int our_id; 715 u_int sxfrctl1; 716 u_int scsiseq; 717 u_int dscommand0; 718 uint32_t devconfig; 719 int error; 720 uint8_t sblkctl; 721 722 our_id = 0; 723 error = entry->setup(ahc); 724 if (error != 0) 725 return (error); 726 ahc->chip |= AHC_PCI; 727 ahc->description = entry->name; 728 729 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0); 730 731 error = ahc_pci_map_registers(ahc); 732 if (error != 0) 733 return (error); 734 735 /* 736 * Before we continue probing the card, ensure that 737 * its interrupts are *disabled*. We don't want 738 * a misstep to hang the machine in an interrupt 739 * storm. 740 */ 741 ahc_intr_enable(ahc, FALSE); 742 743 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 744 745 /* 746 * If we need to support high memory, enable dual 747 * address cycles. This bit must be set to enable 748 * high address bit generation even if we are on a 749 * 64bit bus (PCI64BIT set in devconfig). 750 */ 751 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 752 753 if (bootverbose) 754 printf("%s: Enabling 39Bit Addressing\n", 755 ahc_name(ahc)); 756 devconfig |= DACEN; 757 } 758 759 /* Ensure that pci error generation, a test feature, is disabled. */ 760 devconfig |= PCIERRGENDIS; 761 762 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 763 764 /* Ensure busmastering is enabled */ 765 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 766 command |= PCIM_CMD_BUSMASTEREN; 767 768 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 769 770 /* On all PCI adapters, we allow SCB paging */ 771 ahc->flags |= AHC_PAGESCBS; 772 773 error = ahc_softc_init(ahc); 774 if (error != 0) 775 return (error); 776 777 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 778 ahc->seqctl |= FAILDIS; 779 780 ahc->bus_intr = ahc_pci_intr; 781 ahc->bus_chip_init = ahc_pci_chip_init; 782 ahc->bus_suspend = ahc_pci_suspend; 783 ahc->bus_resume = ahc_pci_resume; 784 785 /* Remeber how the card was setup in case there is no SEEPROM */ 786 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 787 ahc_pause(ahc); 788 if ((ahc->features & AHC_ULTRA2) != 0) 789 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 790 else 791 our_id = ahc_inb(ahc, SCSIID) & OID; 792 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 793 scsiseq = ahc_inb(ahc, SCSISEQ); 794 } else { 795 sxfrctl1 = STPWEN; 796 our_id = 7; 797 scsiseq = 0; 798 } 799 800 error = ahc_reset(ahc, /*reinit*/FALSE); 801 if (error != 0) 802 return (ENXIO); 803 804 if ((ahc->features & AHC_DT) != 0) { 805 u_int sfunct; 806 807 /* Perform ALT-Mode Setup */ 808 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 809 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 810 ahc_outb(ahc, OPTIONMODE, 811 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 812 ahc_outb(ahc, SFUNCT, sfunct); 813 814 /* Normal mode setup */ 815 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 816 |TARGCRCENDEN); 817 } 818 819 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 820 dscommand0 |= MPARCKEN|CACHETHEN; 821 if ((ahc->features & AHC_ULTRA2) != 0) { 822 823 /* 824 * DPARCKEN doesn't work correctly on 825 * some MBs so don't use it. 826 */ 827 dscommand0 &= ~DPARCKEN; 828 } 829 830 /* 831 * Handle chips that must have cache line 832 * streaming (dis/en)abled. 833 */ 834 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 835 dscommand0 |= CACHETHEN; 836 837 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 838 dscommand0 &= ~CACHETHEN; 839 840 ahc_outb(ahc, DSCOMMAND0, dscommand0); 841 842 ahc->pci_cachesize = 843 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 844 /*bytes*/1) & CACHESIZE; 845 ahc->pci_cachesize *= 4; 846 847 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 848 && ahc->pci_cachesize == 4) { 849 850 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 851 0, /*bytes*/1); 852 ahc->pci_cachesize = 0; 853 } 854 855 /* 856 * We cannot perform ULTRA speeds without the presense 857 * of the external precision resistor. 858 */ 859 if ((ahc->features & AHC_ULTRA) != 0) { 860 uint32_t devconfig; 861 862 devconfig = ahc_pci_read_config(ahc->dev_softc, 863 DEVCONFIG, /*bytes*/4); 864 if ((devconfig & REXTVALID) == 0) 865 ahc->features &= ~AHC_ULTRA; 866 } 867 868 /* See if we have a SEEPROM and perform auto-term */ 869 check_extport(ahc, &sxfrctl1); 870 871 /* 872 * Take the LED out of diagnostic mode 873 */ 874 sblkctl = ahc_inb(ahc, SBLKCTL); 875 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 876 877 if ((ahc->features & AHC_ULTRA2) != 0) { 878 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 879 } else { 880 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 881 } 882 883 if (ahc->flags & AHC_USEDEFAULTS) { 884 /* 885 * PCI Adapter default setup 886 * Should only be used if the adapter does not have 887 * a SEEPROM. 888 */ 889 /* See if someone else set us up already */ 890 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 891 && scsiseq != 0) { 892 printf("%s: Using left over BIOS settings\n", 893 ahc_name(ahc)); 894 ahc->flags &= ~AHC_USEDEFAULTS; 895 ahc->flags |= AHC_BIOS_ENABLED; 896 } else { 897 /* 898 * Assume only one connector and always turn 899 * on termination. 900 */ 901 our_id = 0x07; 902 sxfrctl1 = STPWEN; 903 } 904 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 905 906 ahc->our_id = our_id; 907 } 908 909 /* 910 * Take a look to see if we have external SRAM. 911 * We currently do not attempt to use SRAM that is 912 * shared among multiple controllers. 913 */ 914 ahc_probe_ext_scbram(ahc); 915 916 /* 917 * Record our termination setting for the 918 * generic initialization routine. 919 */ 920 if ((sxfrctl1 & STPWEN) != 0) 921 ahc->flags |= AHC_TERM_ENB_A; 922 923 /* 924 * Save chip register configuration data for chip resets 925 * that occur during runtime and resume events. 926 */ 927 ahc->bus_softc.pci_softc.devconfig = 928 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 929 ahc->bus_softc.pci_softc.command = 930 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 931 ahc->bus_softc.pci_softc.csize_lattime = 932 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1); 933 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 934 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 935 if ((ahc->features & AHC_DT) != 0) { 936 u_int sfunct; 937 938 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 939 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 940 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE); 941 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT); 942 ahc_outb(ahc, SFUNCT, sfunct); 943 ahc->bus_softc.pci_softc.crccontrol1 = 944 ahc_inb(ahc, CRCCONTROL1); 945 } 946 if ((ahc->features & AHC_MULTI_FUNC) != 0) 947 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR); 948 949 if ((ahc->features & AHC_ULTRA2) != 0) 950 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 951 952 /* Core initialization */ 953 error = ahc_init(ahc); 954 if (error != 0) 955 return (error); 956 957 /* 958 * Allow interrupts now that we are completely setup. 959 */ 960 error = ahc_pci_map_int(ahc); 961 if (error != 0) 962 return (error); 963 964 ahc->init_level++; 965 return (0); 966} 967 968/* 969 * Test for the presense of external sram in an 970 * "unshared" configuration. 971 */ 972static int 973ahc_ext_scbram_present(struct ahc_softc *ahc) 974{ 975 u_int chip; 976 int ramps; 977 int single_user; 978 uint32_t devconfig; 979 980 chip = ahc->chip & AHC_CHIPID_MASK; 981 devconfig = ahc_pci_read_config(ahc->dev_softc, 982 DEVCONFIG, /*bytes*/4); 983 single_user = (devconfig & MPORTMODE) != 0; 984 985 if ((ahc->features & AHC_ULTRA2) != 0) 986 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 987 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 988 /* 989 * External SCBRAM arbitration is flakey 990 * on these chips. Unfortunately this means 991 * we don't use the extra SCB ram space on the 992 * 3940AUW. 993 */ 994 ramps = 0; 995 else if (chip >= AHC_AIC7870) 996 ramps = (devconfig & RAMPSM) != 0; 997 else 998 ramps = 0; 999 1000 if (ramps && single_user) 1001 return (1); 1002 return (0); 1003} 1004 1005/* 1006 * Enable external scbram. 1007 */ 1008static void 1009ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1010 int fast, int large) 1011{ 1012 uint32_t devconfig; 1013 1014 if (ahc->features & AHC_MULTI_FUNC) { 1015 /* 1016 * Set the SCB Base addr (highest address bit) 1017 * depending on which channel we are. 1018 */ 1019 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 1020 } 1021 1022 ahc->flags &= ~AHC_LSCBS_ENABLED; 1023 if (large) 1024 ahc->flags |= AHC_LSCBS_ENABLED; 1025 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1026 if ((ahc->features & AHC_ULTRA2) != 0) { 1027 u_int dscommand0; 1028 1029 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1030 if (enable) 1031 dscommand0 &= ~INTSCBRAMSEL; 1032 else 1033 dscommand0 |= INTSCBRAMSEL; 1034 if (large) 1035 dscommand0 &= ~USCBSIZE32; 1036 else 1037 dscommand0 |= USCBSIZE32; 1038 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1039 } else { 1040 if (fast) 1041 devconfig &= ~EXTSCBTIME; 1042 else 1043 devconfig |= EXTSCBTIME; 1044 if (enable) 1045 devconfig &= ~SCBRAMSEL; 1046 else 1047 devconfig |= SCBRAMSEL; 1048 if (large) 1049 devconfig &= ~SCBSIZE32; 1050 else 1051 devconfig |= SCBSIZE32; 1052 } 1053 if (pcheck) 1054 devconfig |= EXTSCBPEN; 1055 else 1056 devconfig &= ~EXTSCBPEN; 1057 1058 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 1059} 1060 1061/* 1062 * Take a look to see if we have external SRAM. 1063 * We currently do not attempt to use SRAM that is 1064 * shared among multiple controllers. 1065 */ 1066static void 1067ahc_probe_ext_scbram(struct ahc_softc *ahc) 1068{ 1069 int num_scbs; 1070 int test_num_scbs; 1071 int enable; 1072 int pcheck; 1073 int fast; 1074 int large; 1075 1076 enable = FALSE; 1077 pcheck = FALSE; 1078 fast = FALSE; 1079 large = FALSE; 1080 num_scbs = 0; 1081 1082 if (ahc_ext_scbram_present(ahc) == 0) 1083 goto done; 1084 1085 /* 1086 * Probe for the best parameters to use. 1087 */ 1088 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1089 num_scbs = ahc_probe_scbs(ahc); 1090 if (num_scbs == 0) { 1091 /* The SRAM wasn't really present. */ 1092 goto done; 1093 } 1094 enable = TRUE; 1095 1096 /* 1097 * Clear any outstanding parity error 1098 * and ensure that parity error reporting 1099 * is enabled. 1100 */ 1101 ahc_outb(ahc, SEQCTL, 0); 1102 ahc_outb(ahc, CLRINT, CLRPARERR); 1103 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1104 1105 /* Now see if we can do parity */ 1106 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1107 num_scbs = ahc_probe_scbs(ahc); 1108 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1109 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1110 pcheck = TRUE; 1111 1112 /* Clear any resulting parity error */ 1113 ahc_outb(ahc, CLRINT, CLRPARERR); 1114 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1115 1116 /* Now see if we can do fast timing */ 1117 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1118 test_num_scbs = ahc_probe_scbs(ahc); 1119 if (test_num_scbs == num_scbs 1120 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1121 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1122 fast = TRUE; 1123 1124 /* 1125 * See if we can use large SCBs and still maintain 1126 * the same overall count of SCBs. 1127 */ 1128 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1129 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1130 test_num_scbs = ahc_probe_scbs(ahc); 1131 if (test_num_scbs >= num_scbs) { 1132 large = TRUE; 1133 num_scbs = test_num_scbs; 1134 if (num_scbs >= 64) { 1135 /* 1136 * We have enough space to move the 1137 * "busy targets table" into SCB space 1138 * and make it qualify all the way to the 1139 * lun level. 1140 */ 1141 ahc->flags |= AHC_SCB_BTT; 1142 } 1143 } 1144 } 1145done: 1146 /* 1147 * Disable parity error reporting until we 1148 * can load instruction ram. 1149 */ 1150 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1151 /* Clear any latched parity error */ 1152 ahc_outb(ahc, CLRINT, CLRPARERR); 1153 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1154 if (bootverbose && enable) { 1155 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1156 ahc_name(ahc), fast ? "fast" : "slow", 1157 pcheck ? ", parity checking enabled" : "", 1158 large ? 64 : 32); 1159 } 1160 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1161} 1162 1163/* 1164 * Perform some simple tests that should catch situations where 1165 * our registers are invalidly mapped. 1166 */ 1167int 1168ahc_pci_test_register_access(struct ahc_softc *ahc) 1169{ 1170 int error; 1171 u_int status1; 1172 uint32_t cmd; 1173 uint8_t hcntrl; 1174 1175 error = EIO; 1176 1177 /* 1178 * Enable PCI error interrupt status, but suppress NMIs 1179 * generated by SERR raised due to target aborts. 1180 */ 1181 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 1182 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 1183 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 1184 1185 /* 1186 * First a simple test to see if any 1187 * registers can be read. Reading 1188 * HCNTRL has no side effects and has 1189 * at least one bit that is guaranteed to 1190 * be zero so it is a good register to 1191 * use for this test. 1192 */ 1193 hcntrl = ahc_inb(ahc, HCNTRL); 1194 1195 if (hcntrl == 0xFF) 1196 goto fail; 1197 1198 if ((hcntrl & CHIPRST) != 0) { 1199 /* 1200 * The chip has not been initialized since 1201 * PCI/EISA/VLB bus reset. Don't trust 1202 * "left over BIOS data". 1203 */ 1204 ahc->flags |= AHC_NO_BIOS_INIT; 1205 } 1206 1207 /* 1208 * Next create a situation where write combining 1209 * or read prefetching could be initiated by the 1210 * CPU or host bridge. Our device does not support 1211 * either, so look for data corruption and/or flagged 1212 * PCI errors. First pause without causing another 1213 * chip reset. 1214 */ 1215 hcntrl &= ~CHIPRST; 1216 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1217 while (ahc_is_paused(ahc) == 0) 1218 ; 1219 1220 /* Clear any PCI errors that occurred before our driver attached. */ 1221 status1 = ahc_pci_read_config(ahc->dev_softc, 1222 PCIR_STATUS + 1, /*bytes*/1); 1223 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1224 status1, /*bytes*/1); 1225 ahc_outb(ahc, CLRINT, CLRPARERR); 1226 1227 ahc_outb(ahc, SEQCTL, PERRORDIS); 1228 ahc_outb(ahc, SCBPTR, 0); 1229 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1230 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1231 goto fail; 1232 1233 status1 = ahc_pci_read_config(ahc->dev_softc, 1234 PCIR_STATUS + 1, /*bytes*/1); 1235 if ((status1 & STA) != 0) 1236 goto fail; 1237 1238 error = 0; 1239 1240fail: 1241 /* Silently clear any latched errors. */ 1242 status1 = ahc_pci_read_config(ahc->dev_softc, 1243 PCIR_STATUS + 1, /*bytes*/1); 1244 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1245 status1, /*bytes*/1); 1246 ahc_outb(ahc, CLRINT, CLRPARERR); 1247 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1248 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1249 return (error); 1250} 1251 1252/* 1253 * Check the external port logic for a serial eeprom 1254 * and termination/cable detection contrls. 1255 */ 1256static void 1257check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1258{ 1259 struct seeprom_descriptor sd; 1260 struct seeprom_config *sc; 1261 int have_seeprom; 1262 int have_autoterm; 1263 1264 sd.sd_ahc = ahc; 1265 sd.sd_control_offset = SEECTL; 1266 sd.sd_status_offset = SEECTL; 1267 sd.sd_dataout_offset = SEECTL; 1268 sc = ahc->seep_config; 1269 1270 /* 1271 * For some multi-channel devices, the c46 is simply too 1272 * small to work. For the other controller types, we can 1273 * get our information from either SEEPROM type. Set the 1274 * type to start our probe with accordingly. 1275 */ 1276 if (ahc->flags & AHC_LARGE_SEEPROM) 1277 sd.sd_chip = C56_66; 1278 else 1279 sd.sd_chip = C46; 1280 1281 sd.sd_MS = SEEMS; 1282 sd.sd_RDY = SEERDY; 1283 sd.sd_CS = SEECS; 1284 sd.sd_CK = SEECK; 1285 sd.sd_DO = SEEDO; 1286 sd.sd_DI = SEEDI; 1287 1288 have_seeprom = ahc_acquire_seeprom(ahc, &sd); 1289 if (have_seeprom) { 1290 1291 if (bootverbose) 1292 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1293 1294 for (;;) { 1295 u_int start_addr; 1296 1297 start_addr = 32 * (ahc->channel - 'A'); 1298 1299 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc, 1300 start_addr, 1301 sizeof(*sc)/2); 1302 1303 if (have_seeprom) 1304 have_seeprom = ahc_verify_cksum(sc); 1305 1306 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1307 if (bootverbose) { 1308 if (have_seeprom == 0) 1309 printf ("checksum error\n"); 1310 else 1311 printf ("done.\n"); 1312 } 1313 break; 1314 } 1315 sd.sd_chip = C56_66; 1316 } 1317 ahc_release_seeprom(&sd); 1318 1319 /* Remember the SEEPROM type for later */ 1320 if (sd.sd_chip == C56_66) 1321 ahc->flags |= AHC_LARGE_SEEPROM; 1322 } 1323 1324 if (!have_seeprom) { 1325 /* 1326 * Pull scratch ram settings and treat them as 1327 * if they are the contents of an seeprom if 1328 * the 'ADPT' signature is found in SCB2. 1329 * We manually compose the data as 16bit values 1330 * to avoid endian issues. 1331 */ 1332 ahc_outb(ahc, SCBPTR, 2); 1333 if (ahc_inb(ahc, SCB_BASE) == 'A' 1334 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1335 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1336 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1337 uint16_t *sc_data; 1338 int i; 1339 1340 sc_data = (uint16_t *)sc; 1341 for (i = 0; i < 32; i++, sc_data++) { 1342 int j; 1343 1344 j = i * 2; 1345 *sc_data = ahc_inb(ahc, SRAM_BASE + j) 1346 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1347 } 1348 have_seeprom = ahc_verify_cksum(sc); 1349 if (have_seeprom) 1350 ahc->flags |= AHC_SCB_CONFIG_USED; 1351 } 1352 /* 1353 * Clear any SCB parity errors in case this data and 1354 * its associated parity was not initialized by the BIOS 1355 */ 1356 ahc_outb(ahc, CLRINT, CLRPARERR); 1357 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1358 } 1359 1360 if (!have_seeprom) { 1361 if (bootverbose) 1362 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1363 ahc->flags |= AHC_USEDEFAULTS; 1364 free(ahc->seep_config, M_DEVBUF); 1365 ahc->seep_config = NULL; 1366 sc = NULL; 1367 } else { 1368 ahc_parse_pci_eeprom(ahc, sc); 1369 } 1370 1371 /* 1372 * Cards that have the external logic necessary to talk to 1373 * a SEEPROM, are almost certain to have the remaining logic 1374 * necessary for auto-termination control. This assumption 1375 * hasn't failed yet... 1376 */ 1377 have_autoterm = have_seeprom; 1378 1379 /* 1380 * Some low-cost chips have SEEPROM and auto-term control built 1381 * in, instead of using a GAL. They can tell us directly 1382 * if the termination logic is enabled. 1383 */ 1384 if ((ahc->features & AHC_SPIOCAP) != 0) { 1385 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0) 1386 have_autoterm = FALSE; 1387 } 1388 1389 if (have_autoterm) { 1390 ahc->flags |= AHC_HAS_TERM_LOGIC; 1391 ahc_acquire_seeprom(ahc, &sd); 1392 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1); 1393 ahc_release_seeprom(&sd); 1394 } else if (have_seeprom) { 1395 *sxfrctl1 &= ~STPWEN; 1396 if ((sc->adapter_control & CFSTERM) != 0) 1397 *sxfrctl1 |= STPWEN; 1398 if (bootverbose) 1399 printf("%s: Low byte termination %sabled\n", 1400 ahc_name(ahc), 1401 (*sxfrctl1 & STPWEN) ? "en" : "dis"); 1402 } 1403} 1404 1405static void 1406ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc) 1407{ 1408 /* 1409 * Put the data we've collected down into SRAM 1410 * where ahc_init will find it. 1411 */ 1412 int i; 1413 int max_targ = sc->max_targets & CFMAXTARG; 1414 u_int scsi_conf; 1415 uint16_t discenable; 1416 uint16_t ultraenb; 1417 1418 discenable = 0; 1419 ultraenb = 0; 1420 if ((sc->adapter_control & CFULTRAEN) != 0) { 1421 /* 1422 * Determine if this adapter has a "newstyle" 1423 * SEEPROM format. 1424 */ 1425 for (i = 0; i < max_targ; i++) { 1426 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) { 1427 ahc->flags |= AHC_NEWEEPROM_FMT; 1428 break; 1429 } 1430 } 1431 } 1432 1433 for (i = 0; i < max_targ; i++) { 1434 u_int scsirate; 1435 uint16_t target_mask; 1436 1437 target_mask = 0x01 << i; 1438 if (sc->device_flags[i] & CFDISC) 1439 discenable |= target_mask; 1440 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1441 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) 1442 ultraenb |= target_mask; 1443 } else if ((sc->adapter_control & CFULTRAEN) != 0) { 1444 ultraenb |= target_mask; 1445 } 1446 if ((sc->device_flags[i] & CFXFER) == 0x04 1447 && (ultraenb & target_mask) != 0) { 1448 /* Treat 10MHz as a non-ultra speed */ 1449 sc->device_flags[i] &= ~CFXFER; 1450 ultraenb &= ~target_mask; 1451 } 1452 if ((ahc->features & AHC_ULTRA2) != 0) { 1453 u_int offset; 1454 1455 if (sc->device_flags[i] & CFSYNCH) 1456 offset = MAX_OFFSET_ULTRA2; 1457 else 1458 offset = 0; 1459 ahc_outb(ahc, TARG_OFFSET + i, offset); 1460 1461 /* 1462 * The ultra enable bits contain the 1463 * high bit of the ultra2 sync rate 1464 * field. 1465 */ 1466 scsirate = (sc->device_flags[i] & CFXFER) 1467 | ((ultraenb & target_mask) ? 0x8 : 0x0); 1468 if (sc->device_flags[i] & CFWIDEB) 1469 scsirate |= WIDEXFER; 1470 } else { 1471 scsirate = (sc->device_flags[i] & CFXFER) << 4; 1472 if (sc->device_flags[i] & CFSYNCH) 1473 scsirate |= SOFS; 1474 if (sc->device_flags[i] & CFWIDEB) 1475 scsirate |= WIDEXFER; 1476 } 1477 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1478 } 1479 ahc->our_id = sc->brtime_id & CFSCSIID; 1480 1481 scsi_conf = (ahc->our_id & 0x7); 1482 if (sc->adapter_control & CFSPARITY) 1483 scsi_conf |= ENSPCHK; 1484 if (sc->adapter_control & CFRESETB) 1485 scsi_conf |= RESET_SCSI; 1486 1487 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1488 1489 if (sc->bios_control & CFEXTEND) 1490 ahc->flags |= AHC_EXTENDED_TRANS_A; 1491 1492 if (sc->bios_control & CFBIOSEN) 1493 ahc->flags |= AHC_BIOS_ENABLED; 1494 if (ahc->features & AHC_ULTRA 1495 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1496 /* Should we enable Ultra mode? */ 1497 if (!(sc->adapter_control & CFULTRAEN)) 1498 /* Treat us as a non-ultra card */ 1499 ultraenb = 0; 1500 } 1501 1502 if (sc->signature == CFSIGNATURE 1503 || sc->signature == CFSIGNATURE2) { 1504 uint32_t devconfig; 1505 1506 /* Honor the STPWLEVEL settings */ 1507 devconfig = ahc_pci_read_config(ahc->dev_softc, 1508 DEVCONFIG, /*bytes*/4); 1509 devconfig &= ~STPWLEVEL; 1510 if ((sc->bios_control & CFSTPWLEVEL) != 0) 1511 devconfig |= STPWLEVEL; 1512 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1513 devconfig, /*bytes*/4); 1514 } 1515 /* Set SCSICONF info */ 1516 ahc_outb(ahc, SCSICONF, scsi_conf); 1517 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1518 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1519 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1520 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1521} 1522 1523static void 1524configure_termination(struct ahc_softc *ahc, 1525 struct seeprom_descriptor *sd, 1526 u_int adapter_control, 1527 u_int *sxfrctl1) 1528{ 1529 uint8_t brddat; 1530 1531 brddat = 0; 1532 1533 /* 1534 * Update the settings in sxfrctl1 to match the 1535 * termination settings 1536 */ 1537 *sxfrctl1 = 0; 1538 1539 /* 1540 * SEECS must be on for the GALS to latch 1541 * the data properly. Be sure to leave MS 1542 * on or we will release the seeprom. 1543 */ 1544 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1545 if ((adapter_control & CFAUTOTERM) != 0 1546 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1547 int internal50_present; 1548 int internal68_present; 1549 int externalcable_present; 1550 int eeprom_present; 1551 int enableSEC_low; 1552 int enableSEC_high; 1553 int enablePRI_low; 1554 int enablePRI_high; 1555 int sum; 1556 1557 enableSEC_low = 0; 1558 enableSEC_high = 0; 1559 enablePRI_low = 0; 1560 enablePRI_high = 0; 1561 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1562 ahc_new_term_detect(ahc, &enableSEC_low, 1563 &enableSEC_high, 1564 &enablePRI_low, 1565 &enablePRI_high, 1566 &eeprom_present); 1567 if ((adapter_control & CFSEAUTOTERM) == 0) { 1568 if (bootverbose) 1569 printf("%s: Manual SE Termination\n", 1570 ahc_name(ahc)); 1571 enableSEC_low = (adapter_control & CFSELOWTERM); 1572 enableSEC_high = 1573 (adapter_control & CFSEHIGHTERM); 1574 } 1575 if ((adapter_control & CFAUTOTERM) == 0) { 1576 if (bootverbose) 1577 printf("%s: Manual LVD Termination\n", 1578 ahc_name(ahc)); 1579 enablePRI_low = (adapter_control & CFSTERM); 1580 enablePRI_high = (adapter_control & CFWSTERM); 1581 } 1582 /* Make the table calculations below happy */ 1583 internal50_present = 0; 1584 internal68_present = 1; 1585 externalcable_present = 1; 1586 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1587 aic785X_cable_detect(ahc, &internal50_present, 1588 &externalcable_present, 1589 &eeprom_present); 1590 /* Can never support a wide connector. */ 1591 internal68_present = 0; 1592 } else { 1593 aic787X_cable_detect(ahc, &internal50_present, 1594 &internal68_present, 1595 &externalcable_present, 1596 &eeprom_present); 1597 } 1598 1599 if ((ahc->features & AHC_WIDE) == 0) 1600 internal68_present = 0; 1601 1602 if (bootverbose 1603 && (ahc->features & AHC_ULTRA2) == 0) { 1604 printf("%s: internal 50 cable %s present", 1605 ahc_name(ahc), 1606 internal50_present ? "is":"not"); 1607 1608 if ((ahc->features & AHC_WIDE) != 0) 1609 printf(", internal 68 cable %s present", 1610 internal68_present ? "is":"not"); 1611 printf("\n%s: external cable %s present\n", 1612 ahc_name(ahc), 1613 externalcable_present ? "is":"not"); 1614 } 1615 if (bootverbose) 1616 printf("%s: BIOS eeprom %s present\n", 1617 ahc_name(ahc), eeprom_present ? "is" : "not"); 1618 1619 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1620 /* 1621 * The 50 pin connector is a separate bus, 1622 * so force it to always be terminated. 1623 * In the future, perform current sensing 1624 * to determine if we are in the middle of 1625 * a properly terminated bus. 1626 */ 1627 internal50_present = 0; 1628 } 1629 1630 /* 1631 * Now set the termination based on what 1632 * we found. 1633 * Flash Enable = BRDDAT7 1634 * Secondary High Term Enable = BRDDAT6 1635 * Secondary Low Term Enable = BRDDAT5 (7890) 1636 * Primary High Term Enable = BRDDAT4 (7890) 1637 */ 1638 if ((ahc->features & AHC_ULTRA2) == 0 1639 && (internal50_present != 0) 1640 && (internal68_present != 0) 1641 && (externalcable_present != 0)) { 1642 printf("%s: Illegal cable configuration!!. " 1643 "Only two connectors on the " 1644 "adapter may be used at a " 1645 "time!\n", ahc_name(ahc)); 1646 1647 /* 1648 * Pretend there are no cables in the hope 1649 * that having all of the termination on 1650 * gives us a more stable bus. 1651 */ 1652 internal50_present = 0; 1653 internal68_present = 0; 1654 externalcable_present = 0; 1655 } 1656 1657 if ((ahc->features & AHC_WIDE) != 0 1658 && ((externalcable_present == 0) 1659 || (internal68_present == 0) 1660 || (enableSEC_high != 0))) { 1661 brddat |= BRDDAT6; 1662 if (bootverbose) { 1663 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1664 printf("%s: 68 pin termination " 1665 "Enabled\n", ahc_name(ahc)); 1666 else 1667 printf("%s: %sHigh byte termination " 1668 "Enabled\n", ahc_name(ahc), 1669 enableSEC_high ? "Secondary " 1670 : ""); 1671 } 1672 } 1673 1674 sum = internal50_present + internal68_present 1675 + externalcable_present; 1676 if (sum < 2 || (enableSEC_low != 0)) { 1677 if ((ahc->features & AHC_ULTRA2) != 0) 1678 brddat |= BRDDAT5; 1679 else 1680 *sxfrctl1 |= STPWEN; 1681 if (bootverbose) { 1682 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1683 printf("%s: 50 pin termination " 1684 "Enabled\n", ahc_name(ahc)); 1685 else 1686 printf("%s: %sLow byte termination " 1687 "Enabled\n", ahc_name(ahc), 1688 enableSEC_low ? "Secondary " 1689 : ""); 1690 } 1691 } 1692 1693 if (enablePRI_low != 0) { 1694 *sxfrctl1 |= STPWEN; 1695 if (bootverbose) 1696 printf("%s: Primary Low Byte termination " 1697 "Enabled\n", ahc_name(ahc)); 1698 } 1699 1700 /* 1701 * Setup STPWEN before setting up the rest of 1702 * the termination per the tech note on the U160 cards. 1703 */ 1704 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1705 1706 if (enablePRI_high != 0) { 1707 brddat |= BRDDAT4; 1708 if (bootverbose) 1709 printf("%s: Primary High Byte " 1710 "termination Enabled\n", 1711 ahc_name(ahc)); 1712 } 1713 1714 write_brdctl(ahc, brddat); 1715 1716 } else { 1717 if ((adapter_control & CFSTERM) != 0) { 1718 *sxfrctl1 |= STPWEN; 1719 1720 if (bootverbose) 1721 printf("%s: %sLow byte termination Enabled\n", 1722 ahc_name(ahc), 1723 (ahc->features & AHC_ULTRA2) ? "Primary " 1724 : ""); 1725 } 1726 1727 if ((adapter_control & CFWSTERM) != 0 1728 && (ahc->features & AHC_WIDE) != 0) { 1729 brddat |= BRDDAT6; 1730 if (bootverbose) 1731 printf("%s: %sHigh byte termination Enabled\n", 1732 ahc_name(ahc), 1733 (ahc->features & AHC_ULTRA2) 1734 ? "Secondary " : ""); 1735 } 1736 1737 /* 1738 * Setup STPWEN before setting up the rest of 1739 * the termination per the tech note on the U160 cards. 1740 */ 1741 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1742 1743 if ((ahc->features & AHC_WIDE) != 0) 1744 write_brdctl(ahc, brddat); 1745 } 1746 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1747} 1748 1749static void 1750ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1751 int *enableSEC_high, int *enablePRI_low, 1752 int *enablePRI_high, int *eeprom_present) 1753{ 1754 uint8_t brdctl; 1755 1756 /* 1757 * BRDDAT7 = Eeprom 1758 * BRDDAT6 = Enable Secondary High Byte termination 1759 * BRDDAT5 = Enable Secondary Low Byte termination 1760 * BRDDAT4 = Enable Primary high byte termination 1761 * BRDDAT3 = Enable Primary low byte termination 1762 */ 1763 brdctl = read_brdctl(ahc); 1764 *eeprom_present = brdctl & BRDDAT7; 1765 *enableSEC_high = (brdctl & BRDDAT6); 1766 *enableSEC_low = (brdctl & BRDDAT5); 1767 *enablePRI_high = (brdctl & BRDDAT4); 1768 *enablePRI_low = (brdctl & BRDDAT3); 1769} 1770 1771static void 1772aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1773 int *internal68_present, int *externalcable_present, 1774 int *eeprom_present) 1775{ 1776 uint8_t brdctl; 1777 1778 /* 1779 * First read the status of our cables. 1780 * Set the rom bank to 0 since the 1781 * bank setting serves as a multiplexor 1782 * for the cable detection logic. 1783 * BRDDAT5 controls the bank switch. 1784 */ 1785 write_brdctl(ahc, 0); 1786 1787 /* 1788 * Now read the state of the internal 1789 * connectors. BRDDAT6 is INT50 and 1790 * BRDDAT7 is INT68. 1791 */ 1792 brdctl = read_brdctl(ahc); 1793 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1794 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1795 1796 /* 1797 * Set the rom bank to 1 and determine 1798 * the other signals. 1799 */ 1800 write_brdctl(ahc, BRDDAT5); 1801 1802 /* 1803 * Now read the state of the external 1804 * connectors. BRDDAT6 is EXT68 and 1805 * BRDDAT7 is EPROMPS. 1806 */ 1807 brdctl = read_brdctl(ahc); 1808 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1809 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1810} 1811 1812static void 1813aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1814 int *externalcable_present, int *eeprom_present) 1815{ 1816 uint8_t brdctl; 1817 uint8_t spiocap; 1818 1819 spiocap = ahc_inb(ahc, SPIOCAP); 1820 spiocap &= ~SOFTCMDEN; 1821 spiocap |= EXT_BRDCTL; 1822 ahc_outb(ahc, SPIOCAP, spiocap); 1823 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1824 ahc_flush_device_writes(ahc); 1825 ahc_delay(500); 1826 ahc_outb(ahc, BRDCTL, 0); 1827 ahc_flush_device_writes(ahc); 1828 ahc_delay(500); 1829 brdctl = ahc_inb(ahc, BRDCTL); 1830 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1831 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1832 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1833} 1834 1835int 1836ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1837{ 1838 int wait; 1839 1840 if ((ahc->features & AHC_SPIOCAP) != 0 1841 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1842 return (0); 1843 1844 /* 1845 * Request access of the memory port. When access is 1846 * granted, SEERDY will go high. We use a 1 second 1847 * timeout which should be near 1 second more than 1848 * is needed. Reason: after the chip reset, there 1849 * should be no contention. 1850 */ 1851 SEEPROM_OUTB(sd, sd->sd_MS); 1852 wait = 1000; /* 1 second timeout in msec */ 1853 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1854 ahc_delay(1000); /* delay 1 msec */ 1855 } 1856 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1857 SEEPROM_OUTB(sd, 0); 1858 return (0); 1859 } 1860 return(1); 1861} 1862 1863void 1864ahc_release_seeprom(struct seeprom_descriptor *sd) 1865{ 1866 /* Release access to the memory port and the serial EEPROM. */ 1867 SEEPROM_OUTB(sd, 0); 1868} 1869 1870static void 1871write_brdctl(struct ahc_softc *ahc, uint8_t value) 1872{ 1873 uint8_t brdctl; 1874 1875 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1876 brdctl = BRDSTB; 1877 if (ahc->channel == 'B') 1878 brdctl |= BRDCS; 1879 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1880 brdctl = 0; 1881 } else { 1882 brdctl = BRDSTB|BRDCS; 1883 } 1884 ahc_outb(ahc, BRDCTL, brdctl); 1885 ahc_flush_device_writes(ahc); 1886 brdctl |= value; 1887 ahc_outb(ahc, BRDCTL, brdctl); 1888 ahc_flush_device_writes(ahc); 1889 if ((ahc->features & AHC_ULTRA2) != 0) 1890 brdctl |= BRDSTB_ULTRA2; 1891 else 1892 brdctl &= ~BRDSTB; 1893 ahc_outb(ahc, BRDCTL, brdctl); 1894 ahc_flush_device_writes(ahc); 1895 if ((ahc->features & AHC_ULTRA2) != 0) 1896 brdctl = 0; 1897 else 1898 brdctl &= ~BRDCS; 1899 ahc_outb(ahc, BRDCTL, brdctl); 1900} 1901 1902static uint8_t 1903read_brdctl(struct ahc_softc *ahc) 1904{ 1905 uint8_t brdctl; 1906 uint8_t value; 1907 1908 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1909 brdctl = BRDRW; 1910 if (ahc->channel == 'B') 1911 brdctl |= BRDCS; 1912 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1913 brdctl = BRDRW_ULTRA2; 1914 } else { 1915 brdctl = BRDRW|BRDCS; 1916 } 1917 ahc_outb(ahc, BRDCTL, brdctl); 1918 ahc_flush_device_writes(ahc); 1919 value = ahc_inb(ahc, BRDCTL); 1920 ahc_outb(ahc, BRDCTL, 0); 1921 return (value); 1922} 1923 1924static void 1925ahc_pci_intr(struct ahc_softc *ahc) 1926{ 1927 u_int error; 1928 u_int status1; 1929 1930 error = ahc_inb(ahc, ERROR); 1931 if ((error & PCIERRSTAT) == 0) 1932 return; 1933 1934 status1 = ahc_pci_read_config(ahc->dev_softc, 1935 PCIR_STATUS + 1, /*bytes*/1); 1936 1937 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1938 ahc_name(ahc), 1939 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1940 1941 if (status1 & DPE) { 1942 ahc->pci_target_perr_count++; 1943 printf("%s: Data Parity Error Detected during address " 1944 "or write data phase\n", ahc_name(ahc)); 1945 } 1946 if (status1 & SSE) { 1947 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1948 } 1949 if (status1 & RMA) { 1950 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1951 } 1952 if (status1 & RTA) { 1953 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1954 } 1955 if (status1 & STA) { 1956 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1957 } 1958 if (status1 & DPR) { 1959 printf("%s: Data Parity Error has been reported via PERR#\n", 1960 ahc_name(ahc)); 1961 } 1962 1963 /* Clear latched errors. */ 1964 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1965 status1, /*bytes*/1); 1966 1967 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1968 printf("%s: Latched PCIERR interrupt with " 1969 "no status bits set\n", ahc_name(ahc)); 1970 } else { 1971 ahc_outb(ahc, CLRINT, CLRPARERR); 1972 } 1973 1974 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) { 1975 printf( 1976"%s: WARNING WARNING WARNING WARNING\n" 1977"%s: Too many PCI parity errors observed as a target.\n" 1978"%s: Some device on this bus is generating bad parity.\n" 1979"%s: This is an error *observed by*, not *generated by*, this controller.\n" 1980"%s: PCI parity error checking has been disabled.\n" 1981"%s: WARNING WARNING WARNING WARNING\n", 1982 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc), 1983 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc)); 1984 ahc->seqctl |= FAILDIS; 1985 ahc_outb(ahc, SEQCTL, ahc->seqctl); 1986 } 1987 ahc_unpause(ahc); 1988} 1989 1990static int 1991ahc_pci_chip_init(struct ahc_softc *ahc) 1992{ 1993 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0); 1994 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus); 1995 if ((ahc->features & AHC_DT) != 0) { 1996 u_int sfunct; 1997 1998 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 1999 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 2000 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode); 2001 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt); 2002 ahc_outb(ahc, SFUNCT, sfunct); 2003 ahc_outb(ahc, CRCCONTROL1, 2004 ahc->bus_softc.pci_softc.crccontrol1); 2005 } 2006 if ((ahc->features & AHC_MULTI_FUNC) != 0) 2007 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr); 2008 2009 if ((ahc->features & AHC_ULTRA2) != 0) 2010 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh); 2011 2012 return (ahc_chip_init(ahc)); 2013} 2014 2015static int 2016ahc_pci_suspend(struct ahc_softc *ahc) 2017{ 2018 return (ahc_suspend(ahc)); 2019} 2020 2021static int 2022ahc_pci_resume(struct ahc_softc *ahc) 2023{ 2024 2025 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0); 2026 2027 /* 2028 * We assume that the OS has restored our register 2029 * mappings, etc. Just update the config space registers 2030 * that the OS doesn't know about and rely on our chip 2031 * reset handler to handle the rest. 2032 */ 2033 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 2034 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4); 2035 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 2036 ahc->bus_softc.pci_softc.command, /*bytes*/1); 2037 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 2038 ahc->bus_softc.pci_softc.csize_lattime, /*bytes*/1); 2039 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) { 2040 struct seeprom_descriptor sd; 2041 u_int sxfrctl1; 2042 2043 sd.sd_ahc = ahc; 2044 sd.sd_control_offset = SEECTL; 2045 sd.sd_status_offset = SEECTL; 2046 sd.sd_dataout_offset = SEECTL; 2047 2048 ahc_acquire_seeprom(ahc, &sd); 2049 configure_termination(ahc, &sd, 2050 ahc->seep_config->adapter_control, 2051 &sxfrctl1); 2052 ahc_release_seeprom(&sd); 2053 } 2054 return (ahc_resume(ahc)); 2055} 2056 2057static int 2058ahc_aic785X_setup(struct ahc_softc *ahc) 2059{ 2060 ahc_dev_softc_t pci; 2061 uint8_t rev; 2062 2063 pci = ahc->dev_softc; 2064 ahc->channel = 'A'; 2065 ahc->chip = AHC_AIC7850; 2066 ahc->features = AHC_AIC7850_FE; 2067 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2068 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2069 if (rev >= 1) 2070 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2071 ahc->instruction_ram_size = 512; 2072 return (0); 2073} 2074 2075static int 2076ahc_aic7860_setup(struct ahc_softc *ahc) 2077{ 2078 ahc_dev_softc_t pci; 2079 uint8_t rev; 2080 2081 pci = ahc->dev_softc; 2082 ahc->channel = 'A'; 2083 ahc->chip = AHC_AIC7860; 2084 ahc->features = AHC_AIC7860_FE; 2085 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2086 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2087 if (rev >= 1) 2088 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2089 ahc->instruction_ram_size = 512; 2090 return (0); 2091} 2092 2093static int 2094ahc_apa1480_setup(struct ahc_softc *ahc) 2095{ 2096 int error; 2097 2098 error = ahc_aic7860_setup(ahc); 2099 if (error != 0) 2100 return (error); 2101 ahc->features |= AHC_REMOVABLE; 2102 return (0); 2103} 2104 2105static int 2106ahc_aic7870_setup(struct ahc_softc *ahc) 2107{ 2108 2109 ahc->channel = 'A'; 2110 ahc->chip = AHC_AIC7870; 2111 ahc->features = AHC_AIC7870_FE; 2112 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2113 ahc->instruction_ram_size = 512; 2114 return (0); 2115} 2116 2117static int 2118ahc_aic7870h_setup(struct ahc_softc *ahc) 2119{ 2120 int error = ahc_aic7870_setup(ahc); 2121 2122 ahc->features |= AHC_HVD; 2123 2124 return error; 2125} 2126 2127static int 2128ahc_aha394X_setup(struct ahc_softc *ahc) 2129{ 2130 int error; 2131 2132 error = ahc_aic7870_setup(ahc); 2133 if (error == 0) 2134 error = ahc_aha394XX_setup(ahc); 2135 return (error); 2136} 2137 2138static int 2139ahc_aha394Xh_setup(struct ahc_softc *ahc) 2140{ 2141 int error = ahc_aha394X_setup(ahc); 2142 2143 ahc->features |= AHC_HVD; 2144 2145 return error; 2146} 2147 2148static int 2149ahc_aha398X_setup(struct ahc_softc *ahc) 2150{ 2151 int error; 2152 2153 error = ahc_aic7870_setup(ahc); 2154 if (error == 0) 2155 error = ahc_aha398XX_setup(ahc); 2156 return (error); 2157} 2158 2159static int 2160ahc_aha494X_setup(struct ahc_softc *ahc) 2161{ 2162 int error; 2163 2164 error = ahc_aic7870_setup(ahc); 2165 if (error == 0) 2166 error = ahc_aha494XX_setup(ahc); 2167 return (error); 2168} 2169 2170static int 2171ahc_aha494Xh_setup(struct ahc_softc *ahc) 2172{ 2173 int error = ahc_aha494X_setup(ahc); 2174 2175 ahc->features |= AHC_HVD; 2176 2177 return error; 2178} 2179 2180static int 2181ahc_aic7880_setup(struct ahc_softc *ahc) 2182{ 2183 ahc_dev_softc_t pci; 2184 uint8_t rev; 2185 2186 pci = ahc->dev_softc; 2187 ahc->channel = 'A'; 2188 ahc->chip = AHC_AIC7880; 2189 ahc->features = AHC_AIC7880_FE; 2190 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 2191 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2192 if (rev >= 1) { 2193 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2194 } else { 2195 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2196 } 2197 ahc->instruction_ram_size = 512; 2198 return (0); 2199} 2200 2201static int 2202ahc_aic7880h_setup(struct ahc_softc *ahc) 2203{ 2204 int error = ahc_aic7880_setup(ahc); 2205 2206 ahc->features |= AHC_HVD; 2207 2208 return error; 2209} 2210 2211 2212static int 2213ahc_aha2940Pro_setup(struct ahc_softc *ahc) 2214{ 2215 2216 ahc->flags |= AHC_INT50_SPEEDFLEX; 2217 return (ahc_aic7880_setup(ahc)); 2218} 2219 2220static int 2221ahc_aha394XU_setup(struct ahc_softc *ahc) 2222{ 2223 int error; 2224 2225 error = ahc_aic7880_setup(ahc); 2226 if (error == 0) 2227 error = ahc_aha394XX_setup(ahc); 2228 return (error); 2229} 2230 2231static int 2232ahc_aha394XUh_setup(struct ahc_softc *ahc) 2233{ 2234 int error = ahc_aha394XU_setup(ahc); 2235 2236 ahc->features |= AHC_HVD; 2237 2238 return error; 2239} 2240 2241static int 2242ahc_aha398XU_setup(struct ahc_softc *ahc) 2243{ 2244 int error; 2245 2246 error = ahc_aic7880_setup(ahc); 2247 if (error == 0) 2248 error = ahc_aha398XX_setup(ahc); 2249 return (error); 2250} 2251 2252static int 2253ahc_aic7890_setup(struct ahc_softc *ahc) 2254{ 2255 ahc_dev_softc_t pci; 2256 uint8_t rev; 2257 2258 pci = ahc->dev_softc; 2259 ahc->channel = 'A'; 2260 ahc->chip = AHC_AIC7890; 2261 ahc->features = AHC_AIC7890_FE; 2262 ahc->flags |= AHC_NEWEEPROM_FMT; 2263 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2264 if (rev == 0) 2265 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 2266 ahc->instruction_ram_size = 768; 2267 return (0); 2268} 2269 2270static int 2271ahc_aic7892_setup(struct ahc_softc *ahc) 2272{ 2273 2274 ahc->channel = 'A'; 2275 ahc->chip = AHC_AIC7892; 2276 ahc->features = AHC_AIC7892_FE; 2277 ahc->flags |= AHC_NEWEEPROM_FMT; 2278 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2279 ahc->instruction_ram_size = 1024; 2280 return (0); 2281} 2282 2283static int 2284ahc_aic7895_setup(struct ahc_softc *ahc) 2285{ 2286 ahc_dev_softc_t pci; 2287 uint8_t rev; 2288 2289 pci = ahc->dev_softc; 2290 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2291 /* 2292 * The 'C' revision of the aic7895 has a few additional features. 2293 */ 2294 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2295 if (rev >= 4) { 2296 ahc->chip = AHC_AIC7895C; 2297 ahc->features = AHC_AIC7895C_FE; 2298 } else { 2299 u_int command; 2300 2301 ahc->chip = AHC_AIC7895; 2302 ahc->features = AHC_AIC7895_FE; 2303 2304 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 2305 command |= PCIM_CMD_MWRICEN; 2306 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 2307 ahc->bugs |= AHC_PCI_MWI_BUG; 2308 } 2309 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 2310 | AHC_CACHETHEN_BUG; 2311 2312 ahc->flags |= AHC_NEWEEPROM_FMT; 2313 ahc->instruction_ram_size = 512; 2314 return (0); 2315} 2316 2317static int 2318ahc_aic7895h_setup(struct ahc_softc *ahc) 2319{ 2320 int error = ahc_aic7895_setup(ahc); 2321 2322 ahc->features |= AHC_HVD; 2323 2324 return error; 2325} 2326 2327static int 2328ahc_aic7896_setup(struct ahc_softc *ahc) 2329{ 2330 ahc_dev_softc_t pci; 2331 2332 pci = ahc->dev_softc; 2333 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2334 ahc->chip = AHC_AIC7896; 2335 ahc->features = AHC_AIC7896_FE; 2336 ahc->flags |= AHC_NEWEEPROM_FMT; 2337 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 2338 ahc->instruction_ram_size = 768; 2339 return (0); 2340} 2341 2342static int 2343ahc_aic7899_setup(struct ahc_softc *ahc) 2344{ 2345 ahc_dev_softc_t pci; 2346 2347 pci = ahc->dev_softc; 2348 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2349 ahc->chip = AHC_AIC7899; 2350 ahc->features = AHC_AIC7899_FE; 2351 ahc->flags |= AHC_NEWEEPROM_FMT; 2352 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2353 ahc->instruction_ram_size = 1024; 2354 return (0); 2355} 2356 2357static int 2358ahc_aha29160C_setup(struct ahc_softc *ahc) 2359{ 2360 int error; 2361 2362 error = ahc_aic7899_setup(ahc); 2363 if (error != 0) 2364 return (error); 2365 ahc->features |= AHC_REMOVABLE; 2366 return (0); 2367} 2368 2369static int 2370ahc_raid_setup(struct ahc_softc *ahc) 2371{ 2372 printf("RAID functionality unsupported\n"); 2373 return (ENXIO); 2374} 2375 2376static int 2377ahc_aha394XX_setup(struct ahc_softc *ahc) 2378{ 2379 ahc_dev_softc_t pci; 2380 2381 pci = ahc->dev_softc; 2382 switch (ahc_get_pci_slot(pci)) { 2383 case AHC_394X_SLOT_CHANNEL_A: 2384 ahc->channel = 'A'; 2385 break; 2386 case AHC_394X_SLOT_CHANNEL_B: 2387 ahc->channel = 'B'; 2388 break; 2389 default: 2390 printf("adapter at unexpected slot %d\n" 2391 "unable to map to a channel\n", 2392 ahc_get_pci_slot(pci)); 2393 ahc->channel = 'A'; 2394 } 2395 return (0); 2396} 2397 2398static int 2399ahc_aha398XX_setup(struct ahc_softc *ahc) 2400{ 2401 ahc_dev_softc_t pci; 2402 2403 pci = ahc->dev_softc; 2404 switch (ahc_get_pci_slot(pci)) { 2405 case AHC_398X_SLOT_CHANNEL_A: 2406 ahc->channel = 'A'; 2407 break; 2408 case AHC_398X_SLOT_CHANNEL_B: 2409 ahc->channel = 'B'; 2410 break; 2411 case AHC_398X_SLOT_CHANNEL_C: 2412 ahc->channel = 'C'; 2413 break; 2414 default: 2415 printf("adapter at unexpected slot %d\n" 2416 "unable to map to a channel\n", 2417 ahc_get_pci_slot(pci)); 2418 ahc->channel = 'A'; 2419 break; 2420 } 2421 ahc->flags |= AHC_LARGE_SEEPROM; 2422 return (0); 2423} 2424 2425static int 2426ahc_aha494XX_setup(struct ahc_softc *ahc) 2427{ 2428 ahc_dev_softc_t pci; 2429 2430 pci = ahc->dev_softc; 2431 switch (ahc_get_pci_slot(pci)) { 2432 case AHC_494X_SLOT_CHANNEL_A: 2433 ahc->channel = 'A'; 2434 break; 2435 case AHC_494X_SLOT_CHANNEL_B: 2436 ahc->channel = 'B'; 2437 break; 2438 case AHC_494X_SLOT_CHANNEL_C: 2439 ahc->channel = 'C'; 2440 break; 2441 case AHC_494X_SLOT_CHANNEL_D: 2442 ahc->channel = 'D'; 2443 break; 2444 default: 2445 printf("adapter at unexpected slot %d\n" 2446 "unable to map to a channel\n", 2447 ahc_get_pci_slot(pci)); 2448 ahc->channel = 'A'; 2449 } 2450 ahc->flags |= AHC_LARGE_SEEPROM; 2451 return (0); 2452} 2453