1/* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 * 13 * The bridge optimization stuff has been removed. If you really 14 * have a silly BIOS which is unable to set your host bridge right, 15 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 16 */ 17 18#include <linux/types.h> 19#include <linux/kernel.h> 20#include <linux/pci.h> 21#include <linux/init.h> 22#include <linux/delay.h> 23#include <linux/acpi.h> 24#include "pci.h" 25 26/* The Mellanox Tavor device gives false positive parity errors 27 * Mark this device with a broken_parity_status, to allow 28 * PCI scanning code to "skip" this now blacklisted device. 29 */ 30static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) 31{ 32 dev->broken_parity_status = 1; /* This device gives false positives */ 33} 34DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); 35DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); 36 37/* Deal with broken BIOS'es that neglect to enable passive release, 38 which can cause problems in combination with the 82441FX/PPro MTRRs */ 39static void quirk_passive_release(struct pci_dev *dev) 40{ 41 struct pci_dev *d = NULL; 42 unsigned char dlc; 43 44 /* We have to make sure a particular bit is set in the PIIX3 45 ISA bridge, so we have to go out and find it. */ 46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 47 pci_read_config_byte(d, 0x82, &dlc); 48 if (!(dlc & 1<<1)) { 49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); 50 dlc |= 1<<1; 51 pci_write_config_byte(d, 0x82, dlc); 52 } 53 } 54} 55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 56DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 57 58int isa_dma_bridge_buggy; 59EXPORT_SYMBOL(isa_dma_bridge_buggy); 60 61static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 62{ 63 if (!isa_dma_bridge_buggy) { 64 isa_dma_bridge_buggy=1; 65 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); 66 } 67} 68 /* 69 * Its not totally clear which chipsets are the problematic ones 70 * We know 82C586 and 82C596 variants are affected. 71 */ 72DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); 73DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); 74DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); 75DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); 76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); 77DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); 78DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); 79 80int pci_pci_problems; 81EXPORT_SYMBOL(pci_pci_problems); 82 83/* 84 * Chipsets where PCI->PCI transfers vanish or hang 85 */ 86static void __devinit quirk_nopcipci(struct pci_dev *dev) 87{ 88 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 89 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); 90 pci_pci_problems |= PCIPCI_FAIL; 91 } 92} 93DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); 94DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); 95 96static void __devinit quirk_nopciamd(struct pci_dev *dev) 97{ 98 u8 rev; 99 pci_read_config_byte(dev, 0x08, &rev); 100 if (rev == 0x13) { 101 /* Erratum 24 */ 102 printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n"); 103 pci_pci_problems |= PCIAGP_FAIL; 104 } 105} 106DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd ); 107 108/* 109 * Triton requires workarounds to be used by the drivers 110 */ 111static void __devinit quirk_triton(struct pci_dev *dev) 112{ 113 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 114 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 115 pci_pci_problems |= PCIPCI_TRITON; 116 } 117} 118DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); 119DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); 120DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); 121DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); 122 123/* 124 * VIA Apollo KT133 needs PCI latency patch 125 * Made according to a windows driver based patch by George E. Breese 126 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 127 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 128 * the info on which Mr Breese based his work. 129 * 130 * Updated based on further information from the site and also on 131 * information provided by VIA 132 */ 133static void quirk_vialatency(struct pci_dev *dev) 134{ 135 struct pci_dev *p; 136 u8 rev; 137 u8 busarb; 138 /* Ok we have a potential problem chipset here. Now see if we have 139 a buggy southbridge */ 140 141 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 142 if (p!=NULL) { 143 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 144 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 145 /* Check for buggy part revisions */ 146 if (rev < 0x40 || rev > 0x42) 147 goto exit; 148 } else { 149 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 150 if (p==NULL) /* No problem parts */ 151 goto exit; 152 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 153 /* Check for buggy part revisions */ 154 if (rev < 0x10 || rev > 0x12) 155 goto exit; 156 } 157 158 /* 159 * Ok we have the problem. Now set the PCI master grant to 160 * occur every master grant. The apparent bug is that under high 161 * PCI load (quite common in Linux of course) you can get data 162 * loss when the CPU is held off the bus for 3 bus master requests 163 * This happens to include the IDE controllers.... 164 * 165 * VIA only apply this fix when an SB Live! is present but under 166 * both Linux and Windows this isnt enough, and we have seen 167 * corruption without SB Live! but with things like 3 UDMA IDE 168 * controllers. So we ignore that bit of the VIA recommendation.. 169 */ 170 171 pci_read_config_byte(dev, 0x76, &busarb); 172 /* Set bit 4 and bi 5 of byte 76 to 0x01 173 "Master priority rotation on every PCI master grant */ 174 busarb &= ~(1<<5); 175 busarb |= (1<<4); 176 pci_write_config_byte(dev, 0x76, busarb); 177 printk(KERN_INFO "Applying VIA southbridge workaround.\n"); 178exit: 179 pci_dev_put(p); 180} 181DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 182DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 183DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 184/* Must restore this on a resume from RAM */ 185DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 186DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 187DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 188 189/* 190 * VIA Apollo VP3 needs ETBF on BT848/878 191 */ 192static void __devinit quirk_viaetbf(struct pci_dev *dev) 193{ 194 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 195 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 196 pci_pci_problems |= PCIPCI_VIAETBF; 197 } 198} 199DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); 200 201static void __devinit quirk_vsfx(struct pci_dev *dev) 202{ 203 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 204 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 205 pci_pci_problems |= PCIPCI_VSFX; 206 } 207} 208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); 209 210static void __init quirk_alimagik(struct pci_dev *dev) 211{ 212 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 213 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 214 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 215 } 216} 217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); 218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); 219 220/* 221 * Natoma has some interesting boundary conditions with Zoran stuff 222 * at least 223 */ 224static void __devinit quirk_natoma(struct pci_dev *dev) 225{ 226 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 227 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 228 pci_pci_problems |= PCIPCI_NATOMA; 229 } 230} 231DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); 232DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); 233DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); 234DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); 235DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); 236DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); 237 238/* 239 * This chip can cause PCI parity errors if config register 0xA0 is read 240 * while DMAs are occurring. 241 */ 242static void __devinit quirk_citrine(struct pci_dev *dev) 243{ 244 dev->cfg_size = 0xA0; 245} 246DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); 247 248/* 249 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 250 * If it's needed, re-allocate the region. 251 */ 252static void __devinit quirk_s3_64M(struct pci_dev *dev) 253{ 254 struct resource *r = &dev->resource[0]; 255 256 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 257 r->start = 0; 258 r->end = 0x3ffffff; 259 } 260} 261DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); 262DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); 263 264static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 265 unsigned size, int nr, const char *name) 266{ 267 region &= ~(size-1); 268 if (region) { 269 struct pci_bus_region bus_region; 270 struct resource *res = dev->resource + nr; 271 272 res->name = pci_name(dev); 273 res->start = region; 274 res->end = region + size - 1; 275 res->flags = IORESOURCE_IO; 276 277 /* Convert from PCI bus to resource space. */ 278 bus_region.start = res->start; 279 bus_region.end = res->end; 280 pcibios_bus_to_resource(dev, res, &bus_region); 281 282 pci_claim_resource(dev, nr); 283 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); 284 } 285} 286 287/* 288 * ATI Northbridge setups MCE the processor if you even 289 * read somewhere between 0x3b0->0x3bb or read 0x3d3 290 */ 291static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 292{ 293 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); 294 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 295 request_region(0x3b0, 0x0C, "RadeonIGP"); 296 request_region(0x3d3, 0x01, "RadeonIGP"); 297} 298DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); 299 300/* 301 * Let's make the southbridge information explicit instead 302 * of having to worry about people probing the ACPI areas, 303 * for example.. (Yes, it happens, and if you read the wrong 304 * ACPI register it will put the machine to sleep with no 305 * way of waking it up again. Bummer). 306 * 307 * ALI M7101: Two IO regions pointed to by words at 308 * 0xE0 (64 bytes of ACPI registers) 309 * 0xE2 (32 bytes of SMB registers) 310 */ 311static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 312{ 313 u16 region; 314 315 pci_read_config_word(dev, 0xE0, ®ion); 316 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 317 pci_read_config_word(dev, 0xE2, ®ion); 318 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 319} 320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); 321 322static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 323{ 324 u32 devres; 325 u32 mask, size, base; 326 327 pci_read_config_dword(dev, port, &devres); 328 if ((devres & enable) != enable) 329 return; 330 mask = (devres >> 16) & 15; 331 base = devres & 0xffff; 332 size = 16; 333 for (;;) { 334 unsigned bit = size >> 1; 335 if ((bit & mask) == bit) 336 break; 337 size = bit; 338 } 339 /* 340 * For now we only print it out. Eventually we'll want to 341 * reserve it (at least if it's in the 0x1000+ range), but 342 * let's get enough confirmation reports first. 343 */ 344 base &= -size; 345 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1); 346} 347 348static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 349{ 350 u32 devres; 351 u32 mask, size, base; 352 353 pci_read_config_dword(dev, port, &devres); 354 if ((devres & enable) != enable) 355 return; 356 base = devres & 0xffff0000; 357 mask = (devres & 0x3f) << 16; 358 size = 128 << 16; 359 for (;;) { 360 unsigned bit = size >> 1; 361 if ((bit & mask) == bit) 362 break; 363 size = bit; 364 } 365 /* 366 * For now we only print it out. Eventually we'll want to 367 * reserve it, but let's get enough confirmation reports first. 368 */ 369 base &= -size; 370 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1); 371} 372 373/* 374 * PIIX4 ACPI: Two IO regions pointed to by longwords at 375 * 0x40 (64 bytes of ACPI registers) 376 * 0x90 (16 bytes of SMB registers) 377 * and a few strange programmable PIIX4 device resources. 378 */ 379static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 380{ 381 u32 region, res_a; 382 383 pci_read_config_dword(dev, 0x40, ®ion); 384 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 385 pci_read_config_dword(dev, 0x90, ®ion); 386 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 387 388 /* Device resource A has enables for some of the other ones */ 389 pci_read_config_dword(dev, 0x5c, &res_a); 390 391 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 392 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 393 394 /* Device resource D is just bitfields for static resources */ 395 396 /* Device 12 enabled? */ 397 if (res_a & (1 << 29)) { 398 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 399 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 400 } 401 /* Device 13 enabled? */ 402 if (res_a & (1 << 30)) { 403 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 404 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 405 } 406 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 407 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 408} 409DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); 410DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi ); 411 412/* 413 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 414 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 415 * 0x58 (64 bytes of GPIO I/O space) 416 */ 417static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 418{ 419 u32 region; 420 421 pci_read_config_dword(dev, 0x40, ®ion); 422 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); 423 424 pci_read_config_dword(dev, 0x58, ®ion); 425 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); 426} 427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); 428DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); 429DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); 430DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); 431DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); 432DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); 433DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); 434DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); 435DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); 436DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); 437 438static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) 439{ 440 u32 region; 441 442 pci_read_config_dword(dev, 0x40, ®ion); 443 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); 444 445 pci_read_config_dword(dev, 0x48, ®ion); 446 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); 447} 448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi ); 449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi ); 450DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi ); 451DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi ); 452DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi ); 453DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi ); 454DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi ); 455DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi ); 456 457/* 458 * VIA ACPI: One IO region pointed to by longword at 459 * 0x48 or 0x20 (256 bytes of ACPI registers) 460 */ 461static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 462{ 463 u8 rev; 464 u32 region; 465 466 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); 467 if (rev & 0x10) { 468 pci_read_config_dword(dev, 0x48, ®ion); 469 region &= PCI_BASE_ADDRESS_IO_MASK; 470 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 471 } 472} 473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); 474 475/* 476 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 477 * 0x48 (256 bytes of ACPI registers) 478 * 0x70 (128 bytes of hardware monitoring register) 479 * 0x90 (16 bytes of SMB registers) 480 */ 481static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 482{ 483 u16 hm; 484 u32 smb; 485 486 quirk_vt82c586_acpi(dev); 487 488 pci_read_config_word(dev, 0x70, &hm); 489 hm &= PCI_BASE_ADDRESS_IO_MASK; 490 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); 491 492 pci_read_config_dword(dev, 0x90, &smb); 493 smb &= PCI_BASE_ADDRESS_IO_MASK; 494 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 495} 496DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); 497 498/* 499 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 500 * 0x88 (128 bytes of power management registers) 501 * 0xd0 (16 bytes of SMB registers) 502 */ 503static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 504{ 505 u16 pm, smb; 506 507 pci_read_config_word(dev, 0x88, &pm); 508 pm &= PCI_BASE_ADDRESS_IO_MASK; 509 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 510 511 pci_read_config_word(dev, 0xd0, &smb); 512 smb &= PCI_BASE_ADDRESS_IO_MASK; 513 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); 514} 515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 516 517 518#ifdef CONFIG_X86_IO_APIC 519 520#include <asm/io_apic.h> 521 522/* 523 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 524 * devices to the external APIC. 525 * 526 * TODO: When we have device-specific interrupt routers, 527 * this code will go away from quirks. 528 */ 529static void quirk_via_ioapic(struct pci_dev *dev) 530{ 531 u8 tmp; 532 533 if (nr_ioapics < 1) 534 tmp = 0; /* nothing routed to external APIC */ 535 else 536 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 537 538 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", 539 tmp == 0 ? "Disa" : "Ena"); 540 541 /* Offset 0x58: External APIC IRQ output control */ 542 pci_write_config_byte (dev, 0x58, tmp); 543} 544DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 545DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 546 547/* 548 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 549 * This leads to doubled level interrupt rates. 550 * Set this bit to get rid of cycle wastage. 551 * Otherwise uncritical. 552 */ 553static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 554{ 555 u8 misc_control2; 556#define BYPASS_APIC_DEASSERT 8 557 558 pci_read_config_byte(dev, 0x5B, &misc_control2); 559 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 560 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); 561 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 562 } 563} 564DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 565DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 566 567/* 568 * The AMD io apic can hang the box when an apic irq is masked. 569 * We check all revs >= B0 (yet not in the pre production!) as the bug 570 * is currently marked NoFix 571 * 572 * We have multiple reports of hangs with this chipset that went away with 573 * noapic specified. For the moment we assume it's the erratum. We may be wrong 574 * of course. However the advice is demonstrably good even if so.. 575 */ 576static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 577{ 578 u8 rev; 579 580 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 581 if (rev >= 0x02) { 582 printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 583 printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); 584 } 585} 586DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); 587 588static void __init quirk_ioapic_rmw(struct pci_dev *dev) 589{ 590 if (dev->devfn == 0 && dev->bus->number == 0) 591 sis_apic_bug = 1; 592} 593DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); 594 595#define AMD8131_revA0 0x01 596#define AMD8131_revB0 0x11 597#define AMD8131_MISC 0x40 598#define AMD8131_NIOAMODE_BIT 0 599static void quirk_amd_8131_ioapic(struct pci_dev *dev) 600{ 601 unsigned char revid, tmp; 602 603 if (nr_ioapics == 0) 604 return; 605 606 pci_read_config_byte(dev, PCI_REVISION_ID, &revid); 607 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) { 608 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); 609 pci_read_config_byte( dev, AMD8131_MISC, &tmp); 610 tmp &= ~(1 << AMD8131_NIOAMODE_BIT); 611 pci_write_config_byte( dev, AMD8131_MISC, tmp); 612 } 613} 614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); 615DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); 616#endif /* CONFIG_X86_IO_APIC */ 617 618 619static void __devinit quirk_via_acpi(struct pci_dev *d) 620{ 621 /* 622 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 623 */ 624 u8 irq; 625 pci_read_config_byte(d, 0x42, &irq); 626 irq &= 0xf; 627 if (irq && (irq != 2)) 628 d->irq = irq; 629} 630DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); 631DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); 632 633 634/* 635 * VIA bridges which have VLink 636 */ 637 638static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 639 640static void quirk_via_bridge(struct pci_dev *dev) 641{ 642 /* See what bridge we have and find the device ranges */ 643 switch (dev->device) { 644 case PCI_DEVICE_ID_VIA_82C686: 645 /* The VT82C686 is special, it attaches to PCI and can have 646 any device number. All its subdevices are functions of 647 that single device. */ 648 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 649 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 650 break; 651 case PCI_DEVICE_ID_VIA_8237: 652 case PCI_DEVICE_ID_VIA_8237A: 653 via_vlink_dev_lo = 15; 654 break; 655 case PCI_DEVICE_ID_VIA_8235: 656 via_vlink_dev_lo = 16; 657 break; 658 case PCI_DEVICE_ID_VIA_8231: 659 case PCI_DEVICE_ID_VIA_8233_0: 660 case PCI_DEVICE_ID_VIA_8233A: 661 case PCI_DEVICE_ID_VIA_8233C_0: 662 via_vlink_dev_lo = 17; 663 break; 664 } 665} 666DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 667DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 668DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 669DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 670DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 671DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 672DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 673DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 674 675/** 676 * quirk_via_vlink - VIA VLink IRQ number update 677 * @dev: PCI device 678 * 679 * If the device we are dealing with is on a PIC IRQ we need to 680 * ensure that the IRQ line register which usually is not relevant 681 * for PCI cards, is actually written so that interrupts get sent 682 * to the right place. 683 * We only do this on systems where a VIA south bridge was detected, 684 * and only for VIA devices on the motherboard (see quirk_via_bridge 685 * above). 686 */ 687 688static void quirk_via_vlink(struct pci_dev *dev) 689{ 690 u8 irq, new_irq; 691 692 /* Check if we have VLink at all */ 693 if (via_vlink_dev_lo == -1) 694 return; 695 696 new_irq = dev->irq; 697 698 /* Don't quirk interrupts outside the legacy IRQ range */ 699 if (!new_irq || new_irq > 15) 700 return; 701 702 /* Internal device ? */ 703 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 704 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 705 return; 706 707 /* This is an internal VLink device on a PIC interrupt. The BIOS 708 ought to have set this but may not have, so we redo it */ 709 710 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 711 if (new_irq != irq) { 712 printk(KERN_INFO "PCI: VIA VLink IRQ fixup for %s, from %d to %d\n", 713 pci_name(dev), irq, new_irq); 714 udelay(15); /* unknown if delay really needed */ 715 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 716 } 717} 718DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 719 720/* 721 * VIA VT82C598 has its device ID settable and many BIOSes 722 * set it to the ID of VT82C597 for backward compatibility. 723 * We need to switch it off to be able to recognize the real 724 * type of the chip. 725 */ 726static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 727{ 728 pci_write_config_byte(dev, 0xfc, 0); 729 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 730} 731DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); 732 733/* 734 * CardBus controllers have a legacy base address that enables them 735 * to respond as i82365 pcmcia controllers. We don't want them to 736 * do this even if the Linux CardBus driver is not loaded, because 737 * the Linux i82365 driver does not (and should not) handle CardBus. 738 */ 739static void quirk_cardbus_legacy(struct pci_dev *dev) 740{ 741 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 742 return; 743 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 744} 745DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 746DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 747 748/* 749 * Following the PCI ordering rules is optional on the AMD762. I'm not 750 * sure what the designers were smoking but let's not inhale... 751 * 752 * To be fair to AMD, it follows the spec by default, its BIOS people 753 * who turn it off! 754 */ 755static void quirk_amd_ordering(struct pci_dev *dev) 756{ 757 u32 pcic; 758 pci_read_config_dword(dev, 0x4C, &pcic); 759 if ((pcic&6)!=6) { 760 pcic |= 6; 761 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); 762 pci_write_config_dword(dev, 0x4C, pcic); 763 pci_read_config_dword(dev, 0x84, &pcic); 764 pcic |= (1<<23); /* Required in this mode */ 765 pci_write_config_dword(dev, 0x84, pcic); 766 } 767} 768DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 769DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 770 771static void __devinit quirk_dunord ( struct pci_dev * dev ) 772{ 773 struct resource *r = &dev->resource [1]; 774 r->start = 0; 775 r->end = 0xffffff; 776} 777DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); 778 779/* 780 * i82380FB mobile docking controller: its PCI-to-PCI bridge 781 * is subtractive decoding (transparent), and does indicate this 782 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 783 * instead of 0x01. 784 */ 785static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 786{ 787 dev->transparent = 1; 788} 789DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); 790DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); 791 792/* 793 * Common misconfiguration of the MediaGX/Geode PCI master that will 794 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 795 * datasheets found at http://www.national.com/ds/GX for info on what 796 * these bits do. <christer@weinigel.se> 797 */ 798static void quirk_mediagx_master(struct pci_dev *dev) 799{ 800 u8 reg; 801 pci_read_config_byte(dev, 0x41, ®); 802 if (reg & 2) { 803 reg &= ~2; 804 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 805 pci_write_config_byte(dev, 0x41, reg); 806 } 807} 808DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 809DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 810 811/* 812 * Ensure C0 rev restreaming is off. This is normally done by 813 * the BIOS but in the odd case it is not the results are corruption 814 * hence the presence of a Linux check 815 */ 816static void quirk_disable_pxb(struct pci_dev *pdev) 817{ 818 u16 config; 819 u8 rev; 820 821 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 822 if (rev != 0x04) /* Only C0 requires this */ 823 return; 824 pci_read_config_word(pdev, 0x40, &config); 825 if (config & (1<<6)) { 826 config &= ~(1<<6); 827 pci_write_config_word(pdev, 0x40, config); 828 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); 829 } 830} 831DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 832DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 833 834 835static void __devinit quirk_sb600_sata(struct pci_dev *pdev) 836{ 837 /* set sb600 sata to ahci mode */ 838 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { 839 u8 tmp; 840 841 pci_read_config_byte(pdev, 0x40, &tmp); 842 pci_write_config_byte(pdev, 0x40, tmp|1); 843 pci_write_config_byte(pdev, 0x9, 1); 844 pci_write_config_byte(pdev, 0xa, 6); 845 pci_write_config_byte(pdev, 0x40, tmp); 846 847 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 848 } 849} 850DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_sb600_sata); 851DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_sb600_sata); 852 853/* 854 * Serverworks CSB5 IDE does not fully support native mode 855 */ 856static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 857{ 858 u8 prog; 859 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 860 if (prog & 5) { 861 prog &= ~5; 862 pdev->class &= ~5; 863 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 864 /* PCI layer will sort out resources */ 865 } 866} 867DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); 868 869/* 870 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 871 */ 872static void __init quirk_ide_samemode(struct pci_dev *pdev) 873{ 874 u8 prog; 875 876 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 877 878 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 879 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); 880 prog &= ~5; 881 pdev->class &= ~5; 882 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 883 } 884} 885DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 886 887/* This was originally an Alpha specific thing, but it really fits here. 888 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 889 */ 890static void __init quirk_eisa_bridge(struct pci_dev *dev) 891{ 892 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 893} 894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); 895 896static void k8t_sound_hostbridge(struct pci_dev *dev) 897{ 898 unsigned char val; 899 900 pci_read_config_byte(dev, 0x50, &val); 901 if (val == 0x88 || val == 0xc8) { 902 /* Assume it's probably a MSI-K8T-Neo2Fir */ 903 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n"); 904 pci_write_config_byte(dev, 0x50, val & (~0x40)); 905 906 /* Verify the Change for Status output */ 907 pci_read_config_byte(dev, 0x50, &val); 908 if (val & 0x40) 909 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n"); 910 else 911 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n"); 912 } 913} 914DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge); 915DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge); 916 917/* 918 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 919 * is not activated. The myth is that Asus said that they do not want the 920 * users to be irritated by just another PCI Device in the Win98 device 921 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 922 * package 2.7.0 for details) 923 * 924 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 925 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 926 * becomes necessary to do this tweak in two steps -- I've chosen the Host 927 * bridge as trigger. 928 * 929 * Note that we used to unhide the SMBus that way on Toshiba laptops 930 * (Satellite A40 and Tecra M2) but then found that the thermal management 931 * was done by SMM code, which could cause unsynchronized concurrent 932 * accesses to the SMBus registers, with potentially bad effects. Thus you 933 * should be very careful when adding new entries: if SMM is accessing the 934 * Intel SMBus, this is a very good reason to leave it hidden. 935 */ 936static int asus_hides_smbus; 937 938static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 939{ 940 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 941 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 942 switch(dev->subsystem_device) { 943 case 0x8025: /* P4B-LX */ 944 case 0x8070: /* P4B */ 945 case 0x8088: /* P4B533 */ 946 case 0x1626: /* L3C notebook */ 947 asus_hides_smbus = 1; 948 } 949 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 950 switch(dev->subsystem_device) { 951 case 0x80b1: /* P4GE-V */ 952 case 0x80b2: /* P4PE */ 953 case 0x8093: /* P4B533-V */ 954 asus_hides_smbus = 1; 955 } 956 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 957 switch(dev->subsystem_device) { 958 case 0x8030: /* P4T533 */ 959 asus_hides_smbus = 1; 960 } 961 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 962 switch (dev->subsystem_device) { 963 case 0x8070: /* P4G8X Deluxe */ 964 asus_hides_smbus = 1; 965 } 966 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 967 switch (dev->subsystem_device) { 968 case 0x80c9: /* PU-DLS */ 969 asus_hides_smbus = 1; 970 } 971 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 972 switch (dev->subsystem_device) { 973 case 0x1751: /* M2N notebook */ 974 case 0x1821: /* M5N notebook */ 975 asus_hides_smbus = 1; 976 } 977 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 978 switch (dev->subsystem_device) { 979 case 0x184b: /* W1N notebook */ 980 case 0x186a: /* M6Ne notebook */ 981 asus_hides_smbus = 1; 982 } 983 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 984 switch (dev->subsystem_device) { 985 case 0x80f2: /* P4P800-X */ 986 asus_hides_smbus = 1; 987 } 988 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 989 switch (dev->subsystem_device) { 990 case 0x1882: /* M6V notebook */ 991 case 0x1977: /* A6VA notebook */ 992 asus_hides_smbus = 1; 993 } 994 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 995 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 996 switch(dev->subsystem_device) { 997 case 0x088C: /* HP Compaq nc8000 */ 998 case 0x0890: /* HP Compaq nc6000 */ 999 asus_hides_smbus = 1; 1000 } 1001 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1002 switch (dev->subsystem_device) { 1003 case 0x12bc: /* HP D330L */ 1004 case 0x12bd: /* HP D530 */ 1005 asus_hides_smbus = 1; 1006 } 1007 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1008 switch (dev->subsystem_device) { 1009 case 0x099c: /* HP Compaq nx6110 */ 1010 asus_hides_smbus = 1; 1011 } 1012 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1013 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1014 switch(dev->subsystem_device) { 1015 case 0xC00C: /* Samsung P35 notebook */ 1016 asus_hides_smbus = 1; 1017 } 1018 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1019 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1020 switch(dev->subsystem_device) { 1021 case 0x0058: /* Compaq Evo N620c */ 1022 asus_hides_smbus = 1; 1023 } 1024 } 1025} 1026DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); 1027DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); 1028DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); 1029DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); 1030DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); 1031DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge ); 1032DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); 1033DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); 1034DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge ); 1035 1036static void asus_hides_smbus_lpc(struct pci_dev *dev) 1037{ 1038 u16 val; 1039 1040 if (likely(!asus_hides_smbus)) 1041 return; 1042 1043 pci_read_config_word(dev, 0xF2, &val); 1044 if (val & 0x8) { 1045 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1046 pci_read_config_word(dev, 0xF2, &val); 1047 if (val & 0x8) 1048 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1049 else 1050 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); 1051 } 1052} 1053DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 1054DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 1055DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); 1056DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 1057DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 1058DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 1059DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 1060DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 1061DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); 1062DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 1063DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 1064DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 1065 1066static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1067{ 1068 u32 val, rcba; 1069 void __iomem *base; 1070 1071 if (likely(!asus_hides_smbus)) 1072 return; 1073 pci_read_config_dword(dev, 0xF0, &rcba); 1074 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */ 1075 if (base == NULL) return; 1076 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ 1077 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ 1078 iounmap(base); 1079 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n"); 1080} 1081DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); 1082DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); 1083 1084/* 1085 * SiS 96x south bridge: BIOS typically hides SMBus device... 1086 */ 1087static void quirk_sis_96x_smbus(struct pci_dev *dev) 1088{ 1089 u8 val = 0; 1090 pci_read_config_byte(dev, 0x77, &val); 1091 if (val & 0x10) { 1092 printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); 1093 pci_write_config_byte(dev, 0x77, val & ~0x10); 1094 } 1095} 1096DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1097DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1098DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1099DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1100DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1101DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1102DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1103DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1104 1105/* 1106 * ... This is further complicated by the fact that some SiS96x south 1107 * bridges pretend to be 85C503/5513 instead. In that case see if we 1108 * spotted a compatible north bridge to make sure. 1109 * (pci_find_device doesn't work yet) 1110 * 1111 * We can also enable the sis96x bit in the discovery register.. 1112 */ 1113#define SIS_DETECT_REGISTER 0x40 1114 1115static void quirk_sis_503(struct pci_dev *dev) 1116{ 1117 u8 reg; 1118 u16 devid; 1119 1120 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1121 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1122 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1123 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1124 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1125 return; 1126 } 1127 1128 /* 1129 * Ok, it now shows up as a 96x.. run the 96x quirk by 1130 * hand in case it has already been processed. 1131 * (depends on link order, which is apparently not guaranteed) 1132 */ 1133 dev->device = devid; 1134 quirk_sis_96x_smbus(dev); 1135} 1136DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1137DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1138 1139 1140/* 1141 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1142 * and MC97 modem controller are disabled when a second PCI soundcard is 1143 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1144 * -- bjd 1145 */ 1146static void asus_hides_ac97_lpc(struct pci_dev *dev) 1147{ 1148 u8 val; 1149 int asus_hides_ac97 = 0; 1150 1151 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1152 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1153 asus_hides_ac97 = 1; 1154 } 1155 1156 if (!asus_hides_ac97) 1157 return; 1158 1159 pci_read_config_byte(dev, 0x50, &val); 1160 if (val & 0xc0) { 1161 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1162 pci_read_config_byte(dev, 0x50, &val); 1163 if (val & 0xc0) 1164 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1165 else 1166 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n"); 1167 } 1168} 1169DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); 1170DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); 1171 1172#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1173 1174/* 1175 * If we are using libata we can drive this chip properly but must 1176 * do this early on to make the additional device appear during 1177 * the PCI scanning. 1178 */ 1179static void quirk_jmicron_ata(struct pci_dev *pdev) 1180{ 1181 u32 conf1, conf5, class; 1182 u8 hdr; 1183 1184 /* Only poke fn 0 */ 1185 if (PCI_FUNC(pdev->devfn)) 1186 return; 1187 1188 pci_read_config_dword(pdev, 0x40, &conf1); 1189 pci_read_config_dword(pdev, 0x80, &conf5); 1190 1191 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1192 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1193 1194 switch (pdev->device) { 1195 case PCI_DEVICE_ID_JMICRON_JMB360: 1196 /* The controller should be in single function ahci mode */ 1197 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1198 break; 1199 1200 case PCI_DEVICE_ID_JMICRON_JMB365: 1201 case PCI_DEVICE_ID_JMICRON_JMB366: 1202 /* Redirect IDE second PATA port to the right spot */ 1203 conf5 |= (1 << 24); 1204 /* Fall through */ 1205 case PCI_DEVICE_ID_JMICRON_JMB361: 1206 case PCI_DEVICE_ID_JMICRON_JMB363: 1207 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1208 /* Set the class codes correctly and then direct IDE 0 */ 1209 conf1 |= 0x00C2A102; /* Set 1, 8, 13, 15, 17, 22, 23 */ 1210 break; 1211 1212 case PCI_DEVICE_ID_JMICRON_JMB368: 1213 /* The controller should be in single function IDE mode */ 1214 conf1 |= 0x00C00000; /* Set 22, 23 */ 1215 break; 1216 } 1217 1218 pci_write_config_dword(pdev, 0x40, conf1); 1219 pci_write_config_dword(pdev, 0x80, conf5); 1220 1221 /* Update pdev accordingly */ 1222 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1223 pdev->hdr_type = hdr & 0x7f; 1224 pdev->multifunction = !!(hdr & 0x80); 1225 1226 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1227 pdev->class = class >> 8; 1228} 1229DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1230DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1231DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1232DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1233DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1234DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1235DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1236DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1237DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1238DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1239DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1240DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1241 1242#endif 1243 1244#ifdef CONFIG_X86_IO_APIC 1245static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1246{ 1247 int i; 1248 1249 if ((pdev->class >> 8) != 0xff00) 1250 return; 1251 1252 /* the first BAR is the location of the IO APIC...we must 1253 * not touch this (and it's already covered by the fixmap), so 1254 * forcibly insert it into the resource tree */ 1255 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1256 insert_resource(&iomem_resource, &pdev->resource[0]); 1257 1258 /* The next five BARs all seem to be rubbish, so just clean 1259 * them out */ 1260 for (i=1; i < 6; i++) { 1261 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1262 } 1263 1264} 1265DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); 1266#endif 1267 1268int pcie_mch_quirk; 1269EXPORT_SYMBOL(pcie_mch_quirk); 1270 1271static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1272{ 1273 pcie_mch_quirk = 1; 1274} 1275DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); 1276DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); 1277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); 1278 1279 1280/* 1281 * It's possible for the MSI to get corrupted if shpc and acpi 1282 * are used together on certain PXH-based systems. 1283 */ 1284static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1285{ 1286 pci_msi_off(dev); 1287 1288 dev->no_msi = 1; 1289 1290 printk(KERN_WARNING "PCI: PXH quirk detected, " 1291 "disabling MSI for SHPC device\n"); 1292} 1293DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1294DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1295DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1296DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1297DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1298 1299/* 1300 * Some Intel PCI Express chipsets have trouble with downstream 1301 * device power management. 1302 */ 1303static void quirk_intel_pcie_pm(struct pci_dev * dev) 1304{ 1305 pci_pm_d3_delay = 120; 1306 dev->no_d1d2 = 1; 1307} 1308 1309DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1311DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1312DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1313DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1314DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1315DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1316DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1317DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1318DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1319DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1320DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1321DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1322DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1325DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1326DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1327DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1328DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1329DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1330 1331/* 1332 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1333 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1334 * Re-allocate the region if needed... 1335 */ 1336static void __init quirk_tc86c001_ide(struct pci_dev *dev) 1337{ 1338 struct resource *r = &dev->resource[0]; 1339 1340 if (r->start & 0x8) { 1341 r->start = 0; 1342 r->end = 0xf; 1343 } 1344} 1345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1346 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1347 quirk_tc86c001_ide); 1348 1349static void __devinit quirk_netmos(struct pci_dev *dev) 1350{ 1351 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1352 unsigned int num_serial = dev->subsystem_device & 0xf; 1353 1354 /* 1355 * These Netmos parts are multiport serial devices with optional 1356 * parallel ports. Even when parallel ports are present, they 1357 * are identified as class SERIAL, which means the serial driver 1358 * will claim them. To prevent this, mark them as class OTHER. 1359 * These combo devices should be claimed by parport_serial. 1360 * 1361 * The subdevice ID is of the form 0x00PS, where <P> is the number 1362 * of parallel ports and <S> is the number of serial ports. 1363 */ 1364 switch (dev->device) { 1365 case PCI_DEVICE_ID_NETMOS_9735: 1366 case PCI_DEVICE_ID_NETMOS_9745: 1367 case PCI_DEVICE_ID_NETMOS_9835: 1368 case PCI_DEVICE_ID_NETMOS_9845: 1369 case PCI_DEVICE_ID_NETMOS_9855: 1370 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1371 num_parallel) { 1372 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " 1373 "%u serial); changing class SERIAL to OTHER " 1374 "(use parport_serial)\n", 1375 dev->device, num_parallel, num_serial); 1376 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1377 (dev->class & 0xff); 1378 } 1379 } 1380} 1381DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1382 1383static void __devinit quirk_e100_interrupt(struct pci_dev *dev) 1384{ 1385 u16 command; 1386 u32 bar; 1387 u8 __iomem *csr; 1388 u8 cmd_hi; 1389 1390 switch (dev->device) { 1391 /* PCI IDs taken from drivers/net/e100.c */ 1392 case 0x1029: 1393 case 0x1030 ... 0x1034: 1394 case 0x1038 ... 0x103E: 1395 case 0x1050 ... 0x1057: 1396 case 0x1059: 1397 case 0x1064 ... 0x106B: 1398 case 0x1091 ... 0x1095: 1399 case 0x1209: 1400 case 0x1229: 1401 case 0x2449: 1402 case 0x2459: 1403 case 0x245D: 1404 case 0x27DC: 1405 break; 1406 default: 1407 return; 1408 } 1409 1410 /* 1411 * Some firmware hands off the e100 with interrupts enabled, 1412 * which can cause a flood of interrupts if packets are 1413 * received before the driver attaches to the device. So 1414 * disable all e100 interrupts here. The driver will 1415 * re-enable them when it's ready. 1416 */ 1417 pci_read_config_word(dev, PCI_COMMAND, &command); 1418 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar); 1419 1420 if (!(command & PCI_COMMAND_MEMORY) || !bar) 1421 return; 1422 1423 csr = ioremap(bar, 8); 1424 if (!csr) { 1425 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n", 1426 pci_name(dev)); 1427 return; 1428 } 1429 1430 cmd_hi = readb(csr + 3); 1431 if (cmd_hi == 0) { 1432 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts " 1433 "enabled, disabling\n", pci_name(dev)); 1434 writeb(1, csr + 3); 1435 } 1436 1437 iounmap(csr); 1438} 1439DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); 1440 1441static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1442{ 1443 /* rev 1 ncr53c810 chips don't set the class at all which means 1444 * they don't get their resources remapped. Fix that here. 1445 */ 1446 1447 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1448 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n"); 1449 dev->class = PCI_CLASS_STORAGE_SCSI; 1450 } 1451} 1452DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1453 1454static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) 1455{ 1456 while (f < end) { 1457 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 1458 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 1459 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); 1460 f->hook(dev); 1461 } 1462 f++; 1463 } 1464} 1465 1466extern struct pci_fixup __start_pci_fixups_early[]; 1467extern struct pci_fixup __end_pci_fixups_early[]; 1468extern struct pci_fixup __start_pci_fixups_header[]; 1469extern struct pci_fixup __end_pci_fixups_header[]; 1470extern struct pci_fixup __start_pci_fixups_final[]; 1471extern struct pci_fixup __end_pci_fixups_final[]; 1472extern struct pci_fixup __start_pci_fixups_enable[]; 1473extern struct pci_fixup __end_pci_fixups_enable[]; 1474extern struct pci_fixup __start_pci_fixups_resume[]; 1475extern struct pci_fixup __end_pci_fixups_resume[]; 1476 1477 1478void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 1479{ 1480 struct pci_fixup *start, *end; 1481 1482 switch(pass) { 1483 case pci_fixup_early: 1484 start = __start_pci_fixups_early; 1485 end = __end_pci_fixups_early; 1486 break; 1487 1488 case pci_fixup_header: 1489 start = __start_pci_fixups_header; 1490 end = __end_pci_fixups_header; 1491 break; 1492 1493 case pci_fixup_final: 1494 start = __start_pci_fixups_final; 1495 end = __end_pci_fixups_final; 1496 break; 1497 1498 case pci_fixup_enable: 1499 start = __start_pci_fixups_enable; 1500 end = __end_pci_fixups_enable; 1501 break; 1502 1503 case pci_fixup_resume: 1504 start = __start_pci_fixups_resume; 1505 end = __end_pci_fixups_resume; 1506 break; 1507 1508 default: 1509 /* stupid compiler warning, you would think with an enum... */ 1510 return; 1511 } 1512 pci_do_fixups(dev, start, end); 1513} 1514EXPORT_SYMBOL(pci_fixup_device); 1515 1516/* Enable 1k I/O space granularity on the Intel P64H2 */ 1517static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) 1518{ 1519 u16 en1k; 1520 u8 io_base_lo, io_limit_lo; 1521 unsigned long base, limit; 1522 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1523 1524 pci_read_config_word(dev, 0x40, &en1k); 1525 1526 if (en1k & 0x200) { 1527 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); 1528 1529 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 1530 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 1531 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1532 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1533 1534 if (base <= limit) { 1535 res->start = base; 1536 res->end = limit + 0x3ff; 1537 } 1538 } 1539} 1540DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 1541 1542/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 1543 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() 1544 * in drivers/pci/setup-bus.c 1545 */ 1546static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) 1547{ 1548 u16 en1k, iobl_adr, iobl_adr_1k; 1549 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1550 1551 pci_read_config_word(dev, 0x40, &en1k); 1552 1553 if (en1k & 0x200) { 1554 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); 1555 1556 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); 1557 1558 if (iobl_adr != iobl_adr_1k) { 1559 printk(KERN_INFO "PCI: Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1 KB Granularity\n", 1560 iobl_adr,iobl_adr_1k); 1561 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); 1562 } 1563 } 1564} 1565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); 1566 1567/* Under some circumstances, AER is not linked with extended capabilities. 1568 * Force it to be linked by setting the corresponding control bit in the 1569 * config space. 1570 */ 1571static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 1572{ 1573 uint8_t b; 1574 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1575 if (!(b & 0x20)) { 1576 pci_write_config_byte(dev, 0xf41, b | 0x20); 1577 printk(KERN_INFO 1578 "PCI: Linking AER extended capability on %s\n", 1579 pci_name(dev)); 1580 } 1581 } 1582} 1583DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1584 quirk_nvidia_ck804_pcie_aer_ext_cap); 1585DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1586 quirk_nvidia_ck804_pcie_aer_ext_cap); 1587 1588#ifdef CONFIG_PCI_MSI 1589/* Some chipsets do not support MSI. We cannot easily rely on setting 1590 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 1591 * some other busses controlled by the chipset even if Linux is not 1592 * aware of it. Instead of setting the flag on all busses in the 1593 * machine, simply disable MSI globally. 1594 */ 1595static void __init quirk_disable_all_msi(struct pci_dev *dev) 1596{ 1597 pci_no_msi(); 1598 printk(KERN_WARNING "PCI: MSI quirk detected. MSI deactivated.\n"); 1599} 1600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 1601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000_PCIX, quirk_disable_all_msi); 1602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 1603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 1604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 1605 1606/* Disable MSI on chipsets that are known to not support it */ 1607static void __devinit quirk_disable_msi(struct pci_dev *dev) 1608{ 1609 if (dev->subordinate) { 1610 printk(KERN_WARNING "PCI: MSI quirk detected. " 1611 "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n", 1612 pci_name(dev)); 1613 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1614 } 1615} 1616DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 1617 1618/* Go through the list of Hypertransport capabilities and 1619 * return 1 if a HT MSI capability is found and enabled */ 1620static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) 1621{ 1622 int pos, ttl = 48; 1623 1624 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 1625 while (pos && ttl--) { 1626 u8 flags; 1627 1628 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 1629 &flags) == 0) 1630 { 1631 printk(KERN_INFO "PCI: Found %s HT MSI Mapping on %s\n", 1632 flags & HT_MSI_FLAGS_ENABLE ? 1633 "enabled" : "disabled", pci_name(dev)); 1634 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 1635 } 1636 1637 pos = pci_find_next_ht_capability(dev, pos, 1638 HT_CAPTYPE_MSI_MAPPING); 1639 } 1640 return 0; 1641} 1642 1643/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 1644static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) 1645{ 1646 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 1647 printk(KERN_WARNING "PCI: MSI quirk detected. " 1648 "MSI disabled on chipset %s.\n", 1649 pci_name(dev)); 1650 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1651 } 1652} 1653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 1654 quirk_msi_ht_cap); 1655 1656/* The nVidia CK804 chipset may have 2 HT MSI mappings. 1657 * MSI are supported if the MSI capability set in any of these mappings. 1658 */ 1659static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 1660{ 1661 struct pci_dev *pdev; 1662 1663 if (!dev->subordinate) 1664 return; 1665 1666 /* check HT MSI cap on this chipset and the root one. 1667 * a single one having MSI is enough to be sure that MSI are supported. 1668 */ 1669 pdev = pci_get_slot(dev->bus, 0); 1670 if (!pdev) 1671 return; 1672 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 1673 printk(KERN_WARNING "PCI: MSI quirk detected. " 1674 "MSI disabled on chipset %s.\n", 1675 pci_name(dev)); 1676 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1677 } 1678 pci_dev_put(pdev); 1679} 1680DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1681 quirk_nvidia_ck804_msi_ht_cap); 1682#endif /* CONFIG_PCI_MSI */ 1683