1/* 2 * probe.c - PCI detection and setup code 3 */ 4 5#include <linux/kernel.h> 6#include <linux/delay.h> 7#include <linux/init.h> 8#include <linux/pci.h> 9#include <linux/slab.h> 10#include <linux/module.h> 11#include <linux/cpumask.h> 12#include "pci.h" 13 14#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 15#define CARDBUS_RESERVE_BUSNR 3 16#define PCI_CFG_SPACE_SIZE 256 17#define PCI_CFG_SPACE_EXP_SIZE 4096 18 19/* Ugh. Need to stop exporting this to modules. */ 20LIST_HEAD(pci_root_buses); 21EXPORT_SYMBOL(pci_root_buses); 22 23LIST_HEAD(pci_devices); 24 25#ifdef HAVE_PCI_LEGACY 26/** 27 * pci_create_legacy_files - create legacy I/O port and memory files 28 * @b: bus to create files under 29 * 30 * Some platforms allow access to legacy I/O port and ISA memory space on 31 * a per-bus basis. This routine creates the files and ties them into 32 * their associated read, write and mmap files from pci-sysfs.c 33 */ 34static void pci_create_legacy_files(struct pci_bus *b) 35{ 36 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2, 37 GFP_ATOMIC); 38 if (b->legacy_io) { 39 b->legacy_io->attr.name = "legacy_io"; 40 b->legacy_io->size = 0xffff; 41 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR; 42 b->legacy_io->attr.owner = THIS_MODULE; 43 b->legacy_io->read = pci_read_legacy_io; 44 b->legacy_io->write = pci_write_legacy_io; 45 class_device_create_bin_file(&b->class_dev, b->legacy_io); 46 47 /* Allocated above after the legacy_io struct */ 48 b->legacy_mem = b->legacy_io + 1; 49 b->legacy_mem->attr.name = "legacy_mem"; 50 b->legacy_mem->size = 1024*1024; 51 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR; 52 b->legacy_mem->attr.owner = THIS_MODULE; 53 b->legacy_mem->mmap = pci_mmap_legacy_mem; 54 class_device_create_bin_file(&b->class_dev, b->legacy_mem); 55 } 56} 57 58void pci_remove_legacy_files(struct pci_bus *b) 59{ 60 if (b->legacy_io) { 61 class_device_remove_bin_file(&b->class_dev, b->legacy_io); 62 class_device_remove_bin_file(&b->class_dev, b->legacy_mem); 63 kfree(b->legacy_io); /* both are allocated here */ 64 } 65} 66#else /* !HAVE_PCI_LEGACY */ 67static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 68void pci_remove_legacy_files(struct pci_bus *bus) { return; } 69#endif /* HAVE_PCI_LEGACY */ 70 71/* 72 * PCI Bus Class Devices 73 */ 74static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev, 75 char *buf) 76{ 77 int ret; 78 cpumask_t cpumask; 79 80 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev)); 81 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask); 82 if (ret < PAGE_SIZE) 83 buf[ret++] = '\n'; 84 return ret; 85} 86CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL); 87 88/* 89 * PCI Bus Class 90 */ 91static void release_pcibus_dev(struct class_device *class_dev) 92{ 93 struct pci_bus *pci_bus = to_pci_bus(class_dev); 94 95 if (pci_bus->bridge) 96 put_device(pci_bus->bridge); 97 kfree(pci_bus); 98} 99 100static struct class pcibus_class = { 101 .name = "pci_bus", 102 .release = &release_pcibus_dev, 103}; 104 105static int __init pcibus_class_init(void) 106{ 107 return class_register(&pcibus_class); 108} 109postcore_initcall(pcibus_class_init); 110 111/* 112 * Translate the low bits of the PCI base 113 * to the resource type 114 */ 115static inline unsigned int pci_calc_resource_flags(unsigned int flags) 116{ 117 if (flags & PCI_BASE_ADDRESS_SPACE_IO) 118 return IORESOURCE_IO; 119 120 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 121 return IORESOURCE_MEM | IORESOURCE_PREFETCH; 122 123 return IORESOURCE_MEM; 124} 125 126/* 127 * Find the extent of a PCI decode.. 128 */ 129static u32 pci_size(u32 base, u32 maxbase, u32 mask) 130{ 131 u32 size = mask & maxbase; /* Find the significant bits */ 132 if (!size) 133 return 0; 134 135 /* Get the lowest of them to find the decode size, and 136 from that the extent. */ 137 size = (size & ~(size-1)) - 1; 138 139 /* base == maxbase can be valid only if the BAR has 140 already been programmed with all 1s. */ 141 if (base == maxbase && ((base | size) & mask) != mask) 142 return 0; 143 144 return size; 145} 146 147static u64 pci_size64(u64 base, u64 maxbase, u64 mask) 148{ 149 u64 size = mask & maxbase; /* Find the significant bits */ 150 if (!size) 151 return 0; 152 153 /* Get the lowest of them to find the decode size, and 154 from that the extent. */ 155 size = (size & ~(size-1)) - 1; 156 157 /* base == maxbase can be valid only if the BAR has 158 already been programmed with all 1s. */ 159 if (base == maxbase && ((base | size) & mask) != mask) 160 return 0; 161 162 return size; 163} 164 165static inline int is_64bit_memory(u32 mask) 166{ 167 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == 168 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) 169 return 1; 170 return 0; 171} 172 173static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 174{ 175 unsigned int pos, reg, next; 176 u32 l, sz; 177 struct resource *res; 178 179 for(pos=0; pos<howmany; pos = next) { 180 u64 l64; 181 u64 sz64; 182 u32 raw_sz; 183 184 next = pos+1; 185 res = &dev->resource[pos]; 186 res->name = pci_name(dev); 187 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 188 pci_read_config_dword(dev, reg, &l); 189 pci_write_config_dword(dev, reg, ~0); 190 pci_read_config_dword(dev, reg, &sz); 191 pci_write_config_dword(dev, reg, l); 192 if (!sz || sz == 0xffffffff) 193 continue; 194 if (l == 0xffffffff) 195 l = 0; 196 raw_sz = sz; 197 if ((l & PCI_BASE_ADDRESS_SPACE) == 198 PCI_BASE_ADDRESS_SPACE_MEMORY) { 199 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK); 200 /* 201 * For 64bit prefetchable memory sz could be 0, if the 202 * real size is bigger than 4G, so we need to check 203 * szhi for that. 204 */ 205 if (!is_64bit_memory(l) && !sz) 206 continue; 207 res->start = l & PCI_BASE_ADDRESS_MEM_MASK; 208 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; 209 } else { 210 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); 211 if (!sz) 212 continue; 213 res->start = l & PCI_BASE_ADDRESS_IO_MASK; 214 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; 215 } 216 res->end = res->start + (unsigned long) sz; 217 res->flags |= pci_calc_resource_flags(l); 218 if (is_64bit_memory(l)) { 219 u32 szhi, lhi; 220 221 pci_read_config_dword(dev, reg+4, &lhi); 222 pci_write_config_dword(dev, reg+4, ~0); 223 pci_read_config_dword(dev, reg+4, &szhi); 224 pci_write_config_dword(dev, reg+4, lhi); 225 sz64 = ((u64)szhi << 32) | raw_sz; 226 l64 = ((u64)lhi << 32) | l; 227 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); 228 next++; 229#if BITS_PER_LONG == 64 230 if (!sz64) { 231 res->start = 0; 232 res->end = 0; 233 res->flags = 0; 234 continue; 235 } 236 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; 237 res->end = res->start + sz64; 238#else 239 if (sz64 > 0x100000000ULL) { 240 printk(KERN_ERR "PCI: Unable to handle 64-bit " 241 "BAR for device %s\n", pci_name(dev)); 242 res->start = 0; 243 res->flags = 0; 244 } else if (lhi) { 245 /* 64-bit wide address, treat as disabled */ 246 pci_write_config_dword(dev, reg, 247 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK); 248 pci_write_config_dword(dev, reg+4, 0); 249 res->start = 0; 250 res->end = sz; 251 } 252#endif 253 } 254 } 255 if (rom) { 256 dev->rom_base_reg = rom; 257 res = &dev->resource[PCI_ROM_RESOURCE]; 258 res->name = pci_name(dev); 259 pci_read_config_dword(dev, rom, &l); 260 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE); 261 pci_read_config_dword(dev, rom, &sz); 262 pci_write_config_dword(dev, rom, l); 263 if (l == 0xffffffff) 264 l = 0; 265 if (sz && sz != 0xffffffff) { 266 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK); 267 if (sz) { 268 res->flags = (l & IORESOURCE_ROM_ENABLE) | 269 IORESOURCE_MEM | IORESOURCE_PREFETCH | 270 IORESOURCE_READONLY | IORESOURCE_CACHEABLE; 271 res->start = l & PCI_ROM_ADDRESS_MASK; 272 res->end = res->start + (unsigned long) sz; 273 } 274 } 275 } 276} 277 278void __devinit pci_read_bridge_bases(struct pci_bus *child) 279{ 280 struct pci_dev *dev = child->self; 281 u8 io_base_lo, io_limit_lo; 282 u16 mem_base_lo, mem_limit_lo; 283 unsigned long base, limit; 284 struct resource *res; 285 int i; 286 287 if (!dev) /* It's a host bus, nothing to read */ 288 return; 289 290 if (dev->transparent) { 291 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev)); 292 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++) 293 child->resource[i] = child->parent->resource[i - 3]; 294 } 295 296 for(i=0; i<3; i++) 297 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 298 299 res = child->resource[0]; 300 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 301 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 302 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; 303 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; 304 305 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 306 u16 io_base_hi, io_limit_hi; 307 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 308 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 309 base |= (io_base_hi << 16); 310 limit |= (io_limit_hi << 16); 311 } 312 313 if (base <= limit) { 314 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 315 if (!res->start) 316 res->start = base; 317 if (!res->end) 318 res->end = limit + 0xfff; 319 } 320 321 res = child->resource[1]; 322 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 323 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 324 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 325 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 326 if (base <= limit) { 327 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 328 res->start = base; 329 res->end = limit + 0xfffff; 330 } 331 332 res = child->resource[2]; 333 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 334 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 335 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 336 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 337 338 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 339 u32 mem_base_hi, mem_limit_hi; 340 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 341 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 342 343 /* 344 * Some bridges set the base > limit by default, and some 345 * (broken) BIOSes do not initialize them. If we find 346 * this, just assume they are not being used. 347 */ 348 if (mem_base_hi <= mem_limit_hi) { 349#if BITS_PER_LONG == 64 350 base |= ((long) mem_base_hi) << 32; 351 limit |= ((long) mem_limit_hi) << 32; 352#else 353 if (mem_base_hi || mem_limit_hi) { 354 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev)); 355 return; 356 } 357#endif 358 } 359 } 360 if (base <= limit) { 361 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; 362 res->start = base; 363 res->end = limit + 0xfffff; 364 } 365} 366 367static struct pci_bus * pci_alloc_bus(void) 368{ 369 struct pci_bus *b; 370 371 b = kzalloc(sizeof(*b), GFP_KERNEL); 372 if (b) { 373 INIT_LIST_HEAD(&b->node); 374 INIT_LIST_HEAD(&b->children); 375 INIT_LIST_HEAD(&b->devices); 376 } 377 return b; 378} 379 380static struct pci_bus * __devinit 381pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr) 382{ 383 struct pci_bus *child; 384 int i; 385 int retval; 386 387 /* 388 * Allocate a new bus, and inherit stuff from the parent.. 389 */ 390 child = pci_alloc_bus(); 391 if (!child) 392 return NULL; 393 394 child->self = bridge; 395 child->parent = parent; 396 child->ops = parent->ops; 397 child->sysdata = parent->sysdata; 398 child->bus_flags = parent->bus_flags; 399 child->bridge = get_device(&bridge->dev); 400 401 child->class_dev.class = &pcibus_class; 402 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr); 403 retval = class_device_register(&child->class_dev); 404 if (retval) 405 goto error_register; 406 retval = class_device_create_file(&child->class_dev, 407 &class_device_attr_cpuaffinity); 408 if (retval) 409 goto error_file_create; 410 411 /* 412 * Set up the primary, secondary and subordinate 413 * bus numbers. 414 */ 415 child->number = child->secondary = busnr; 416 child->primary = parent->secondary; 417 child->subordinate = 0xff; 418 419 /* Set up default resource pointers and names.. */ 420 for (i = 0; i < 4; i++) { 421 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 422 child->resource[i]->name = child->name; 423 } 424 bridge->subordinate = child; 425 426 return child; 427 428error_file_create: 429 class_device_unregister(&child->class_dev); 430error_register: 431 kfree(child); 432 return NULL; 433} 434 435struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) 436{ 437 struct pci_bus *child; 438 439 child = pci_alloc_child_bus(parent, dev, busnr); 440 if (child) { 441 down_write(&pci_bus_sem); 442 list_add_tail(&child->node, &parent->children); 443 up_write(&pci_bus_sem); 444 } 445 return child; 446} 447 448static void pci_enable_crs(struct pci_dev *dev) 449{ 450 u16 cap, rpctl; 451 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP); 452 if (!rpcap) 453 return; 454 455 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap); 456 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT) 457 return; 458 459 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl); 460 rpctl |= PCI_EXP_RTCTL_CRSSVE; 461 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl); 462} 463 464static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) 465{ 466 struct pci_bus *parent = child->parent; 467 468 /* Attempts to fix that up are really dangerous unless 469 we're going to re-assign all bus numbers. */ 470 if (!pcibios_assign_all_busses()) 471 return; 472 473 while (parent->parent && parent->subordinate < max) { 474 parent->subordinate = max; 475 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); 476 parent = parent->parent; 477 } 478} 479 480unsigned int pci_scan_child_bus(struct pci_bus *bus); 481 482/* 483 * If it's a bridge, configure it and scan the bus behind it. 484 * For CardBus bridges, we don't scan behind as the devices will 485 * be handled by the bridge driver itself. 486 * 487 * We need to process bridges in two passes -- first we scan those 488 * already configured by the BIOS and after we are done with all of 489 * them, we proceed to assigning numbers to the remaining buses in 490 * order to avoid overlaps between old and new bus numbers. 491 */ 492int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass) 493{ 494 struct pci_bus *child; 495 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 496 u32 buses, i, j = 0; 497 u16 bctl; 498 499 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 500 501 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n", 502 pci_name(dev), buses & 0xffffff, pass); 503 504 /* Disable MasterAbortMode during probing to avoid reporting 505 of bus errors (in some architectures) */ 506 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 507 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 508 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 509 510 pci_enable_crs(dev); 511 512 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) { 513 unsigned int cmax, busnr; 514 /* 515 * Bus already configured by firmware, process it in the first 516 * pass and just note the configuration. 517 */ 518 if (pass) 519 goto out; 520 busnr = (buses >> 8) & 0xFF; 521 522 /* 523 * If we already got to this bus through a different bridge, 524 * ignore it. This can happen with the i450NX chipset. 525 */ 526 if (pci_find_bus(pci_domain_nr(bus), busnr)) { 527 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n", 528 pci_domain_nr(bus), busnr); 529 goto out; 530 } 531 532 child = pci_add_new_bus(bus, dev, busnr); 533 if (!child) 534 goto out; 535 child->primary = buses & 0xFF; 536 child->subordinate = (buses >> 16) & 0xFF; 537 child->bridge_ctl = bctl; 538 539 cmax = pci_scan_child_bus(child); 540 if (cmax > max) 541 max = cmax; 542 if (child->subordinate > max) 543 max = child->subordinate; 544 } else { 545 /* 546 * We need to assign a number to this bus which we always 547 * do in the second pass. 548 */ 549 if (!pass) { 550 if (pcibios_assign_all_busses()) 551 /* Temporarily disable forwarding of the 552 configuration cycles on all bridges in 553 this bus segment to avoid possible 554 conflicts in the second pass between two 555 bridges programmed with overlapping 556 bus ranges. */ 557 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 558 buses & ~0xffffff); 559 goto out; 560 } 561 562 /* Clear errors */ 563 pci_write_config_word(dev, PCI_STATUS, 0xffff); 564 565 /* Prevent assigning a bus number that already exists. 566 * This can happen when a bridge is hot-plugged */ 567 if (pci_find_bus(pci_domain_nr(bus), max+1)) 568 goto out; 569 child = pci_add_new_bus(bus, dev, ++max); 570 buses = (buses & 0xff000000) 571 | ((unsigned int)(child->primary) << 0) 572 | ((unsigned int)(child->secondary) << 8) 573 | ((unsigned int)(child->subordinate) << 16); 574 575 /* 576 * yenta.c forces a secondary latency timer of 176. 577 * Copy that behaviour here. 578 */ 579 if (is_cardbus) { 580 buses &= ~0xff000000; 581 buses |= CARDBUS_LATENCY_TIMER << 24; 582 } 583 584 /* 585 * We need to blast all three values with a single write. 586 */ 587 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 588 589 if (!is_cardbus) { 590 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA; 591 /* 592 * Adjust subordinate busnr in parent buses. 593 * We do this before scanning for children because 594 * some devices may not be detected if the bios 595 * was lazy. 596 */ 597 pci_fixup_parent_subordinate_busnr(child, max); 598 /* Now we can scan all subordinate buses... */ 599 max = pci_scan_child_bus(child); 600 /* 601 * now fix it up again since we have found 602 * the real value of max. 603 */ 604 pci_fixup_parent_subordinate_busnr(child, max); 605 } else { 606 /* 607 * For CardBus bridges, we leave 4 bus numbers 608 * as cards with a PCI-to-PCI bridge can be 609 * inserted later. 610 */ 611 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { 612 struct pci_bus *parent = bus; 613 if (pci_find_bus(pci_domain_nr(bus), 614 max+i+1)) 615 break; 616 while (parent->parent) { 617 if ((!pcibios_assign_all_busses()) && 618 (parent->subordinate > max) && 619 (parent->subordinate <= max+i)) { 620 j = 1; 621 } 622 parent = parent->parent; 623 } 624 if (j) { 625 /* 626 * Often, there are two cardbus bridges 627 * -- try to leave one valid bus number 628 * for each one. 629 */ 630 i /= 2; 631 break; 632 } 633 } 634 max += i; 635 pci_fixup_parent_subordinate_busnr(child, max); 636 } 637 /* 638 * Set the subordinate bus number to its real value. 639 */ 640 child->subordinate = max; 641 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 642 } 643 644 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number); 645 646 while (bus->parent) { 647 if ((child->subordinate > bus->subordinate) || 648 (child->number > bus->subordinate) || 649 (child->number < bus->number) || 650 (child->subordinate < bus->number)) { 651 printk(KERN_WARNING "PCI: Bus #%02x (-#%02x) is " 652 "hidden behind%s bridge #%02x (-#%02x)%s\n", 653 child->number, child->subordinate, 654 bus->self->transparent ? " transparent" : " ", 655 bus->number, bus->subordinate, 656 pcibios_assign_all_busses() ? " " : 657 " (try 'pci=assign-busses')"); 658 printk(KERN_WARNING "Please report the result to " 659 "linux-kernel to fix this permanently\n"); 660 } 661 bus = bus->parent; 662 } 663 664out: 665 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 666 667 return max; 668} 669 670/* 671 * Read interrupt line and base address registers. 672 * The architecture-dependent code can tweak these, of course. 673 */ 674static void pci_read_irq(struct pci_dev *dev) 675{ 676 unsigned char irq; 677 678 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 679 dev->pin = irq; 680 if (irq) 681 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 682 dev->irq = irq; 683} 684 685#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 686 687/** 688 * pci_setup_device - fill in class and map information of a device 689 * @dev: the device structure to fill 690 * 691 * Initialize the device structure with information about the device's 692 * vendor,class,memory and IO-space addresses,IRQ lines etc. 693 * Called at initialisation of the PCI subsystem and by CardBus services. 694 * Returns 0 on success and -1 if unknown type of device (not normal, bridge 695 * or CardBus). 696 */ 697static int pci_setup_device(struct pci_dev * dev) 698{ 699 u32 class; 700 701 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 702 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 703 704 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 705 class >>= 8; /* upper 3 bytes */ 706 dev->class = class; 707 class >>= 8; 708 709 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev), 710 dev->vendor, dev->device, class, dev->hdr_type); 711 712 /* "Unknown power state" */ 713 dev->current_state = PCI_UNKNOWN; 714 715 /* Early fixups, before probing the BARs */ 716 pci_fixup_device(pci_fixup_early, dev); 717 class = dev->class >> 8; 718 719 switch (dev->hdr_type) { /* header type */ 720 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 721 if (class == PCI_CLASS_BRIDGE_PCI) 722 goto bad; 723 pci_read_irq(dev); 724 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 725 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 726 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); 727 728 /* 729 * Do the ugly legacy mode stuff here rather than broken chip 730 * quirk code. Legacy mode ATA controllers have fixed 731 * addresses. These are not always echoed in BAR0-3, and 732 * BAR0-3 in a few cases contain junk! 733 */ 734 if (class == PCI_CLASS_STORAGE_IDE) { 735 u8 progif; 736 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 737 if ((progif & 1) == 0) { 738 dev->resource[0].start = 0x1F0; 739 dev->resource[0].end = 0x1F7; 740 dev->resource[0].flags = LEGACY_IO_RESOURCE; 741 dev->resource[1].start = 0x3F6; 742 dev->resource[1].end = 0x3F6; 743 dev->resource[1].flags = LEGACY_IO_RESOURCE; 744 } 745 if ((progif & 4) == 0) { 746 dev->resource[2].start = 0x170; 747 dev->resource[2].end = 0x177; 748 dev->resource[2].flags = LEGACY_IO_RESOURCE; 749 dev->resource[3].start = 0x376; 750 dev->resource[3].end = 0x376; 751 dev->resource[3].flags = LEGACY_IO_RESOURCE; 752 } 753 } 754 break; 755 756 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 757 if (class != PCI_CLASS_BRIDGE_PCI) 758 goto bad; 759 /* The PCI-to-PCI bridge spec requires that subtractive 760 decoding (i.e. transparent) bridge must have programming 761 interface code of 0x01. */ 762 pci_read_irq(dev); 763 dev->transparent = ((dev->class & 0xff) == 1); 764 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 765 break; 766 767 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 768 if (class != PCI_CLASS_BRIDGE_CARDBUS) 769 goto bad; 770 pci_read_irq(dev); 771 pci_read_bases(dev, 1, 0); 772 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 773 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 774 break; 775 776 default: /* unknown header */ 777 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", 778 pci_name(dev), dev->hdr_type); 779 return -1; 780 781 bad: 782 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", 783 pci_name(dev), class, dev->hdr_type); 784 dev->class = PCI_CLASS_NOT_DEFINED; 785 } 786 787 /* We found a fine healthy device, go go go... */ 788 return 0; 789} 790 791/** 792 * pci_release_dev - free a pci device structure when all users of it are finished. 793 * @dev: device that's been disconnected 794 * 795 * Will be called only by the device core when all users of this pci device are 796 * done. 797 */ 798static void pci_release_dev(struct device *dev) 799{ 800 struct pci_dev *pci_dev; 801 802 pci_dev = to_pci_dev(dev); 803 kfree(pci_dev); 804} 805 806/** 807 * pci_cfg_space_size - get the configuration space size of the PCI device. 808 * @dev: PCI device 809 * 810 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 811 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 812 * access it. Maybe we don't have a way to generate extended config space 813 * accesses, or the device is behind a reverse Express bridge. So we try 814 * reading the dword at 0x100 which must either be 0 or a valid extended 815 * capability header. 816 */ 817int pci_cfg_space_size(struct pci_dev *dev) 818{ 819 int pos; 820 u32 status; 821 822 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 823 if (!pos) { 824 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 825 if (!pos) 826 goto fail; 827 828 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 829 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) 830 goto fail; 831 } 832 833 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL) 834 goto fail; 835 if (status == 0xffffffff) 836 goto fail; 837 838 return PCI_CFG_SPACE_EXP_SIZE; 839 840 fail: 841 return PCI_CFG_SPACE_SIZE; 842} 843 844static void pci_release_bus_bridge_dev(struct device *dev) 845{ 846 kfree(dev); 847} 848 849struct pci_dev *alloc_pci_dev(void) 850{ 851 struct pci_dev *dev; 852 853 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 854 if (!dev) 855 return NULL; 856 857 INIT_LIST_HEAD(&dev->global_list); 858 INIT_LIST_HEAD(&dev->bus_list); 859 860 pci_msi_init_pci_dev(dev); 861 862 return dev; 863} 864EXPORT_SYMBOL(alloc_pci_dev); 865 866/* 867 * Read the config data for a PCI device, sanity-check it 868 * and fill in the dev structure... 869 */ 870static struct pci_dev * __devinit 871pci_scan_device(struct pci_bus *bus, int devfn) 872{ 873 struct pci_dev *dev; 874 u32 l; 875 u8 hdr_type; 876 int delay = 1; 877 878 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) 879 return NULL; 880 881 /* some broken boards return 0 or ~0 if a slot is empty: */ 882 if (l == 0xffffffff || l == 0x00000000 || 883 l == 0x0000ffff || l == 0xffff0000) 884 return NULL; 885 886 /* Configuration request Retry Status */ 887 while (l == 0xffff0001) { 888 msleep(delay); 889 delay *= 2; 890 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) 891 return NULL; 892 /* Card hasn't responded in 60 seconds? Must be stuck. */ 893 if (delay > 60 * 1000) { 894 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " 895 "responding\n", pci_domain_nr(bus), 896 bus->number, PCI_SLOT(devfn), 897 PCI_FUNC(devfn)); 898 return NULL; 899 } 900 } 901 902 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type)) 903 return NULL; 904 905 dev = alloc_pci_dev(); 906 if (!dev) 907 return NULL; 908 909 dev->bus = bus; 910 dev->sysdata = bus->sysdata; 911 dev->dev.parent = bus->bridge; 912 dev->dev.bus = &pci_bus_type; 913 dev->devfn = devfn; 914 dev->hdr_type = hdr_type & 0x7f; 915 dev->multifunction = !!(hdr_type & 0x80); 916 dev->vendor = l & 0xffff; 917 dev->device = (l >> 16) & 0xffff; 918 dev->cfg_size = pci_cfg_space_size(dev); 919 dev->error_state = pci_channel_io_normal; 920 921 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 922 set this higher, assuming the system even supports it. */ 923 dev->dma_mask = 0xffffffff; 924 if (pci_setup_device(dev) < 0) { 925 kfree(dev); 926 return NULL; 927 } 928 929 return dev; 930} 931 932void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 933{ 934 device_initialize(&dev->dev); 935 dev->dev.release = pci_release_dev; 936 pci_dev_get(dev); 937 938 set_dev_node(&dev->dev, pcibus_to_node(bus)); 939 dev->dev.dma_mask = &dev->dma_mask; 940 dev->dev.coherent_dma_mask = 0xffffffffull; 941 942 /* Fix up broken headers */ 943 pci_fixup_device(pci_fixup_header, dev); 944 945 /* 946 * Add the device to our list of discovered devices 947 * and the bus list for fixup functions, etc. 948 */ 949 INIT_LIST_HEAD(&dev->global_list); 950 down_write(&pci_bus_sem); 951 list_add_tail(&dev->bus_list, &bus->devices); 952 up_write(&pci_bus_sem); 953} 954 955struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 956{ 957 struct pci_dev *dev; 958 959 dev = pci_scan_device(bus, devfn); 960 if (!dev) 961 return NULL; 962 963 pci_device_add(dev, bus); 964 965 return dev; 966} 967 968/** 969 * pci_scan_slot - scan a PCI slot on a bus for devices. 970 * @bus: PCI bus to scan 971 * @devfn: slot number to scan (must have zero function.) 972 * 973 * Scan a PCI slot on the specified PCI bus for devices, adding 974 * discovered devices to the @bus->devices list. New devices 975 * will have an empty dev->global_list head. 976 */ 977int pci_scan_slot(struct pci_bus *bus, int devfn) 978{ 979 int func, nr = 0; 980 int scan_all_fns; 981 982 scan_all_fns = pcibios_scan_all_fns(bus, devfn); 983 984 for (func = 0; func < 8; func++, devfn++) { 985 struct pci_dev *dev; 986 987 dev = pci_scan_single_device(bus, devfn); 988 if (dev) { 989 nr++; 990 991 /* 992 * If this is a single function device, 993 * don't scan past the first function. 994 */ 995 if (!dev->multifunction) { 996 if (func > 0) { 997 dev->multifunction = 1; 998 } else { 999 break; 1000 } 1001 } 1002 } else { 1003 if (func == 0 && !scan_all_fns) 1004 break; 1005 } 1006 } 1007 return nr; 1008} 1009 1010unsigned int pci_scan_child_bus(struct pci_bus *bus) 1011{ 1012 unsigned int devfn, pass, max = bus->secondary; 1013 struct pci_dev *dev; 1014 1015 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number); 1016 1017 /* Go find them, Rover! */ 1018 for (devfn = 0; devfn < 0x100; devfn += 8) 1019 pci_scan_slot(bus, devfn); 1020 1021 /* 1022 * After performing arch-dependent fixup of the bus, look behind 1023 * all PCI-to-PCI bridges on this bus. 1024 */ 1025 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number); 1026 pcibios_fixup_bus(bus); 1027 for (pass=0; pass < 2; pass++) 1028 list_for_each_entry(dev, &bus->devices, bus_list) { 1029 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1030 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 1031 max = pci_scan_bridge(bus, dev, max, pass); 1032 } 1033 1034 /* 1035 * We've scanned the bus and so we know all about what's on 1036 * the other side of any bridges that may be on this bus plus 1037 * any devices. 1038 * 1039 * Return how far we've got finding sub-buses. 1040 */ 1041 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n", 1042 pci_domain_nr(bus), bus->number, max); 1043 return max; 1044} 1045 1046unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus) 1047{ 1048 unsigned int max; 1049 1050 max = pci_scan_child_bus(bus); 1051 1052 /* 1053 * Make the discovered devices available. 1054 */ 1055 pci_bus_add_devices(bus); 1056 1057 return max; 1058} 1059 1060struct pci_bus * pci_create_bus(struct device *parent, 1061 int bus, struct pci_ops *ops, void *sysdata) 1062{ 1063 int error; 1064 struct pci_bus *b; 1065 struct device *dev; 1066 1067 b = pci_alloc_bus(); 1068 if (!b) 1069 return NULL; 1070 1071 dev = kmalloc(sizeof(*dev), GFP_KERNEL); 1072 if (!dev){ 1073 kfree(b); 1074 return NULL; 1075 } 1076 1077 b->sysdata = sysdata; 1078 b->ops = ops; 1079 1080 if (pci_find_bus(pci_domain_nr(b), bus)) { 1081 /* If we already got to this bus through a different bridge, ignore it */ 1082 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus); 1083 goto err_out; 1084 } 1085 1086 down_write(&pci_bus_sem); 1087 list_add_tail(&b->node, &pci_root_buses); 1088 up_write(&pci_bus_sem); 1089 1090 memset(dev, 0, sizeof(*dev)); 1091 dev->parent = parent; 1092 dev->release = pci_release_bus_bridge_dev; 1093 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus); 1094 error = device_register(dev); 1095 if (error) 1096 goto dev_reg_err; 1097 b->bridge = get_device(dev); 1098 1099 b->class_dev.class = &pcibus_class; 1100 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus); 1101 error = class_device_register(&b->class_dev); 1102 if (error) 1103 goto class_dev_reg_err; 1104 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity); 1105 if (error) 1106 goto class_dev_create_file_err; 1107 1108 /* Create legacy_io and legacy_mem files for this bus */ 1109 pci_create_legacy_files(b); 1110 1111 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge"); 1112 if (error) 1113 goto sys_create_link_err; 1114 1115 b->number = b->secondary = bus; 1116 b->resource[0] = &ioport_resource; 1117 b->resource[1] = &iomem_resource; 1118 1119 return b; 1120 1121sys_create_link_err: 1122 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity); 1123class_dev_create_file_err: 1124 class_device_unregister(&b->class_dev); 1125class_dev_reg_err: 1126 device_unregister(dev); 1127dev_reg_err: 1128 down_write(&pci_bus_sem); 1129 list_del(&b->node); 1130 up_write(&pci_bus_sem); 1131err_out: 1132 kfree(dev); 1133 kfree(b); 1134 return NULL; 1135} 1136EXPORT_SYMBOL_GPL(pci_create_bus); 1137 1138struct pci_bus *pci_scan_bus_parented(struct device *parent, 1139 int bus, struct pci_ops *ops, void *sysdata) 1140{ 1141 struct pci_bus *b; 1142 1143 b = pci_create_bus(parent, bus, ops, sysdata); 1144 if (b) 1145 b->subordinate = pci_scan_child_bus(b); 1146 return b; 1147} 1148EXPORT_SYMBOL(pci_scan_bus_parented); 1149 1150#ifdef CONFIG_HOTPLUG 1151EXPORT_SYMBOL(pci_add_new_bus); 1152EXPORT_SYMBOL(pci_do_scan_bus); 1153EXPORT_SYMBOL(pci_scan_slot); 1154EXPORT_SYMBOL(pci_scan_bridge); 1155EXPORT_SYMBOL(pci_scan_single_device); 1156EXPORT_SYMBOL_GPL(pci_scan_child_bus); 1157#endif 1158 1159static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b) 1160{ 1161 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 1162 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 1163 1164 if (a->bus->number < b->bus->number) return -1; 1165 else if (a->bus->number > b->bus->number) return 1; 1166 1167 if (a->devfn < b->devfn) return -1; 1168 else if (a->devfn > b->devfn) return 1; 1169 1170 return 0; 1171} 1172 1173/* 1174 * Yes, this forcably breaks the klist abstraction temporarily. It 1175 * just wants to sort the klist, not change reference counts and 1176 * take/drop locks rapidly in the process. It does all this while 1177 * holding the lock for the list, so objects can't otherwise be 1178 * added/removed while we're swizzling. 1179 */ 1180static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list) 1181{ 1182 struct list_head *pos; 1183 struct klist_node *n; 1184 struct device *dev; 1185 struct pci_dev *b; 1186 1187 list_for_each(pos, list) { 1188 n = container_of(pos, struct klist_node, n_node); 1189 dev = container_of(n, struct device, knode_bus); 1190 b = to_pci_dev(dev); 1191 if (pci_sort_bf_cmp(a, b) <= 0) { 1192 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node); 1193 return; 1194 } 1195 } 1196 list_move_tail(&a->dev.knode_bus.n_node, list); 1197} 1198 1199static void __init pci_sort_breadthfirst_klist(void) 1200{ 1201 LIST_HEAD(sorted_devices); 1202 struct list_head *pos, *tmp; 1203 struct klist_node *n; 1204 struct device *dev; 1205 struct pci_dev *pdev; 1206 1207 spin_lock(&pci_bus_type.klist_devices.k_lock); 1208 list_for_each_safe(pos, tmp, &pci_bus_type.klist_devices.k_list) { 1209 n = container_of(pos, struct klist_node, n_node); 1210 dev = container_of(n, struct device, knode_bus); 1211 pdev = to_pci_dev(dev); 1212 pci_insertion_sort_klist(pdev, &sorted_devices); 1213 } 1214 list_splice(&sorted_devices, &pci_bus_type.klist_devices.k_list); 1215 spin_unlock(&pci_bus_type.klist_devices.k_lock); 1216} 1217 1218static void __init pci_insertion_sort_devices(struct pci_dev *a, struct list_head *list) 1219{ 1220 struct pci_dev *b; 1221 1222 list_for_each_entry(b, list, global_list) { 1223 if (pci_sort_bf_cmp(a, b) <= 0) { 1224 list_move_tail(&a->global_list, &b->global_list); 1225 return; 1226 } 1227 } 1228 list_move_tail(&a->global_list, list); 1229} 1230 1231static void __init pci_sort_breadthfirst_devices(void) 1232{ 1233 LIST_HEAD(sorted_devices); 1234 struct pci_dev *dev, *tmp; 1235 1236 down_write(&pci_bus_sem); 1237 list_for_each_entry_safe(dev, tmp, &pci_devices, global_list) { 1238 pci_insertion_sort_devices(dev, &sorted_devices); 1239 } 1240 list_splice(&sorted_devices, &pci_devices); 1241 up_write(&pci_bus_sem); 1242} 1243 1244void __init pci_sort_breadthfirst(void) 1245{ 1246 pci_sort_breadthfirst_devices(); 1247 pci_sort_breadthfirst_klist(); 1248} 1249