1
2
3#include <linux/delay.h>
4#include <linux/types.h>
5#include <linux/kernel.h>
6#include <linux/spinlock.h>
7#include <linux/init.h>		/* for __init and __devinit */
8#include <linux/pci.h>
9#include <linux/ioport.h>
10#include <linux/slab.h>
11
12#include <asm/byteorder.h>
13#include <asm/pdc.h>
14#include <asm/pdcpat.h>
15#include <asm/page.h>
16#include <asm/system.h>
17
18#include <asm/ropes.h>
19#include <asm/hardware.h>	/* for register_parisc_driver() stuff */
20#include <asm/parisc-device.h>
21#include <asm/io.h>		/* read/write stuff */
22
23#undef DEBUG_LBA	/* general stuff */
24#undef DEBUG_LBA_PORT	/* debug I/O Port access */
25#undef DEBUG_LBA_CFG	/* debug Config Space Access (ie PCI Bus walk) */
26#undef DEBUG_LBA_PAT	/* debug PCI Resource Mgt code - PDC PAT only */
27
28#undef FBB_SUPPORT	/* Fast Back-Back xfers - NOT READY YET */
29
30
31#ifdef DEBUG_LBA
32#define DBG(x...)	printk(x)
33#else
34#define DBG(x...)
35#endif
36
37#ifdef DEBUG_LBA_PORT
38#define DBG_PORT(x...)	printk(x)
39#else
40#define DBG_PORT(x...)
41#endif
42
43#ifdef DEBUG_LBA_CFG
44#define DBG_CFG(x...)	printk(x)
45#else
46#define DBG_CFG(x...)
47#endif
48
49#ifdef DEBUG_LBA_PAT
50#define DBG_PAT(x...)	printk(x)
51#else
52#define DBG_PAT(x...)
53#endif
54
55
56/*
57** Config accessor functions only pass in the 8-bit bus number and not
58** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
59** number based on what firmware wrote into the scratch register.
60**
61** The "secondary" bus number is set to this before calling
62** pci_register_ops(). If any PPB's are present, the scan will
63** discover them and update the "secondary" and "subordinate"
64** fields in the pci_bus structure.
65**
66** Changes in the configuration *may* result in a different
67** bus number for each LBA depending on what firmware does.
68*/
69
70#define MODULE_NAME "LBA"
71
72/* non-postable I/O port space, densely packed */
73#define LBA_PORT_BASE	(PCI_F_EXTEND | 0xfee00000UL)
74static void __iomem *astro_iop_base __read_mostly;
75
76static u32 lba_t32;
77
78/* lba flags */
79#define LBA_FLAG_SKIP_PROBE	0x10
80
81#define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
82
83
84/* Looks nice and keeps the compiler happy */
85#define LBA_DEV(d) ((struct lba_device *) (d))
86
87
88/*
89** Only allow 8 subsidiary busses per LBA
90** Problem is the PCI bus numbering is globally shared.
91*/
92#define LBA_MAX_NUM_BUSES 8
93
94/************************************
95 * LBA register read and write support
96 *
97 * BE WARNED: register writes are posted.
98 *  (ie follow writes which must reach HW with a read)
99 */
100#define READ_U8(addr)  __raw_readb(addr)
101#define READ_U16(addr) __raw_readw(addr)
102#define READ_U32(addr) __raw_readl(addr)
103#define WRITE_U8(value, addr)  __raw_writeb(value, addr)
104#define WRITE_U16(value, addr) __raw_writew(value, addr)
105#define WRITE_U32(value, addr) __raw_writel(value, addr)
106
107#define READ_REG8(addr)  readb(addr)
108#define READ_REG16(addr) readw(addr)
109#define READ_REG32(addr) readl(addr)
110#define READ_REG64(addr) readq(addr)
111#define WRITE_REG8(value, addr)  writeb(value, addr)
112#define WRITE_REG16(value, addr) writew(value, addr)
113#define WRITE_REG32(value, addr) writel(value, addr)
114
115
116#define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
117#define LBA_CFG_BUS(tok)  ((u8) ((tok)>>16))
118#define LBA_CFG_DEV(tok)  ((u8) ((tok)>>11) & 0x1f)
119#define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
120
121
122/*
123** Extract LBA (Rope) number from HPA
124** REVISIT: 16 ropes for Stretch/Ike?
125*/
126#define ROPES_PER_IOC	8
127#define LBA_NUM(x)    ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
128
129
130static void
131lba_dump_res(struct resource *r, int d)
132{
133	int i;
134
135	if (NULL == r)
136		return;
137
138	printk(KERN_DEBUG "(%p)", r->parent);
139	for (i = d; i ; --i) printk(" ");
140	printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r,
141		(long)r->start, (long)r->end, r->flags);
142	lba_dump_res(r->child, d+2);
143	lba_dump_res(r->sibling, d);
144}
145
146
147
148static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d)
149{
150	u8 first_bus = d->hba.hba_bus->secondary;
151	u8 last_sub_bus = d->hba.hba_bus->subordinate;
152
153	if ((bus < first_bus) ||
154	    (bus > last_sub_bus) ||
155	    ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) {
156		return 0;
157	}
158
159	return 1;
160}
161
162
163
164#define LBA_CFG_SETUP(d, tok) {				\
165    /* Save contents of error config register.  */			\
166    error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);		\
167\
168    /* Save contents of status control register.  */			\
169    status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);		\
170\
171    /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA		\
172    ** arbitration for full bus walks.					\
173    */									\
174	/* Save contents of arb mask register. */			\
175	arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK);		\
176\
177	/*								\
178	 * Turn off all device arbitration bits (i.e. everything	\
179	 * except arbitration enable bit).				\
180	 */								\
181	WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK);		\
182\
183    /*									\
184     * Set the smart mode bit so that master aborts don't cause		\
185     * LBA to go into PCI fatal mode (required).			\
186     */									\
187    WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG);	\
188}
189
190
191#define LBA_CFG_PROBE(d, tok) {				\
192    /*									\
193     * Setup Vendor ID write and read back the address register		\
194     * to make sure that LBA is the bus master.				\
195     */									\
196    WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
197    /*									\
198     * Read address register to ensure that LBA is the bus master,	\
199     * which implies that DMA traffic has stopped when DMA arb is off.	\
200     */									\
201    lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
202    /*									\
203     * Generate a cfg write cycle (will have no affect on		\
204     * Vendor ID register since read-only).				\
205     */									\
206    WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA);		\
207    /*									\
208     * Make sure write has completed before proceeding further,		\
209     * i.e. before setting clear enable.				\
210     */									\
211    lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
212}
213
214
215/*
216 * HPREVISIT:
217 *   -- Can't tell if config cycle got the error.
218 *
219 *		OV bit is broken until rev 4.0, so can't use OV bit and
220 *		LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
221 *
222 *		As of rev 4.0, no longer need the error check.
223 *
224 *   -- Even if we could tell, we still want to return -1
225 *	for **ANY** error (not just master abort).
226 *
227 *   -- Only clear non-fatal errors (we don't want to bring
228 *	LBA out of pci-fatal mode).
229 *
230 *		Actually, there is still a race in which
231 *		we could be clearing a fatal error.  We will
232 *		live with this during our initial bus walk
233 *		until rev 4.0 (no driver activity during
234 *		initial bus walk).  The initial bus walk
235 *		has race conditions concerning the use of
236 *		smart mode as well.
237 */
238
239#define LBA_MASTER_ABORT_ERROR 0xc
240#define LBA_FATAL_ERROR 0x10
241
242#define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) {		\
243    u32 error_status = 0;						\
244    /*									\
245     * Set clear enable (CE) bit. Unset by HW when new			\
246     * errors are logged -- LBA HW ERS section 14.3.3).		\
247     */									\
248    WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
249    error_status = READ_REG32(base + LBA_ERROR_STATUS);		\
250    if ((error_status & 0x1f) != 0) {					\
251	/*								\
252	 * Fail the config read request.				\
253	 */								\
254	error = 1;							\
255	if ((error_status & LBA_FATAL_ERROR) == 0) {			\
256	    /*								\
257	     * Clear error status (if fatal bit not set) by setting	\
258	     * clear error log bit (CL).				\
259	     */								\
260	    WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
261	}								\
262    }									\
263}
264
265#define LBA_CFG_TR4_ADDR_SETUP(d, addr)					\
266	WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
267
268#define LBA_CFG_ADDR_SETUP(d, addr) {					\
269    WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
270    /*									\
271     * Read address register to ensure that LBA is the bus master,	\
272     * which implies that DMA traffic has stopped when DMA arb is off.	\
273     */									\
274    lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
275}
276
277
278#define LBA_CFG_RESTORE(d, base) {					\
279    /*									\
280     * Restore status control register (turn off clear enable).		\
281     */									\
282    WRITE_REG32(status_control, base + LBA_STAT_CTL);			\
283    /*									\
284     * Restore error config register (turn off smart mode).		\
285     */									\
286    WRITE_REG32(error_config, base + LBA_ERROR_CONFIG);			\
287	/*								\
288	 * Restore arb mask register (reenables DMA arbitration).	\
289	 */								\
290	WRITE_REG32(arb_mask, base + LBA_ARB_MASK);			\
291}
292
293
294
295static unsigned int
296lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
297{
298	u32 data = ~0U;
299	int error = 0;
300	u32 arb_mask = 0;	/* used by LBA_CFG_SETUP/RESTORE */
301	u32 error_config = 0;	/* used by LBA_CFG_SETUP/RESTORE */
302	u32 status_control = 0;	/* used by LBA_CFG_SETUP/RESTORE */
303
304	LBA_CFG_SETUP(d, tok);
305	LBA_CFG_PROBE(d, tok);
306	LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
307	if (!error) {
308		void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
309
310		LBA_CFG_ADDR_SETUP(d, tok | reg);
311		switch (size) {
312		case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break;
313		case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break;
314		case 4: data = READ_REG32(data_reg); break;
315		}
316	}
317	LBA_CFG_RESTORE(d, d->hba.base_addr);
318	return(data);
319}
320
321
322static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
323{
324	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
325	u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
326	u32 tok = LBA_CFG_TOK(local_bus, devfn);
327	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
328
329	if ((pos > 255) || (devfn > 255))
330		return -EINVAL;
331
332	/* if (!LBA_SKIP_PROBE(d)) */ {
333		/* original - Generate config cycle on broken elroy
334		  with risk we will miss PCI bus errors. */
335		*data = lba_rd_cfg(d, tok, pos, size);
336		DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__, tok, pos, *data);
337		return 0;
338	}
339
340	if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->secondary, devfn, d)) {
341		DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__, tok, pos);
342		/* either don't want to look or know device isn't present. */
343		*data = ~0U;
344		return(0);
345	}
346
347	/* Basic Algorithm
348	** Should only get here on fully working LBA rev.
349	** This is how simple the code should have been.
350	*/
351	LBA_CFG_ADDR_SETUP(d, tok | pos);
352	switch(size) {
353	case 1: *data = READ_REG8 (data_reg + (pos & 3)); break;
354	case 2: *data = READ_REG16(data_reg + (pos & 2)); break;
355	case 4: *data = READ_REG32(data_reg); break;
356	}
357	DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data);
358	return 0;
359}
360
361
362static void
363lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
364{
365	int error = 0;
366	u32 arb_mask = 0;
367	u32 error_config = 0;
368	u32 status_control = 0;
369	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
370
371	LBA_CFG_SETUP(d, tok);
372	LBA_CFG_ADDR_SETUP(d, tok | reg);
373	switch (size) {
374	case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break;
375	case 2: WRITE_REG16(data, data_reg + (reg & 2)); break;
376	case 4: WRITE_REG32(data, data_reg);             break;
377	}
378	LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
379	LBA_CFG_RESTORE(d, d->hba.base_addr);
380}
381
382
383/*
384 * LBA 4.0 config write code implements non-postable semantics
385 * by doing a read of CONFIG ADDR after the write.
386 */
387
388static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
389{
390	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
391	u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
392	u32 tok = LBA_CFG_TOK(local_bus,devfn);
393
394	if ((pos > 255) || (devfn > 255))
395		return -EINVAL;
396
397	if (!LBA_SKIP_PROBE(d)) {
398		lba_wr_cfg(d, tok, pos, (u32) data, size);
399		DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__, tok, pos,data);
400		return 0;
401	}
402
403	if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) {
404		DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__, tok, pos,data);
405		return 1;
406	}
407
408	DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data);
409
410	/* Basic Algorithm */
411	LBA_CFG_ADDR_SETUP(d, tok | pos);
412	switch(size) {
413	case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
414		   break;
415	case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
416		   break;
417	case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
418		   break;
419	}
420	/* flush posted write */
421	lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
422	return 0;
423}
424
425
426static struct pci_ops elroy_cfg_ops = {
427	.read =		elroy_cfg_read,
428	.write =	elroy_cfg_write,
429};
430
431/*
432 * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy
433 * TR4.0 as no additional bugs were found in this areea between Elroy and
434 * Mercury
435 */
436
437static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
438{
439	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
440	u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
441	u32 tok = LBA_CFG_TOK(local_bus, devfn);
442	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
443
444	if ((pos > 255) || (devfn > 255))
445		return -EINVAL;
446
447	LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
448	switch(size) {
449	case 1:
450		*data = READ_REG8(data_reg + (pos & 3));
451		break;
452	case 2:
453		*data = READ_REG16(data_reg + (pos & 2));
454		break;
455	case 4:
456		*data = READ_REG32(data_reg);             break;
457		break;
458	}
459
460	DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data);
461	return 0;
462}
463
464/*
465 * LBA 4.0 config write code implements non-postable semantics
466 * by doing a read of CONFIG ADDR after the write.
467 */
468
469static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
470{
471	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
472	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
473	u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
474	u32 tok = LBA_CFG_TOK(local_bus,devfn);
475
476	if ((pos > 255) || (devfn > 255))
477		return -EINVAL;
478
479	DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __FUNCTION__, tok, pos, data);
480
481	LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
482	switch(size) {
483	case 1:
484		WRITE_REG8 (data, data_reg + (pos & 3));
485		break;
486	case 2:
487		WRITE_REG16(data, data_reg + (pos & 2));
488		break;
489	case 4:
490		WRITE_REG32(data, data_reg);
491		break;
492	}
493
494	/* flush posted write */
495	lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
496	return 0;
497}
498
499static struct pci_ops mercury_cfg_ops = {
500	.read =		mercury_cfg_read,
501	.write =	mercury_cfg_write,
502};
503
504
505static void
506lba_bios_init(void)
507{
508	DBG(MODULE_NAME ": lba_bios_init\n");
509}
510
511
512#ifdef CONFIG_64BIT
513
514/*
515** Determine if a device is already configured.
516** If so, reserve it resources.
517**
518** Read PCI cfg command register and see if I/O or MMIO is enabled.
519** PAT has to enable the devices it's using.
520**
521** Note: resources are fixed up before we try to claim them.
522*/
523static void
524lba_claim_dev_resources(struct pci_dev *dev)
525{
526	u16 cmd;
527	int i, srch_flags;
528
529	(void) pci_read_config_word(dev, PCI_COMMAND, &cmd);
530
531	srch_flags  = (cmd & PCI_COMMAND_IO) ? IORESOURCE_IO : 0;
532	if (cmd & PCI_COMMAND_MEMORY)
533		srch_flags |= IORESOURCE_MEM;
534
535	if (!srch_flags)
536		return;
537
538	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
539		if (dev->resource[i].flags & srch_flags) {
540			pci_claim_resource(dev, i);
541			DBG("   claimed %s %d [%lx,%lx]/%lx\n",
542				pci_name(dev), i,
543				dev->resource[i].start,
544				dev->resource[i].end,
545				dev->resource[i].flags
546				);
547		}
548	}
549}
550
551
552static unsigned long
553truncate_pat_collision(struct resource *root, struct resource *new)
554{
555	unsigned long start = new->start;
556	unsigned long end = new->end;
557	struct resource *tmp = root->child;
558
559	if (end <= start || start < root->start || !tmp)
560		return 0;
561
562	/* find first overlap */
563	while (tmp && tmp->end < start)
564		tmp = tmp->sibling;
565
566	/* no entries overlap */
567	if (!tmp)  return 0;
568
569	/* found one that starts behind the new one
570	** Don't need to do anything.
571	*/
572	if (tmp->start >= end) return 0;
573
574	if (tmp->start <= start) {
575		/* "front" of new one overlaps */
576		new->start = tmp->end + 1;
577
578		if (tmp->end >= end) {
579			/* AACCKK! totally overlaps! drop this range. */
580			return 1;
581		}
582	}
583
584	if (tmp->end < end ) {
585		/* "end" of new one overlaps */
586		new->end = tmp->start - 1;
587	}
588
589	printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] "
590					"to [%lx,%lx]\n",
591			start, end,
592			(long)new->start, (long)new->end );
593
594	return 0;	/* truncation successful */
595}
596
597#else
598#define lba_claim_dev_resources(dev) do { } while (0)
599#define truncate_pat_collision(r,n)  (0)
600#endif
601
602/*
603** The algorithm is generic code.
604** But it needs to access local data structures to get the IRQ base.
605** Could make this a "pci_fixup_irq(bus, region)" but not sure
606** it's worth it.
607**
608** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
609** Resources aren't allocated until recursive buswalk below HBA is completed.
610*/
611static void
612lba_fixup_bus(struct pci_bus *bus)
613{
614	struct list_head *ln;
615#ifdef FBB_SUPPORT
616	u16 status;
617#endif
618	struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
619	int lba_portbase = HBA_PORT_BASE(ldev->hba.hba_num);
620
621	DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n",
622		bus, bus->secondary, bus->bridge->platform_data);
623
624	/*
625	** Properly Setup MMIO resources for this bus.
626	** pci_alloc_primary_bus() mangles this.
627	*/
628	if (bus->self) {
629		/* PCI-PCI Bridge */
630		pci_read_bridge_bases(bus);
631	} else {
632		/* Host-PCI Bridge */
633		int err, i;
634
635		DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
636			ldev->hba.io_space.name,
637			ldev->hba.io_space.start, ldev->hba.io_space.end,
638			ldev->hba.io_space.flags);
639		DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
640			ldev->hba.lmmio_space.name,
641			ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
642			ldev->hba.lmmio_space.flags);
643
644		err = request_resource(&ioport_resource, &(ldev->hba.io_space));
645		if (err < 0) {
646			lba_dump_res(&ioport_resource, 2);
647			BUG();
648		}
649		/* advertize Host bridge resources to PCI bus */
650		bus->resource[0] = &(ldev->hba.io_space);
651		i = 1;
652
653		if (ldev->hba.elmmio_space.start) {
654			err = request_resource(&iomem_resource,
655					&(ldev->hba.elmmio_space));
656			if (err < 0) {
657
658				printk("FAILED: lba_fixup_bus() request for "
659						"elmmio_space [%lx/%lx]\n",
660						(long)ldev->hba.elmmio_space.start,
661						(long)ldev->hba.elmmio_space.end);
662
663				/* lba_dump_res(&iomem_resource, 2); */
664				/* BUG(); */
665			} else
666				bus->resource[i++] = &(ldev->hba.elmmio_space);
667		}
668
669
670		if (truncate_pat_collision(&iomem_resource,
671				       	&(ldev->hba.lmmio_space))) {
672
673			printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n",
674					(long)ldev->hba.lmmio_space.start,
675					(long)ldev->hba.lmmio_space.end);
676		} else {
677			err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
678			if (err < 0) {
679				printk(KERN_ERR "FAILED: lba_fixup_bus() request for "
680					"lmmio_space [%lx/%lx]\n",
681					(long)ldev->hba.lmmio_space.start,
682					(long)ldev->hba.lmmio_space.end);
683			} else
684				bus->resource[i++] = &(ldev->hba.lmmio_space);
685		}
686
687#ifdef CONFIG_64BIT
688		/* GMMIO is  distributed range. Every LBA/Rope gets part it. */
689		if (ldev->hba.gmmio_space.flags) {
690			err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
691			if (err < 0) {
692				printk("FAILED: lba_fixup_bus() request for "
693					"gmmio_space [%lx/%lx]\n",
694					(long)ldev->hba.gmmio_space.start,
695					(long)ldev->hba.gmmio_space.end);
696				lba_dump_res(&iomem_resource, 2);
697				BUG();
698			}
699			bus->resource[i++] = &(ldev->hba.gmmio_space);
700		}
701#endif
702
703	}
704
705	list_for_each(ln, &bus->devices) {
706		int i;
707		struct pci_dev *dev = pci_dev_b(ln);
708
709		DBG("lba_fixup_bus() %s\n", pci_name(dev));
710
711		/* Virtualize Device/Bridge Resources. */
712		for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
713			struct resource *res = &dev->resource[i];
714
715			/* If resource not allocated - skip it */
716			if (!res->start)
717				continue;
718
719			if (res->flags & IORESOURCE_IO) {
720				DBG("lba_fixup_bus() I/O Ports [%lx/%lx] -> ",
721					res->start, res->end);
722				res->start |= lba_portbase;
723				res->end   |= lba_portbase;
724				DBG("[%lx/%lx]\n", res->start, res->end);
725			} else if (res->flags & IORESOURCE_MEM) {
726				/*
727				** Convert PCI (IO_VIEW) addresses to
728				** processor (PA_VIEW) addresses
729				 */
730				DBG("lba_fixup_bus() MMIO [%lx/%lx] -> ",
731					res->start, res->end);
732				res->start = PCI_HOST_ADDR(HBA_DATA(ldev), res->start);
733				res->end   = PCI_HOST_ADDR(HBA_DATA(ldev), res->end);
734				DBG("[%lx/%lx]\n", res->start, res->end);
735			} else {
736				DBG("lba_fixup_bus() WTF? 0x%lx [%lx/%lx] XXX",
737					res->flags, res->start, res->end);
738			}
739		}
740
741#ifdef FBB_SUPPORT
742		/*
743		** If one device does not support FBB transfers,
744		** No one on the bus can be allowed to use them.
745		*/
746		(void) pci_read_config_word(dev, PCI_STATUS, &status);
747		bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
748#endif
749
750		if (is_pdc_pat()) {
751			/* Claim resources for PDC's devices */
752			lba_claim_dev_resources(dev);
753		}
754
755                /*
756		** P2PB's have no IRQs. ignore them.
757		*/
758		if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
759			continue;
760
761		/* Adjust INTERRUPT_LINE for this dev */
762		iosapic_fixup_irq(ldev->iosapic_obj, dev);
763	}
764
765#ifdef FBB_SUPPORT
766	if (fbb_enable) {
767		if (bus->self) {
768			u8 control;
769			/* enable on PPB */
770			(void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
771			(void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
772
773		} else {
774			/* enable on LBA */
775		}
776		fbb_enable = PCI_COMMAND_FAST_BACK;
777	}
778
779	/* Lastly enable FBB/PERR/SERR on all devices too */
780	list_for_each(ln, &bus->devices) {
781		(void) pci_read_config_word(dev, PCI_COMMAND, &status);
782		status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
783		(void) pci_write_config_word(dev, PCI_COMMAND, status);
784	}
785#endif
786}
787
788
789struct pci_bios_ops lba_bios_ops = {
790	.init =		lba_bios_init,
791	.fixup_bus =	lba_fixup_bus,
792};
793
794
795
796
797/*******************************************************
798**
799** LBA Sprockets "I/O Port" Space Accessor Functions
800**
801** This set of accessor functions is intended for use with
802** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
803**
804** Many PCI devices don't require use of I/O port space (eg Tulip,
805** NCR720) since they export the same registers to both MMIO and
806** I/O port space. In general I/O port space is slower than
807** MMIO since drivers are designed so PIO writes can be posted.
808**
809********************************************************/
810
811#define LBA_PORT_IN(size, mask) \
812static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
813{ \
814	u##size t; \
815	t = READ_REG##size(astro_iop_base + addr); \
816	DBG_PORT(" 0x%x\n", t); \
817	return (t); \
818}
819
820LBA_PORT_IN( 8, 3)
821LBA_PORT_IN(16, 2)
822LBA_PORT_IN(32, 0)
823
824
825
826#define LBA_PORT_OUT(size, mask) \
827static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
828{ \
829	DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \
830	WRITE_REG##size(val, astro_iop_base + addr); \
831	if (LBA_DEV(d)->hw_rev < 3) \
832		lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
833}
834
835LBA_PORT_OUT( 8, 3)
836LBA_PORT_OUT(16, 2)
837LBA_PORT_OUT(32, 0)
838
839
840static struct pci_port_ops lba_astro_port_ops = {
841	.inb =	lba_astro_in8,
842	.inw =	lba_astro_in16,
843	.inl =	lba_astro_in32,
844	.outb =	lba_astro_out8,
845	.outw =	lba_astro_out16,
846	.outl =	lba_astro_out32
847};
848
849
850#ifdef CONFIG_64BIT
851#define PIOP_TO_GMMIO(lba, addr) \
852	((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
853
854/*******************************************************
855**
856** LBA PAT "I/O Port" Space Accessor Functions
857**
858** This set of accessor functions is intended for use with
859** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
860**
861** This uses the PIOP space located in the first 64MB of GMMIO.
862** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
863** bits 1:0 stay the same.  bits 15:2 become 25:12.
864** Then add the base and we can generate an I/O Port cycle.
865********************************************************/
866#undef LBA_PORT_IN
867#define LBA_PORT_IN(size, mask) \
868static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
869{ \
870	u##size t; \
871	DBG_PORT("%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \
872	t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
873	DBG_PORT(" 0x%x\n", t); \
874	return (t); \
875}
876
877LBA_PORT_IN( 8, 3)
878LBA_PORT_IN(16, 2)
879LBA_PORT_IN(32, 0)
880
881
882#undef LBA_PORT_OUT
883#define LBA_PORT_OUT(size, mask) \
884static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
885{ \
886	void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \
887	DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \
888	WRITE_REG##size(val, where); \
889	/* flush the I/O down to the elroy at least */ \
890	lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
891}
892
893LBA_PORT_OUT( 8, 3)
894LBA_PORT_OUT(16, 2)
895LBA_PORT_OUT(32, 0)
896
897
898static struct pci_port_ops lba_pat_port_ops = {
899	.inb =	lba_pat_in8,
900	.inw =	lba_pat_in16,
901	.inl =	lba_pat_in32,
902	.outb =	lba_pat_out8,
903	.outw =	lba_pat_out16,
904	.outl =	lba_pat_out32
905};
906
907
908
909/*
910** make range information from PDC available to PCI subsystem.
911** We make the PDC call here in order to get the PCI bus range
912** numbers. The rest will get forwarded in pcibios_fixup_bus().
913** We don't have a struct pci_bus assigned to us yet.
914*/
915static void
916lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
917{
918	unsigned long bytecnt;
919	pdc_pat_cell_mod_maddr_block_t pa_pdc_cell;	/* PA_VIEW */
920	pdc_pat_cell_mod_maddr_block_t io_pdc_cell;	/* IO_VIEW */
921	long io_count;
922	long status;	/* PDC return status */
923	long pa_count;
924	int i;
925
926	/* return cell module (IO view) */
927	status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
928				PA_VIEW, & pa_pdc_cell);
929	pa_count = pa_pdc_cell.mod[1];
930
931	status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
932				IO_VIEW, &io_pdc_cell);
933	io_count = io_pdc_cell.mod[1];
934
935	/* We've already done this once for device discovery...*/
936	if (status != PDC_OK) {
937		panic("pdc_pat_cell_module() call failed for LBA!\n");
938	}
939
940	if (PAT_GET_ENTITY(pa_pdc_cell.mod_info) != PAT_ENTITY_LBA) {
941		panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
942	}
943
944	/*
945	** Inspect the resources PAT tells us about
946	*/
947	for (i = 0; i < pa_count; i++) {
948		struct {
949			unsigned long type;
950			unsigned long start;
951			unsigned long end;	/* aka finish */
952		} *p, *io;
953		struct resource *r;
954
955		p = (void *) &(pa_pdc_cell.mod[2+i*3]);
956		io = (void *) &(io_pdc_cell.mod[2+i*3]);
957
958		/* Convert the PAT range data to PCI "struct resource" */
959		switch(p->type & 0xff) {
960		case PAT_PBNUM:
961			lba_dev->hba.bus_num.start = p->start;
962			lba_dev->hba.bus_num.end   = p->end;
963			break;
964
965		case PAT_LMMIO:
966			/* used to fix up pre-initialized MEM BARs */
967			if (!lba_dev->hba.lmmio_space.start) {
968				sprintf(lba_dev->hba.lmmio_name,
969						"PCI%02x LMMIO",
970						(int)lba_dev->hba.bus_num.start);
971				lba_dev->hba.lmmio_space_offset = p->start -
972					io->start;
973				r = &lba_dev->hba.lmmio_space;
974				r->name = lba_dev->hba.lmmio_name;
975			} else if (!lba_dev->hba.elmmio_space.start) {
976				sprintf(lba_dev->hba.elmmio_name,
977						"PCI%02x ELMMIO",
978						(int)lba_dev->hba.bus_num.start);
979				r = &lba_dev->hba.elmmio_space;
980				r->name = lba_dev->hba.elmmio_name;
981			} else {
982				printk(KERN_WARNING MODULE_NAME
983					" only supports 2 LMMIO resources!\n");
984				break;
985			}
986
987			r->start  = p->start;
988			r->end    = p->end;
989			r->flags  = IORESOURCE_MEM;
990			r->parent = r->sibling = r->child = NULL;
991			break;
992
993		case PAT_GMMIO:
994			/* MMIO space > 4GB phys addr; for 64-bit BAR */
995			sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO",
996					(int)lba_dev->hba.bus_num.start);
997			r = &lba_dev->hba.gmmio_space;
998			r->name  = lba_dev->hba.gmmio_name;
999			r->start  = p->start;
1000			r->end    = p->end;
1001			r->flags  = IORESOURCE_MEM;
1002			r->parent = r->sibling = r->child = NULL;
1003			break;
1004
1005		case PAT_NPIOP:
1006			printk(KERN_WARNING MODULE_NAME
1007				" range[%d] : ignoring NPIOP (0x%lx)\n",
1008				i, p->start);
1009			break;
1010
1011		case PAT_PIOP:
1012			/*
1013			** Postable I/O port space is per PCI host adapter.
1014			** base of 64MB PIOP region
1015			*/
1016			lba_dev->iop_base = ioremap_nocache(p->start, 64 * 1024 * 1024);
1017
1018			sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1019					(int)lba_dev->hba.bus_num.start);
1020			r = &lba_dev->hba.io_space;
1021			r->name  = lba_dev->hba.io_name;
1022			r->start  = HBA_PORT_BASE(lba_dev->hba.hba_num);
1023			r->end    = r->start + HBA_PORT_SPACE_SIZE - 1;
1024			r->flags  = IORESOURCE_IO;
1025			r->parent = r->sibling = r->child = NULL;
1026			break;
1027
1028		default:
1029			printk(KERN_WARNING MODULE_NAME
1030				" range[%d] : unknown pat range type (0x%lx)\n",
1031				i, p->type & 0xff);
1032			break;
1033		}
1034	}
1035}
1036#else
1037/* keep compiler from complaining about missing declarations */
1038#define lba_pat_port_ops lba_astro_port_ops
1039#define lba_pat_resources(pa_dev, lba_dev)
1040#endif	/* CONFIG_64BIT */
1041
1042
1043extern void sba_distributed_lmmio(struct parisc_device *, struct resource *);
1044extern void sba_directed_lmmio(struct parisc_device *, struct resource *);
1045
1046
1047static void
1048lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1049{
1050	struct resource *r;
1051	int lba_num;
1052
1053	lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
1054
1055	lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH);
1056	r = &(lba_dev->hba.bus_num);
1057	r->name = "LBA PCI Busses";
1058	r->start = lba_num & 0xff;
1059	r->end = (lba_num>>8) & 0xff;
1060
1061	/* Set up local PCI Bus resources - we don't need them for
1062	** Legacy boxes but it's nice to see in /proc/iomem.
1063	*/
1064	r = &(lba_dev->hba.lmmio_space);
1065	sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO",
1066					(int)lba_dev->hba.bus_num.start);
1067	r->name  = lba_dev->hba.lmmio_name;
1068
1069	/* We want the CPU -> IO routing of addresses.
1070	 * The SBA BASE/MASK registers control CPU -> IO routing.
1071	 * Ask SBA what is routed to this rope/LBA.
1072	 */
1073	sba_distributed_lmmio(pa_dev, r);
1074
1075	/*
1076	** "Directed" ranges are used when the "distributed range" isn't
1077	** sufficient for all devices below a given LBA.  Typically devices
1078	** like graphics cards or X25 may need a directed range when the
1079	** bus has multiple slots (ie multiple devices) or the device
1080	** needs more than the typical 4 or 8MB a distributed range offers.
1081	**
1082	** The main reason for ignoring it now frigging complications.
1083	** Directed ranges may overlap (and have precedence) over
1084	** distributed ranges. Or a distributed range assigned to a unused
1085	** rope may be used by a directed range on a different rope.
1086	** Support for graphics devices may require fixing this
1087	** since they may be assigned a directed range which overlaps
1088	** an existing (but unused portion of) distributed range.
1089	*/
1090	r = &(lba_dev->hba.elmmio_space);
1091	sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO",
1092					(int)lba_dev->hba.bus_num.start);
1093	r->name  = lba_dev->hba.elmmio_name;
1094
1095	/* See comment which precedes call to sba_directed_lmmio() */
1096	sba_directed_lmmio(pa_dev, r);
1097
1098	r = &(lba_dev->hba.io_space);
1099	sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1100					(int)lba_dev->hba.bus_num.start);
1101	r->name  = lba_dev->hba.io_name;
1102	r->flags = IORESOURCE_IO;
1103	r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L;
1104	r->end   = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1105
1106	/* Virtualize the I/O Port space ranges */
1107	lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
1108	r->start |= lba_num;
1109	r->end   |= lba_num;
1110}
1111
1112
1113
1114static int __init
1115lba_hw_init(struct lba_device *d)
1116{
1117	u32 stat;
1118	u32 bus_reset;	/* PDC_PAT_BUG */
1119
1120
1121#ifdef CONFIG_64BIT
1122#endif
1123
1124	/* PDC_PAT_BUG: exhibited in rev 40.48  on L2000 */
1125	bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1126	if (bus_reset) {
1127		printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n");
1128	}
1129
1130	stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1131	if (stat & LBA_SMART_MODE) {
1132		printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n");
1133		stat &= ~LBA_SMART_MODE;
1134		WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
1135	}
1136
1137	/* Set HF mode as the default (vs. -1 mode). */
1138        stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1139	WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1140
1141	/*
1142	** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
1143	** if it's not already set. If we just cleared the PCI Bus Reset
1144	** signal, wait a bit for the PCI devices to recover and setup.
1145	*/
1146	if (bus_reset)
1147		mdelay(pci_post_reset_delay);
1148
1149	if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1150		/*
1151		** PDC_PAT_BUG: PDC rev 40.48 on L2000.
1152		** B2000/C3600/J6000 also have this problem?
1153		**
1154		** Elroys with hot pluggable slots don't get configured
1155		** correctly if the slot is empty.  ARB_MASK is set to 0
1156		** and we can't master transactions on the bus if it's
1157		** not at least one. 0x3 enables elroy and first slot.
1158		*/
1159		printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n");
1160		WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
1161	}
1162
1163	return 0;
1164}
1165
1166/*
1167 * Unfortunately, when firmware numbers busses, it doesn't take into account
1168 * Cardbus bridges.  So we have to renumber the busses to suit ourselves.
1169 * Elroy/Mercury don't actually know what bus number they're attached to;
1170 * we use bus 0 to indicate the directly attached bus and any other bus
1171 * number will be taken care of by the PCI-PCI bridge.
1172 */
1173static unsigned int lba_next_bus = 0;
1174
1175/*
1176 * Determine if lba should claim this chip (return 0) or not (return 1).
1177 * If so, initialize the chip and tell other partners in crime they
1178 * have work to do.
1179 */
1180static int __init
1181lba_driver_probe(struct parisc_device *dev)
1182{
1183	struct lba_device *lba_dev;
1184	struct pci_bus *lba_bus;
1185	struct pci_ops *cfg_ops;
1186	u32 func_class;
1187	void *tmp_obj;
1188	char *version;
1189	void __iomem *addr = ioremap_nocache(dev->hpa.start, 4096);
1190
1191	/* Read HW Rev First */
1192	func_class = READ_REG32(addr + LBA_FCLASS);
1193
1194	if (IS_ELROY(dev)) {
1195		func_class &= 0xf;
1196		switch (func_class) {
1197		case 0:	version = "TR1.0"; break;
1198		case 1:	version = "TR2.0"; break;
1199		case 2:	version = "TR2.1"; break;
1200		case 3:	version = "TR2.2"; break;
1201		case 4:	version = "TR3.0"; break;
1202		case 5:	version = "TR4.0"; break;
1203		default: version = "TR4+";
1204		}
1205
1206		printk(KERN_INFO "Elroy version %s (0x%x) found at 0x%lx\n",
1207		       version, func_class & 0xf, (long)dev->hpa.start);
1208
1209		if (func_class < 2) {
1210			printk(KERN_WARNING "Can't support LBA older than "
1211				"TR2.1 - continuing under adversity.\n");
1212		}
1213
1214		{
1215			cfg_ops = &elroy_cfg_ops;
1216		}
1217
1218	} else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) {
1219		int major, minor;
1220
1221		func_class &= 0xff;
1222		major = func_class >> 4, minor = func_class & 0xf;
1223
1224		/* We could use one printk for both Elroy and Mercury,
1225                 * but for the mask for func_class.
1226                 */
1227		printk(KERN_INFO "%s version TR%d.%d (0x%x) found at 0x%lx\n",
1228		       IS_MERCURY(dev) ? "Mercury" : "Quicksilver", major,
1229		       minor, func_class, (long)dev->hpa.start);
1230
1231		cfg_ops = &mercury_cfg_ops;
1232	} else {
1233		printk(KERN_ERR "Unknown LBA found at 0x%lx\n",
1234			(long)dev->hpa.start);
1235		return -ENODEV;
1236	}
1237
1238	/* Tell I/O SAPIC driver we have a IRQ handler/region. */
1239	tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE);
1240
1241	/* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
1242	**	have an IRT entry will get NULL back from iosapic code.
1243	*/
1244
1245	lba_dev = kzalloc(sizeof(struct lba_device), GFP_KERNEL);
1246	if (!lba_dev) {
1247		printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n");
1248		return(1);
1249	}
1250
1251
1252	/* ---------- First : initialize data we already have --------- */
1253
1254	lba_dev->hw_rev = func_class;
1255	lba_dev->hba.base_addr = addr;
1256	lba_dev->hba.dev = dev;
1257	lba_dev->iosapic_obj = tmp_obj;  /* save interrupt handle */
1258	lba_dev->hba.iommu = sba_get_iommu(dev);  /* get iommu data */
1259	parisc_set_drvdata(dev, lba_dev);
1260
1261	/* ------------ Second : initialize common stuff ---------- */
1262	pci_bios = &lba_bios_ops;
1263	pcibios_register_hba(HBA_DATA(lba_dev));
1264	spin_lock_init(&lba_dev->lba_lock);
1265
1266	if (lba_hw_init(lba_dev))
1267		return(1);
1268
1269	/* ---------- Third : setup I/O Port and MMIO resources  --------- */
1270
1271	if (is_pdc_pat()) {
1272		/* PDC PAT firmware uses PIOP region of GMMIO space. */
1273		pci_port = &lba_pat_port_ops;
1274		/* Go ask PDC PAT what resources this LBA has */
1275		lba_pat_resources(dev, lba_dev);
1276	} else {
1277		if (!astro_iop_base) {
1278			/* Sprockets PDC uses NPIOP region */
1279			astro_iop_base = ioremap_nocache(LBA_PORT_BASE, 64 * 1024);
1280			pci_port = &lba_astro_port_ops;
1281		}
1282
1283		/* Poke the chip a bit for /proc output */
1284		lba_legacy_resources(dev, lba_dev);
1285	}
1286
1287	if (lba_dev->hba.bus_num.start < lba_next_bus)
1288		lba_dev->hba.bus_num.start = lba_next_bus;
1289
1290	dev->dev.platform_data = lba_dev;
1291	lba_bus = lba_dev->hba.hba_bus =
1292		pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start,
1293				cfg_ops, NULL);
1294	if (lba_bus) {
1295		lba_next_bus = lba_bus->subordinate + 1;
1296		pci_bus_add_devices(lba_bus);
1297	}
1298
1299	/* This is in lieu of calling pci_assign_unassigned_resources() */
1300	if (is_pdc_pat()) {
1301		/* assign resources to un-initialized devices */
1302
1303		DBG_PAT("LBA pci_bus_size_bridges()\n");
1304		pci_bus_size_bridges(lba_bus);
1305
1306		DBG_PAT("LBA pci_bus_assign_resources()\n");
1307		pci_bus_assign_resources(lba_bus);
1308
1309#ifdef DEBUG_LBA_PAT
1310		DBG_PAT("\nLBA PIOP resource tree\n");
1311		lba_dump_res(&lba_dev->hba.io_space, 2);
1312		DBG_PAT("\nLBA LMMIO resource tree\n");
1313		lba_dump_res(&lba_dev->hba.lmmio_space, 2);
1314#endif
1315	}
1316	pci_enable_bridges(lba_bus);
1317
1318
1319	/*
1320	** Once PCI register ops has walked the bus, access to config
1321	** space is restricted. Avoids master aborts on config cycles.
1322	** Early LBA revs go fatal on *any* master abort.
1323	*/
1324	if (cfg_ops == &elroy_cfg_ops) {
1325		lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
1326	}
1327
1328	/* Whew! Finally done! Tell services we got this one covered. */
1329	return 0;
1330}
1331
1332static struct parisc_device_id lba_tbl[] = {
1333	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa },
1334	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa },
1335	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa },
1336	{ 0, }
1337};
1338
1339static struct parisc_driver lba_driver = {
1340	.name =		MODULE_NAME,
1341	.id_table =	lba_tbl,
1342	.probe =	lba_driver_probe,
1343};
1344
1345/*
1346** One time initialization to let the world know the LBA was found.
1347** Must be called exactly once before pci_init().
1348*/
1349void __init lba_init(void)
1350{
1351	register_parisc_driver(&lba_driver);
1352}
1353
1354/*
1355** Initialize the IBASE/IMASK registers for LBA (Elroy).
1356** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
1357** sba_iommu is responsible for locking (none needed at init time).
1358*/
1359void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask)
1360{
1361	void __iomem * base_addr = ioremap_nocache(lba->hpa.start, 4096);
1362
1363	imask <<= 2;	/* adjust for hints - 2 more bits */
1364
1365	/* Make sure we aren't trying to set bits that aren't writeable. */
1366	WARN_ON((ibase & 0x001fffff) != 0);
1367	WARN_ON((imask & 0x001fffff) != 0);
1368
1369	DBG("%s() ibase 0x%x imask 0x%x\n", __FUNCTION__, ibase, imask);
1370	WRITE_REG32( imask, base_addr + LBA_IMASK);
1371	WRITE_REG32( ibase, base_addr + LBA_IBASE);
1372	iounmap(base_addr);
1373}
1374