1/* 2** ccio-dma.c: 3** DMA management routines for first generation cache-coherent machines. 4** Program U2/Uturn in "Virtual Mode" and use the I/O MMU. 5** 6** (c) Copyright 2000 Grant Grundler 7** (c) Copyright 2000 Ryan Bradetich 8** (c) Copyright 2000 Hewlett-Packard Company 9** 10** This program is free software; you can redistribute it and/or modify 11** it under the terms of the GNU General Public License as published by 12** the Free Software Foundation; either version 2 of the License, or 13** (at your option) any later version. 14** 15** 16** "Real Mode" operation refers to U2/Uturn chip operation. 17** U2/Uturn were designed to perform coherency checks w/o using 18** the I/O MMU - basically what x86 does. 19** 20** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at: 21** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc 22** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c 23** 24** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c. 25** 26** Drawbacks of using Real Mode are: 27** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal). 28** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute. 29** o Ability to do scatter/gather in HW is lost. 30** o Doesn't work under PCX-U/U+ machines since they didn't follow 31** the coherency design originally worked out. Only PCX-W does. 32*/ 33 34#include <linux/types.h> 35#include <linux/kernel.h> 36#include <linux/init.h> 37#include <linux/mm.h> 38#include <linux/spinlock.h> 39#include <linux/slab.h> 40#include <linux/string.h> 41#include <linux/pci.h> 42#include <linux/reboot.h> 43#include <linux/proc_fs.h> 44#include <linux/seq_file.h> 45 46#include <asm/byteorder.h> 47#include <asm/cache.h> /* for L1_CACHE_BYTES */ 48#include <asm/uaccess.h> 49#include <asm/page.h> 50#include <asm/dma.h> 51#include <asm/io.h> 52#include <asm/hardware.h> /* for register_module() */ 53#include <asm/parisc-device.h> 54 55/* 56** Choose "ccio" since that's what HP-UX calls it. 57** Make it easier for folks to migrate from one to the other :^) 58*/ 59#define MODULE_NAME "ccio" 60 61#undef DEBUG_CCIO_RES 62#undef DEBUG_CCIO_RUN 63#undef DEBUG_CCIO_INIT 64#undef DEBUG_CCIO_RUN_SG 65 66#ifdef CONFIG_PROC_FS 67/* 68 * CCIO_SEARCH_TIME can help measure how fast the bitmap search is. 69 * impacts performance though - ditch it if you don't use it. 70 */ 71#define CCIO_SEARCH_TIME 72#undef CCIO_MAP_STATS 73#else 74#undef CCIO_SEARCH_TIME 75#undef CCIO_MAP_STATS 76#endif 77 78#include <linux/proc_fs.h> 79#include <asm/runway.h> /* for proc_runway_root */ 80 81#ifdef DEBUG_CCIO_INIT 82#define DBG_INIT(x...) printk(x) 83#else 84#define DBG_INIT(x...) 85#endif 86 87#ifdef DEBUG_CCIO_RUN 88#define DBG_RUN(x...) printk(x) 89#else 90#define DBG_RUN(x...) 91#endif 92 93#ifdef DEBUG_CCIO_RES 94#define DBG_RES(x...) printk(x) 95#else 96#define DBG_RES(x...) 97#endif 98 99#ifdef DEBUG_CCIO_RUN_SG 100#define DBG_RUN_SG(x...) printk(x) 101#else 102#define DBG_RUN_SG(x...) 103#endif 104 105#define CCIO_INLINE inline 106#define WRITE_U32(value, addr) __raw_writel(value, addr) 107#define READ_U32(addr) __raw_readl(addr) 108 109#define U2_IOA_RUNWAY 0x580 110#define U2_BC_GSC 0x501 111#define UTURN_IOA_RUNWAY 0x581 112#define UTURN_BC_GSC 0x502 113 114#define IOA_NORMAL_MODE 0x00020080 /* IO_CONTROL to turn on CCIO */ 115#define CMD_TLB_DIRECT_WRITE 35 /* IO_COMMAND for I/O TLB Writes */ 116#define CMD_TLB_PURGE 33 /* IO_COMMAND to Purge I/O TLB entry */ 117 118struct ioa_registers { 119 /* Runway Supervisory Set */ 120 int32_t unused1[12]; 121 uint32_t io_command; /* Offset 12 */ 122 uint32_t io_status; /* Offset 13 */ 123 uint32_t io_control; /* Offset 14 */ 124 int32_t unused2[1]; 125 126 /* Runway Auxiliary Register Set */ 127 uint32_t io_err_resp; /* Offset 0 */ 128 uint32_t io_err_info; /* Offset 1 */ 129 uint32_t io_err_req; /* Offset 2 */ 130 uint32_t io_err_resp_hi; /* Offset 3 */ 131 uint32_t io_tlb_entry_m; /* Offset 4 */ 132 uint32_t io_tlb_entry_l; /* Offset 5 */ 133 uint32_t unused3[1]; 134 uint32_t io_pdir_base; /* Offset 7 */ 135 uint32_t io_io_low_hv; /* Offset 8 */ 136 uint32_t io_io_high_hv; /* Offset 9 */ 137 uint32_t unused4[1]; 138 uint32_t io_chain_id_mask; /* Offset 11 */ 139 uint32_t unused5[2]; 140 uint32_t io_io_low; /* Offset 14 */ 141 uint32_t io_io_high; /* Offset 15 */ 142}; 143 144/* 145** IOA Registers 146** ------------- 147** 148** Runway IO_CONTROL Register (+0x38) 149** 150** The Runway IO_CONTROL register controls the forwarding of transactions. 151** 152** | 0 ... 13 | 14 15 | 16 ... 21 | 22 | 23 24 | 25 ... 31 | 153** | HV | TLB | reserved | HV | mode | reserved | 154** 155** o mode field indicates the address translation of transactions 156** forwarded from Runway to GSC+: 157** Mode Name Value Definition 158** Off (default) 0 Opaque to matching addresses. 159** Include 1 Transparent for matching addresses. 160** Peek 3 Map matching addresses. 161** 162** + "Off" mode: Runway transactions which match the I/O range 163** specified by the IO_IO_LOW/IO_IO_HIGH registers will be ignored. 164** + "Include" mode: all addresses within the I/O range specified 165** by the IO_IO_LOW and IO_IO_HIGH registers are transparently 166** forwarded. This is the I/O Adapter's normal operating mode. 167** + "Peek" mode: used during system configuration to initialize the 168** GSC+ bus. Runway Write_Shorts in the address range specified by 169** IO_IO_LOW and IO_IO_HIGH are forwarded through the I/O Adapter 170** *AND* the GSC+ address is remapped to the Broadcast Physical 171** Address space by setting the 14 high order address bits of the 172** 32 bit GSC+ address to ones. 173** 174** o TLB field affects transactions which are forwarded from GSC+ to Runway. 175** "Real" mode is the poweron default. 176** 177** TLB Mode Value Description 178** Real 0 No TLB translation. Address is directly mapped and the 179** virtual address is composed of selected physical bits. 180** Error 1 Software fills the TLB manually. 181** Normal 2 IOA fetches IO TLB misses from IO PDIR (in host memory). 182** 183** 184** IO_IO_LOW_HV +0x60 (HV dependent) 185** IO_IO_HIGH_HV +0x64 (HV dependent) 186** IO_IO_LOW +0x78 (Architected register) 187** IO_IO_HIGH +0x7c (Architected register) 188** 189** IO_IO_LOW and IO_IO_HIGH set the lower and upper bounds of the 190** I/O Adapter address space, respectively. 191** 192** 0 ... 7 | 8 ... 15 | 16 ... 31 | 193** 11111111 | 11111111 | address | 194** 195** Each LOW/HIGH pair describes a disjoint address space region. 196** (2 per GSC+ port). Each incoming Runway transaction address is compared 197** with both sets of LOW/HIGH registers. If the address is in the range 198** greater than or equal to IO_IO_LOW and less than IO_IO_HIGH the transaction 199** for forwarded to the respective GSC+ bus. 200** Specify IO_IO_LOW equal to or greater than IO_IO_HIGH to avoid specifying 201** an address space region. 202** 203** In order for a Runway address to reside within GSC+ extended address space: 204** Runway Address [0:7] must identically compare to 8'b11111111 205** Runway Address [8:11] must be equal to IO_IO_LOW(_HV)[16:19] 206** Runway Address [12:23] must be greater than or equal to 207** IO_IO_LOW(_HV)[20:31] and less than IO_IO_HIGH(_HV)[20:31]. 208** Runway Address [24:39] is not used in the comparison. 209** 210** When the Runway transaction is forwarded to GSC+, the GSC+ address is 211** as follows: 212** GSC+ Address[0:3] 4'b1111 213** GSC+ Address[4:29] Runway Address[12:37] 214** GSC+ Address[30:31] 2'b00 215** 216** All 4 Low/High registers must be initialized (by PDC) once the lower bus 217** is interrogated and address space is defined. The operating system will 218** modify the architectural IO_IO_LOW and IO_IO_HIGH registers following 219** the PDC initialization. However, the hardware version dependent IO_IO_LOW 220** and IO_IO_HIGH registers should not be subsequently altered by the OS. 221** 222** Writes to both sets of registers will take effect immediately, bypassing 223** the queues, which ensures that subsequent Runway transactions are checked 224** against the updated bounds values. However reads are queued, introducing 225** the possibility of a read being bypassed by a subsequent write to the same 226** register. This sequence can be avoided by having software wait for read 227** returns before issuing subsequent writes. 228*/ 229 230struct ioc { 231 struct ioa_registers __iomem *ioc_regs; /* I/O MMU base address */ 232 u8 *res_map; /* resource map, bit == pdir entry */ 233 u64 *pdir_base; /* physical base address */ 234 u32 pdir_size; /* bytes, function of IOV Space size */ 235 u32 res_hint; /* next available IOVP - 236 circular search */ 237 u32 res_size; /* size of resource map in bytes */ 238 spinlock_t res_lock; 239 240#ifdef CCIO_SEARCH_TIME 241#define CCIO_SEARCH_SAMPLE 0x100 242 unsigned long avg_search[CCIO_SEARCH_SAMPLE]; 243 unsigned long avg_idx; /* current index into avg_search */ 244#endif 245#ifdef CCIO_MAP_STATS 246 unsigned long used_pages; 247 unsigned long msingle_calls; 248 unsigned long msingle_pages; 249 unsigned long msg_calls; 250 unsigned long msg_pages; 251 unsigned long usingle_calls; 252 unsigned long usingle_pages; 253 unsigned long usg_calls; 254 unsigned long usg_pages; 255#endif 256 unsigned short cujo20_bug; 257 258 /* STUFF We don't need in performance path */ 259 u32 chainid_shift; /* specify bit location of chain_id */ 260 struct ioc *next; /* Linked list of discovered iocs */ 261 const char *name; /* device name from firmware */ 262 unsigned int hw_path; /* the hardware path this ioc is associatd with */ 263 struct pci_dev *fake_pci_dev; /* the fake pci_dev for non-pci devs */ 264 struct resource mmio_region[2]; /* The "routed" MMIO regions */ 265}; 266 267static struct ioc *ioc_list; 268static int ioc_count; 269 270/************************************************************** 271* 272* I/O Pdir Resource Management 273* 274* Bits set in the resource map are in use. 275* Each bit can represent a number of pages. 276* LSbs represent lower addresses (IOVA's). 277* 278* This was was copied from sba_iommu.c. Don't try to unify 279* the two resource managers unless a way to have different 280* allocation policies is also adjusted. We'd like to avoid 281* I/O TLB thrashing by having resource allocation policy 282* match the I/O TLB replacement policy. 283* 284***************************************************************/ 285#define IOVP_SIZE PAGE_SIZE 286#define IOVP_SHIFT PAGE_SHIFT 287#define IOVP_MASK PAGE_MASK 288 289/* Convert from IOVP to IOVA and vice versa. */ 290#define CCIO_IOVA(iovp,offset) ((iovp) | (offset)) 291#define CCIO_IOVP(iova) ((iova) & IOVP_MASK) 292 293#define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 294#define MKIOVP(pdir_idx) ((long)(pdir_idx) << IOVP_SHIFT) 295#define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset) 296 297/* 298** Don't worry about the 150% average search length on a miss. 299** If the search wraps around, and passes the res_hint, it will 300** cause the kernel to panic anyhow. 301*/ 302#define CCIO_SEARCH_LOOP(ioc, res_idx, mask, size) \ 303 for(; res_ptr < res_end; ++res_ptr) { \ 304 if(0 == (*res_ptr & mask)) { \ 305 *res_ptr |= mask; \ 306 res_idx = (unsigned int)((unsigned long)res_ptr - (unsigned long)ioc->res_map); \ 307 ioc->res_hint = res_idx + (size >> 3); \ 308 goto resource_found; \ 309 } \ 310 } 311 312#define CCIO_FIND_FREE_MAPPING(ioa, res_idx, mask, size) \ 313 u##size *res_ptr = (u##size *)&((ioc)->res_map[ioa->res_hint & ~((size >> 3) - 1)]); \ 314 u##size *res_end = (u##size *)&(ioc)->res_map[ioa->res_size]; \ 315 CCIO_SEARCH_LOOP(ioc, res_idx, mask, size); \ 316 res_ptr = (u##size *)&(ioc)->res_map[0]; \ 317 CCIO_SEARCH_LOOP(ioa, res_idx, mask, size); 318 319/* 320** Find available bit in this ioa's resource map. 321** Use a "circular" search: 322** o Most IOVA's are "temporary" - avg search time should be small. 323** o keep a history of what happened for debugging 324** o KISS. 325** 326** Perf optimizations: 327** o search for log2(size) bits at a time. 328** o search for available resource bits using byte/word/whatever. 329** o use different search for "large" (eg > 4 pages) or "very large" 330** (eg > 16 pages) mappings. 331*/ 332 333/** 334 * ccio_alloc_range - Allocate pages in the ioc's resource map. 335 * @ioc: The I/O Controller. 336 * @pages_needed: The requested number of pages to be mapped into the 337 * I/O Pdir... 338 * 339 * This function searches the resource map of the ioc to locate a range 340 * of available pages for the requested size. 341 */ 342static int 343ccio_alloc_range(struct ioc *ioc, size_t size) 344{ 345 unsigned int pages_needed = size >> IOVP_SHIFT; 346 unsigned int res_idx; 347#ifdef CCIO_SEARCH_TIME 348 unsigned long cr_start = mfctl(16); 349#endif 350 351 BUG_ON(pages_needed == 0); 352 BUG_ON((pages_needed * IOVP_SIZE) > DMA_CHUNK_SIZE); 353 354 DBG_RES("%s() size: %d pages_needed %d\n", 355 __FUNCTION__, size, pages_needed); 356 357 /* 358 ** "seek and ye shall find"...praying never hurts either... 359 ** ggg sacrifices another 710 to the computer gods. 360 */ 361 362 if (pages_needed <= 8) { 363 /* 364 * LAN traffic will not thrash the TLB IFF the same NIC 365 * uses 8 adjacent pages to map seperate payload data. 366 * ie the same byte in the resource bit map. 367 */ 368 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xff, 8); 369 } else if (pages_needed <= 16) { 370 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xffff, 16); 371 } else if (pages_needed <= 32) { 372 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~(unsigned int)0, 32); 373#ifdef __LP64__ 374 } else if (pages_needed <= 64) { 375 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~0UL, 64); 376#endif 377 } else { 378 panic("%s: %s() Too many pages to map. pages_needed: %u\n", 379 __FILE__, __FUNCTION__, pages_needed); 380 } 381 382 panic("%s: %s() I/O MMU is out of mapping resources.\n", __FILE__, 383 __FUNCTION__); 384 385resource_found: 386 387 DBG_RES("%s() res_idx %d res_hint: %d\n", 388 __FUNCTION__, res_idx, ioc->res_hint); 389 390#ifdef CCIO_SEARCH_TIME 391 { 392 unsigned long cr_end = mfctl(16); 393 unsigned long tmp = cr_end - cr_start; 394 /* check for roll over */ 395 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 396 } 397 ioc->avg_search[ioc->avg_idx++] = cr_start; 398 ioc->avg_idx &= CCIO_SEARCH_SAMPLE - 1; 399#endif 400#ifdef CCIO_MAP_STATS 401 ioc->used_pages += pages_needed; 402#endif 403 /* 404 ** return the bit address. 405 */ 406 return res_idx << 3; 407} 408 409#define CCIO_FREE_MAPPINGS(ioc, res_idx, mask, size) \ 410 u##size *res_ptr = (u##size *)&((ioc)->res_map[res_idx]); \ 411 BUG_ON((*res_ptr & mask) != mask); \ 412 *res_ptr &= ~(mask); 413 414/** 415 * ccio_free_range - Free pages from the ioc's resource map. 416 * @ioc: The I/O Controller. 417 * @iova: The I/O Virtual Address. 418 * @pages_mapped: The requested number of pages to be freed from the 419 * I/O Pdir. 420 * 421 * This function frees the resouces allocated for the iova. 422 */ 423static void 424ccio_free_range(struct ioc *ioc, dma_addr_t iova, unsigned long pages_mapped) 425{ 426 unsigned long iovp = CCIO_IOVP(iova); 427 unsigned int res_idx = PDIR_INDEX(iovp) >> 3; 428 429 BUG_ON(pages_mapped == 0); 430 BUG_ON((pages_mapped * IOVP_SIZE) > DMA_CHUNK_SIZE); 431 BUG_ON(pages_mapped > BITS_PER_LONG); 432 433 DBG_RES("%s(): res_idx: %d pages_mapped %d\n", 434 __FUNCTION__, res_idx, pages_mapped); 435 436#ifdef CCIO_MAP_STATS 437 ioc->used_pages -= pages_mapped; 438#endif 439 440 if(pages_mapped <= 8) { 441 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xff, 8); 442 } else if(pages_mapped <= 16) { 443 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffff, 16); 444 } else if(pages_mapped <= 32) { 445 CCIO_FREE_MAPPINGS(ioc, res_idx, ~(unsigned int)0, 32); 446#ifdef __LP64__ 447 } else if(pages_mapped <= 64) { 448 CCIO_FREE_MAPPINGS(ioc, res_idx, ~0UL, 64); 449#endif 450 } else { 451 panic("%s:%s() Too many pages to unmap.\n", __FILE__, 452 __FUNCTION__); 453 } 454} 455 456/**************************************************************** 457** 458** CCIO dma_ops support routines 459** 460*****************************************************************/ 461 462typedef unsigned long space_t; 463#define KERNEL_SPACE 0 464 465#define IOPDIR_VALID 0x01UL 466#define HINT_SAFE_DMA 0x02UL /* used for pci_alloc_consistent() pages */ 467#ifdef CONFIG_EISA 468#define HINT_STOP_MOST 0x04UL /* LSL support */ 469#else 470#define HINT_STOP_MOST 0x00UL /* only needed for "some EISA devices" */ 471#endif 472#define HINT_UDPATE_ENB 0x08UL /* not used/supported by U2 */ 473#define HINT_PREFETCH 0x10UL /* for outbound pages which are not SAFE */ 474 475 476/* 477** Use direction (ie PCI_DMA_TODEVICE) to pick hint. 478** ccio_alloc_consistent() depends on this to get SAFE_DMA 479** when it passes in BIDIRECTIONAL flag. 480*/ 481static u32 hint_lookup[] = { 482 [PCI_DMA_BIDIRECTIONAL] = HINT_STOP_MOST | HINT_SAFE_DMA | IOPDIR_VALID, 483 [PCI_DMA_TODEVICE] = HINT_STOP_MOST | HINT_PREFETCH | IOPDIR_VALID, 484 [PCI_DMA_FROMDEVICE] = HINT_STOP_MOST | IOPDIR_VALID, 485}; 486 487/** 488 * ccio_io_pdir_entry - Initialize an I/O Pdir. 489 * @pdir_ptr: A pointer into I/O Pdir. 490 * @sid: The Space Identifier. 491 * @vba: The virtual address. 492 * @hints: The DMA Hint. 493 * 494 * Given a virtual address (vba, arg2) and space id, (sid, arg1), 495 * load the I/O PDIR entry pointed to by pdir_ptr (arg0). Each IO Pdir 496 * entry consists of 8 bytes as shown below (MSB == bit 0): 497 * 498 * 499 * WORD 0: 500 * +------+----------------+-----------------------------------------------+ 501 * | Phys | Virtual Index | Phys | 502 * | 0:3 | 0:11 | 4:19 | 503 * |4 bits| 12 bits | 16 bits | 504 * +------+----------------+-----------------------------------------------+ 505 * WORD 1: 506 * +-----------------------+-----------------------------------------------+ 507 * | Phys | Rsvd | Prefetch |Update |Rsvd |Lock |Safe |Valid | 508 * | 20:39 | | Enable |Enable | |Enable|DMA | | 509 * | 20 bits | 5 bits | 1 bit |1 bit |2 bits|1 bit |1 bit |1 bit | 510 * +-----------------------+-----------------------------------------------+ 511 * 512 * The virtual index field is filled with the results of the LCI 513 * (Load Coherence Index) instruction. The 8 bits used for the virtual 514 * index are bits 12:19 of the value returned by LCI. 515 */ 516void CCIO_INLINE 517ccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, 518 unsigned long hints) 519{ 520 register unsigned long pa; 521 register unsigned long ci; /* coherent index */ 522 523 /* We currently only support kernel addresses */ 524 BUG_ON(sid != KERNEL_SPACE); 525 526 mtsp(sid,1); 527 528 /* 529 ** WORD 1 - low order word 530 ** "hints" parm includes the VALID bit! 531 ** "dep" clobbers the physical address offset bits as well. 532 */ 533 pa = virt_to_phys(vba); 534 asm volatile("depw %1,31,12,%0" : "+r" (pa) : "r" (hints)); 535 ((u32 *)pdir_ptr)[1] = (u32) pa; 536 537 /* 538 ** WORD 0 - high order word 539 */ 540 541#ifdef __LP64__ 542 /* 543 ** get bits 12:15 of physical address 544 ** shift bits 16:31 of physical address 545 ** and deposit them 546 */ 547 asm volatile ("extrd,u %1,15,4,%0" : "=r" (ci) : "r" (pa)); 548 asm volatile ("extrd,u %1,31,16,%0" : "+r" (pa) : "r" (pa)); 549 asm volatile ("depd %1,35,4,%0" : "+r" (pa) : "r" (ci)); 550#else 551 pa = 0; 552#endif 553 /* 554 ** get CPU coherency index bits 555 ** Grab virtual index [0:11] 556 ** Deposit virt_idx bits into I/O PDIR word 557 */ 558 asm volatile ("lci %%r0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 559 asm volatile ("extru %1,19,12,%0" : "+r" (ci) : "r" (ci)); 560 asm volatile ("depw %1,15,12,%0" : "+r" (pa) : "r" (ci)); 561 562 ((u32 *)pdir_ptr)[0] = (u32) pa; 563 564 565 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 566 asm volatile("sync"); 567} 568 569static CCIO_INLINE void 570ccio_clear_io_tlb(struct ioc *ioc, dma_addr_t iovp, size_t byte_cnt) 571{ 572 u32 chain_size = 1 << ioc->chainid_shift; 573 574 iovp &= IOVP_MASK; /* clear offset bits, just want pagenum */ 575 byte_cnt += chain_size; 576 577 while(byte_cnt > chain_size) { 578 WRITE_U32(CMD_TLB_PURGE | iovp, &ioc->ioc_regs->io_command); 579 iovp += chain_size; 580 byte_cnt -= chain_size; 581 } 582} 583 584static CCIO_INLINE void 585ccio_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 586{ 587 u32 iovp = (u32)CCIO_IOVP(iova); 588 size_t saved_byte_cnt; 589 590 /* round up to nearest page size */ 591 saved_byte_cnt = byte_cnt = ALIGN(byte_cnt, IOVP_SIZE); 592 593 while(byte_cnt > 0) { 594 /* invalidate one page at a time */ 595 unsigned int idx = PDIR_INDEX(iovp); 596 char *pdir_ptr = (char *) &(ioc->pdir_base[idx]); 597 598 BUG_ON(idx >= (ioc->pdir_size / sizeof(u64))); 599 pdir_ptr[7] = 0; /* clear only VALID bit */ 600 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr[7])); 601 602 iovp += IOVP_SIZE; 603 byte_cnt -= IOVP_SIZE; 604 } 605 606 asm volatile("sync"); 607 ccio_clear_io_tlb(ioc, CCIO_IOVP(iova), saved_byte_cnt); 608} 609 610/**************************************************************** 611** 612** CCIO dma_ops 613** 614*****************************************************************/ 615 616/** 617 * ccio_dma_supported - Verify the IOMMU supports the DMA address range. 618 * @dev: The PCI device. 619 * @mask: A bit mask describing the DMA address range of the device. 620 * 621 * This function implements the pci_dma_supported function. 622 */ 623static int 624ccio_dma_supported(struct device *dev, u64 mask) 625{ 626 if(dev == NULL) { 627 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 628 BUG(); 629 return 0; 630 } 631 632 /* only support 32-bit devices (ie PCI/GSC) */ 633 return (int)(mask == 0xffffffffUL); 634} 635 636/** 637 * ccio_map_single - Map an address range into the IOMMU. 638 * @dev: The PCI device. 639 * @addr: The start address of the DMA region. 640 * @size: The length of the DMA region. 641 * @direction: The direction of the DMA transaction (to/from device). 642 * 643 * This function implements the pci_map_single function. 644 */ 645static dma_addr_t 646ccio_map_single(struct device *dev, void *addr, size_t size, 647 enum dma_data_direction direction) 648{ 649 int idx; 650 struct ioc *ioc; 651 unsigned long flags; 652 dma_addr_t iovp; 653 dma_addr_t offset; 654 u64 *pdir_start; 655 unsigned long hint = hint_lookup[(int)direction]; 656 657 BUG_ON(!dev); 658 ioc = GET_IOC(dev); 659 660 BUG_ON(size <= 0); 661 662 /* save offset bits */ 663 offset = ((unsigned long) addr) & ~IOVP_MASK; 664 665 /* round up to nearest IOVP_SIZE */ 666 size = ALIGN(size + offset, IOVP_SIZE); 667 spin_lock_irqsave(&ioc->res_lock, flags); 668 669#ifdef CCIO_MAP_STATS 670 ioc->msingle_calls++; 671 ioc->msingle_pages += size >> IOVP_SHIFT; 672#endif 673 674 idx = ccio_alloc_range(ioc, size); 675 iovp = (dma_addr_t)MKIOVP(idx); 676 677 pdir_start = &(ioc->pdir_base[idx]); 678 679 DBG_RUN("%s() 0x%p -> 0x%lx size: %0x%x\n", 680 __FUNCTION__, addr, (long)iovp | offset, size); 681 682 /* If not cacheline aligned, force SAFE_DMA on the whole mess */ 683 if((size % L1_CACHE_BYTES) || ((unsigned long)addr % L1_CACHE_BYTES)) 684 hint |= HINT_SAFE_DMA; 685 686 while(size > 0) { 687 ccio_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long)addr, hint); 688 689 DBG_RUN(" pdir %p %08x%08x\n", 690 pdir_start, 691 (u32) (((u32 *) pdir_start)[0]), 692 (u32) (((u32 *) pdir_start)[1])); 693 ++pdir_start; 694 addr += IOVP_SIZE; 695 size -= IOVP_SIZE; 696 } 697 698 spin_unlock_irqrestore(&ioc->res_lock, flags); 699 700 /* form complete address */ 701 return CCIO_IOVA(iovp, offset); 702} 703 704/** 705 * ccio_unmap_single - Unmap an address range from the IOMMU. 706 * @dev: The PCI device. 707 * @addr: The start address of the DMA region. 708 * @size: The length of the DMA region. 709 * @direction: The direction of the DMA transaction (to/from device). 710 * 711 * This function implements the pci_unmap_single function. 712 */ 713static void 714ccio_unmap_single(struct device *dev, dma_addr_t iova, size_t size, 715 enum dma_data_direction direction) 716{ 717 struct ioc *ioc; 718 unsigned long flags; 719 dma_addr_t offset = iova & ~IOVP_MASK; 720 721 BUG_ON(!dev); 722 ioc = GET_IOC(dev); 723 724 DBG_RUN("%s() iovp 0x%lx/%x\n", 725 __FUNCTION__, (long)iova, size); 726 727 iova ^= offset; /* clear offset bits */ 728 size += offset; 729 size = ALIGN(size, IOVP_SIZE); 730 731 spin_lock_irqsave(&ioc->res_lock, flags); 732 733#ifdef CCIO_MAP_STATS 734 ioc->usingle_calls++; 735 ioc->usingle_pages += size >> IOVP_SHIFT; 736#endif 737 738 ccio_mark_invalid(ioc, iova, size); 739 ccio_free_range(ioc, iova, (size >> IOVP_SHIFT)); 740 spin_unlock_irqrestore(&ioc->res_lock, flags); 741} 742 743/** 744 * ccio_alloc_consistent - Allocate a consistent DMA mapping. 745 * @dev: The PCI device. 746 * @size: The length of the DMA region. 747 * @dma_handle: The DMA address handed back to the device (not the cpu). 748 * 749 * This function implements the pci_alloc_consistent function. 750 */ 751static void * 752ccio_alloc_consistent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag) 753{ 754 void *ret; 755 ret = (void *) __get_free_pages(flag, get_order(size)); 756 757 if (ret) { 758 memset(ret, 0, size); 759 *dma_handle = ccio_map_single(dev, ret, size, PCI_DMA_BIDIRECTIONAL); 760 } 761 762 return ret; 763} 764 765/** 766 * ccio_free_consistent - Free a consistent DMA mapping. 767 * @dev: The PCI device. 768 * @size: The length of the DMA region. 769 * @cpu_addr: The cpu address returned from the ccio_alloc_consistent. 770 * @dma_handle: The device address returned from the ccio_alloc_consistent. 771 * 772 * This function implements the pci_free_consistent function. 773 */ 774static void 775ccio_free_consistent(struct device *dev, size_t size, void *cpu_addr, 776 dma_addr_t dma_handle) 777{ 778 ccio_unmap_single(dev, dma_handle, size, 0); 779 free_pages((unsigned long)cpu_addr, get_order(size)); 780} 781 782/* 783** Since 0 is a valid pdir_base index value, can't use that 784** to determine if a value is valid or not. Use a flag to indicate 785** the SG list entry contains a valid pdir index. 786*/ 787#define PIDE_FLAG 0x80000000UL 788 789#ifdef CCIO_MAP_STATS 790#define IOMMU_MAP_STATS 791#endif 792#include "iommu-helpers.h" 793 794/** 795 * ccio_map_sg - Map the scatter/gather list into the IOMMU. 796 * @dev: The PCI device. 797 * @sglist: The scatter/gather list to be mapped in the IOMMU. 798 * @nents: The number of entries in the scatter/gather list. 799 * @direction: The direction of the DMA transaction (to/from device). 800 * 801 * This function implements the pci_map_sg function. 802 */ 803static int 804ccio_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 805 enum dma_data_direction direction) 806{ 807 struct ioc *ioc; 808 int coalesced, filled = 0; 809 unsigned long flags; 810 unsigned long hint = hint_lookup[(int)direction]; 811 unsigned long prev_len = 0, current_len = 0; 812 int i; 813 814 BUG_ON(!dev); 815 ioc = GET_IOC(dev); 816 817 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents); 818 819 /* Fast path single entry scatterlists. */ 820 if (nents == 1) { 821 sg_dma_address(sglist) = ccio_map_single(dev, 822 (void *)sg_virt_addr(sglist), sglist->length, 823 direction); 824 sg_dma_len(sglist) = sglist->length; 825 return 1; 826 } 827 828 for(i = 0; i < nents; i++) 829 prev_len += sglist[i].length; 830 831 spin_lock_irqsave(&ioc->res_lock, flags); 832 833#ifdef CCIO_MAP_STATS 834 ioc->msg_calls++; 835#endif 836 837 /* 838 ** First coalesce the chunks and allocate I/O pdir space 839 ** 840 ** If this is one DMA stream, we can properly map using the 841 ** correct virtual address associated with each DMA page. 842 ** w/o this association, we wouldn't have coherent DMA! 843 ** Access to the virtual address is what forces a two pass algorithm. 844 */ 845 coalesced = iommu_coalesce_chunks(ioc, sglist, nents, ccio_alloc_range); 846 847 /* 848 ** Program the I/O Pdir 849 ** 850 ** map the virtual addresses to the I/O Pdir 851 ** o dma_address will contain the pdir index 852 ** o dma_len will contain the number of bytes to map 853 ** o page/offset contain the virtual address. 854 */ 855 filled = iommu_fill_pdir(ioc, sglist, nents, hint, ccio_io_pdir_entry); 856 857 spin_unlock_irqrestore(&ioc->res_lock, flags); 858 859 BUG_ON(coalesced != filled); 860 861 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled); 862 863 for (i = 0; i < filled; i++) 864 current_len += sg_dma_len(sglist + i); 865 866 BUG_ON(current_len != prev_len); 867 868 return filled; 869} 870 871/** 872 * ccio_unmap_sg - Unmap the scatter/gather list from the IOMMU. 873 * @dev: The PCI device. 874 * @sglist: The scatter/gather list to be unmapped from the IOMMU. 875 * @nents: The number of entries in the scatter/gather list. 876 * @direction: The direction of the DMA transaction (to/from device). 877 * 878 * This function implements the pci_unmap_sg function. 879 */ 880static void 881ccio_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 882 enum dma_data_direction direction) 883{ 884 struct ioc *ioc; 885 886 BUG_ON(!dev); 887 ioc = GET_IOC(dev); 888 889 DBG_RUN_SG("%s() START %d entries, %08lx,%x\n", 890 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length); 891 892#ifdef CCIO_MAP_STATS 893 ioc->usg_calls++; 894#endif 895 896 while(sg_dma_len(sglist) && nents--) { 897 898#ifdef CCIO_MAP_STATS 899 ioc->usg_pages += sg_dma_len(sglist) >> PAGE_SHIFT; 900#endif 901 ccio_unmap_single(dev, sg_dma_address(sglist), 902 sg_dma_len(sglist), direction); 903 ++sglist; 904 } 905 906 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents); 907} 908 909static struct hppa_dma_ops ccio_ops = { 910 .dma_supported = ccio_dma_supported, 911 .alloc_consistent = ccio_alloc_consistent, 912 .alloc_noncoherent = ccio_alloc_consistent, 913 .free_consistent = ccio_free_consistent, 914 .map_single = ccio_map_single, 915 .unmap_single = ccio_unmap_single, 916 .map_sg = ccio_map_sg, 917 .unmap_sg = ccio_unmap_sg, 918 .dma_sync_single_for_cpu = NULL, /* NOP for U2/Uturn */ 919 .dma_sync_single_for_device = NULL, /* NOP for U2/Uturn */ 920 .dma_sync_sg_for_cpu = NULL, /* ditto */ 921 .dma_sync_sg_for_device = NULL, /* ditto */ 922}; 923 924#ifdef CONFIG_PROC_FS 925static int ccio_proc_info(struct seq_file *m, void *p) 926{ 927 int len = 0; 928 struct ioc *ioc = ioc_list; 929 930 while (ioc != NULL) { 931 unsigned int total_pages = ioc->res_size << 3; 932 unsigned long avg = 0, min, max; 933 int j; 934 935 len += seq_printf(m, "%s\n", ioc->name); 936 937 len += seq_printf(m, "Cujo 2.0 bug : %s\n", 938 (ioc->cujo20_bug ? "yes" : "no")); 939 940 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 941 total_pages * 8, total_pages); 942 943#ifdef CCIO_MAP_STATS 944 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 945 total_pages - ioc->used_pages, ioc->used_pages, 946 (int)(ioc->used_pages * 100 / total_pages)); 947#endif 948 949 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 950 ioc->res_size, total_pages); 951 952#ifdef CCIO_SEARCH_TIME 953 min = max = ioc->avg_search[0]; 954 for(j = 0; j < CCIO_SEARCH_SAMPLE; ++j) { 955 avg += ioc->avg_search[j]; 956 if(ioc->avg_search[j] > max) 957 max = ioc->avg_search[j]; 958 if(ioc->avg_search[j] < min) 959 min = ioc->avg_search[j]; 960 } 961 avg /= CCIO_SEARCH_SAMPLE; 962 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 963 min, avg, max); 964#endif 965#ifdef CCIO_MAP_STATS 966 len += seq_printf(m, "pci_map_single(): %8ld calls %8ld pages (avg %d/1000)\n", 967 ioc->msingle_calls, ioc->msingle_pages, 968 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 969 970 /* KLUGE - unmap_sg calls unmap_single for each mapped page */ 971 min = ioc->usingle_calls - ioc->usg_calls; 972 max = ioc->usingle_pages - ioc->usg_pages; 973 len += seq_printf(m, "pci_unmap_single: %8ld calls %8ld pages (avg %d/1000)\n", 974 min, max, (int)((max * 1000)/min)); 975 976 len += seq_printf(m, "pci_map_sg() : %8ld calls %8ld pages (avg %d/1000)\n", 977 ioc->msg_calls, ioc->msg_pages, 978 (int)((ioc->msg_pages * 1000)/ioc->msg_calls)); 979 980 len += seq_printf(m, "pci_unmap_sg() : %8ld calls %8ld pages (avg %d/1000)\n\n\n", 981 ioc->usg_calls, ioc->usg_pages, 982 (int)((ioc->usg_pages * 1000)/ioc->usg_calls)); 983#endif /* CCIO_MAP_STATS */ 984 985 ioc = ioc->next; 986 } 987 988 return 0; 989} 990 991static int ccio_proc_info_open(struct inode *inode, struct file *file) 992{ 993 return single_open(file, &ccio_proc_info, NULL); 994} 995 996static const struct file_operations ccio_proc_info_fops = { 997 .owner = THIS_MODULE, 998 .open = ccio_proc_info_open, 999 .read = seq_read, 1000 .llseek = seq_lseek, 1001 .release = single_release, 1002}; 1003 1004static int ccio_proc_bitmap_info(struct seq_file *m, void *p) 1005{ 1006 int len = 0; 1007 struct ioc *ioc = ioc_list; 1008 1009 while (ioc != NULL) { 1010 u32 *res_ptr = (u32 *)ioc->res_map; 1011 int j; 1012 1013 for (j = 0; j < (ioc->res_size / sizeof(u32)); j++) { 1014 if ((j & 7) == 0) 1015 len += seq_puts(m, "\n "); 1016 len += seq_printf(m, "%08x", *res_ptr); 1017 res_ptr++; 1018 } 1019 len += seq_puts(m, "\n\n"); 1020 ioc = ioc->next; 1021 break; 1022 } 1023 1024 return 0; 1025} 1026 1027static int ccio_proc_bitmap_open(struct inode *inode, struct file *file) 1028{ 1029 return single_open(file, &ccio_proc_bitmap_info, NULL); 1030} 1031 1032static const struct file_operations ccio_proc_bitmap_fops = { 1033 .owner = THIS_MODULE, 1034 .open = ccio_proc_bitmap_open, 1035 .read = seq_read, 1036 .llseek = seq_lseek, 1037 .release = single_release, 1038}; 1039#endif 1040 1041/** 1042 * ccio_find_ioc - Find the ioc in the ioc_list 1043 * @hw_path: The hardware path of the ioc. 1044 * 1045 * This function searches the ioc_list for an ioc that matches 1046 * the provide hardware path. 1047 */ 1048static struct ioc * ccio_find_ioc(int hw_path) 1049{ 1050 int i; 1051 struct ioc *ioc; 1052 1053 ioc = ioc_list; 1054 for (i = 0; i < ioc_count; i++) { 1055 if (ioc->hw_path == hw_path) 1056 return ioc; 1057 1058 ioc = ioc->next; 1059 } 1060 1061 return NULL; 1062} 1063 1064/** 1065 * ccio_get_iommu - Find the iommu which controls this device 1066 * @dev: The parisc device. 1067 * 1068 * This function searches through the registered IOMMU's and returns 1069 * the appropriate IOMMU for the device based on its hardware path. 1070 */ 1071void * ccio_get_iommu(const struct parisc_device *dev) 1072{ 1073 dev = find_pa_parent_type(dev, HPHW_IOA); 1074 if (!dev) 1075 return NULL; 1076 1077 return ccio_find_ioc(dev->hw_path); 1078} 1079 1080#define CUJO_20_STEP 0x10000000 /* inc upper nibble */ 1081 1082/* Cujo 2.0 has a bug which will silently corrupt data being transferred 1083 * to/from certain pages. To avoid this happening, we mark these pages 1084 * as `used', and ensure that nothing will try to allocate from them. 1085 */ 1086void ccio_cujo20_fixup(struct parisc_device *cujo, u32 iovp) 1087{ 1088 unsigned int idx; 1089 struct parisc_device *dev = parisc_parent(cujo); 1090 struct ioc *ioc = ccio_get_iommu(dev); 1091 u8 *res_ptr; 1092 1093 ioc->cujo20_bug = 1; 1094 res_ptr = ioc->res_map; 1095 idx = PDIR_INDEX(iovp) >> 3; 1096 1097 while (idx < ioc->res_size) { 1098 res_ptr[idx] |= 0xff; 1099 idx += PDIR_INDEX(CUJO_20_STEP) >> 3; 1100 } 1101} 1102 1103 1104/* Uturn supports 256 TLB entries */ 1105#define CCIO_CHAINID_SHIFT 8 1106#define CCIO_CHAINID_MASK 0xff 1107 1108/* We *can't* support JAVA (T600). Venture there at your own risk. */ 1109static const struct parisc_device_id ccio_tbl[] = { 1110 { HPHW_IOA, HVERSION_REV_ANY_ID, U2_IOA_RUNWAY, 0xb }, /* U2 */ 1111 { HPHW_IOA, HVERSION_REV_ANY_ID, UTURN_IOA_RUNWAY, 0xb }, /* UTurn */ 1112 { 0, } 1113}; 1114 1115static int ccio_probe(struct parisc_device *dev); 1116 1117static struct parisc_driver ccio_driver = { 1118 .name = "ccio", 1119 .id_table = ccio_tbl, 1120 .probe = ccio_probe, 1121}; 1122 1123/** 1124 * ccio_ioc_init - Initalize the I/O Controller 1125 * @ioc: The I/O Controller. 1126 * 1127 * Initalize the I/O Controller which includes setting up the 1128 * I/O Page Directory, the resource map, and initalizing the 1129 * U2/Uturn chip into virtual mode. 1130 */ 1131static void 1132ccio_ioc_init(struct ioc *ioc) 1133{ 1134 int i; 1135 unsigned int iov_order; 1136 u32 iova_space_size; 1137 1138 /* 1139 ** Determine IOVA Space size from memory size. 1140 ** 1141 ** Ideally, PCI drivers would register the maximum number 1142 ** of DMA they can have outstanding for each device they 1143 ** own. Next best thing would be to guess how much DMA 1144 ** can be outstanding based on PCI Class/sub-class. Both 1145 ** methods still require some "extra" to support PCI 1146 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1147 */ 1148 1149 iova_space_size = (u32) (num_physpages / count_parisc_driver(&ccio_driver)); 1150 1151 /* limit IOVA space size to 1MB-1GB */ 1152 1153 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1154 iova_space_size = 1 << (20 - PAGE_SHIFT); 1155#ifdef __LP64__ 1156 } else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1157 iova_space_size = 1 << (30 - PAGE_SHIFT); 1158#endif 1159 } 1160 1161 /* 1162 ** iova space must be log2() in size. 1163 ** thus, pdir/res_map will also be log2(). 1164 */ 1165 1166 /* We could use larger page sizes in order to *decrease* the number 1167 ** of mappings needed. (ie 8k pages means 1/2 the mappings). 1168 ** 1169 ** Note: Grant Grunder says "Using 8k I/O pages isn't trivial either 1170 ** since the pages must also be physically contiguous - typically 1171 ** this is the case under linux." 1172 */ 1173 1174 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1175 1176 /* iova_space_size is now bytes, not pages */ 1177 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1178 1179 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1180 1181 BUG_ON(ioc->pdir_size > 8 * 1024 * 1024); /* max pdir size <= 8MB */ 1182 1183 /* Verify it's a power of two */ 1184 BUG_ON((1 << get_order(ioc->pdir_size)) != (ioc->pdir_size >> PAGE_SHIFT)); 1185 1186 DBG_INIT("%s() hpa 0x%p mem %luMB IOV %dMB (%d bits)\n", 1187 __FUNCTION__, ioc->ioc_regs, 1188 (unsigned long) num_physpages >> (20 - PAGE_SHIFT), 1189 iova_space_size>>20, 1190 iov_order + PAGE_SHIFT); 1191 1192 ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL, 1193 get_order(ioc->pdir_size)); 1194 if(NULL == ioc->pdir_base) { 1195 panic("%s() could not allocate I/O Page Table\n", __FUNCTION__); 1196 } 1197 memset(ioc->pdir_base, 0, ioc->pdir_size); 1198 1199 BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned long)ioc->pdir_base); 1200 DBG_INIT(" base %p\n", ioc->pdir_base); 1201 1202 /* resource map size dictated by pdir_size */ 1203 ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3; 1204 DBG_INIT("%s() res_size 0x%x\n", __FUNCTION__, ioc->res_size); 1205 1206 ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL, 1207 get_order(ioc->res_size)); 1208 if(NULL == ioc->res_map) { 1209 panic("%s() could not allocate resource map\n", __FUNCTION__); 1210 } 1211 memset(ioc->res_map, 0, ioc->res_size); 1212 1213 /* Initialize the res_hint to 16 */ 1214 ioc->res_hint = 16; 1215 1216 /* Initialize the spinlock */ 1217 spin_lock_init(&ioc->res_lock); 1218 1219 /* 1220 ** Chainid is the upper most bits of an IOVP used to determine 1221 ** which TLB entry an IOVP will use. 1222 */ 1223 ioc->chainid_shift = get_order(iova_space_size) + PAGE_SHIFT - CCIO_CHAINID_SHIFT; 1224 DBG_INIT(" chainid_shift 0x%x\n", ioc->chainid_shift); 1225 1226 /* 1227 ** Initialize IOA hardware 1228 */ 1229 WRITE_U32(CCIO_CHAINID_MASK << ioc->chainid_shift, 1230 &ioc->ioc_regs->io_chain_id_mask); 1231 1232 WRITE_U32(virt_to_phys(ioc->pdir_base), 1233 &ioc->ioc_regs->io_pdir_base); 1234 1235 /* 1236 ** Go to "Virtual Mode" 1237 */ 1238 WRITE_U32(IOA_NORMAL_MODE, &ioc->ioc_regs->io_control); 1239 1240 /* 1241 ** Initialize all I/O TLB entries to 0 (Valid bit off). 1242 */ 1243 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_m); 1244 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_l); 1245 1246 for(i = 1 << CCIO_CHAINID_SHIFT; i ; i--) { 1247 WRITE_U32((CMD_TLB_DIRECT_WRITE | (i << ioc->chainid_shift)), 1248 &ioc->ioc_regs->io_command); 1249 } 1250} 1251 1252static void __init 1253ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr) 1254{ 1255 int result; 1256 1257 res->parent = NULL; 1258 res->flags = IORESOURCE_MEM; 1259 /* 1260 * bracing ((signed) ...) are required for 64bit kernel because 1261 * we only want to sign extend the lower 16 bits of the register. 1262 * The upper 16-bits of range registers are hardcoded to 0xffff. 1263 */ 1264 res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16); 1265 res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16) - 1); 1266 res->name = name; 1267 /* 1268 * Check if this MMIO range is disable 1269 */ 1270 if (res->end + 1 == res->start) 1271 return; 1272 1273 /* On some platforms (e.g. K-Class), we have already registered 1274 * resources for devices reported by firmware. Some are children 1275 * of ccio. 1276 * "insert" ccio ranges in the mmio hierarchy (/proc/iomem). 1277 */ 1278 result = insert_resource(&iomem_resource, res); 1279 if (result < 0) { 1280 printk(KERN_ERR "%s() failed to claim CCIO bus address space (%08lx,%08lx)\n", 1281 __FUNCTION__, res->start, res->end); 1282 } 1283} 1284 1285static void __init ccio_init_resources(struct ioc *ioc) 1286{ 1287 struct resource *res = ioc->mmio_region; 1288 char *name = kmalloc(14, GFP_KERNEL); 1289 1290 snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path); 1291 1292 ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low); 1293 ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv); 1294} 1295 1296static int new_ioc_area(struct resource *res, unsigned long size, 1297 unsigned long min, unsigned long max, unsigned long align) 1298{ 1299 if (max <= min) 1300 return -EBUSY; 1301 1302 res->start = (max - size + 1) &~ (align - 1); 1303 res->end = res->start + size; 1304 1305 /* We might be trying to expand the MMIO range to include 1306 * a child device that has already registered it's MMIO space. 1307 * Use "insert" instead of request_resource(). 1308 */ 1309 if (!insert_resource(&iomem_resource, res)) 1310 return 0; 1311 1312 return new_ioc_area(res, size, min, max - size, align); 1313} 1314 1315static int expand_ioc_area(struct resource *res, unsigned long size, 1316 unsigned long min, unsigned long max, unsigned long align) 1317{ 1318 unsigned long start, len; 1319 1320 if (!res->parent) 1321 return new_ioc_area(res, size, min, max, align); 1322 1323 start = (res->start - size) &~ (align - 1); 1324 len = res->end - start + 1; 1325 if (start >= min) { 1326 if (!adjust_resource(res, start, len)) 1327 return 0; 1328 } 1329 1330 start = res->start; 1331 len = ((size + res->end + align) &~ (align - 1)) - start; 1332 if (start + len <= max) { 1333 if (!adjust_resource(res, start, len)) 1334 return 0; 1335 } 1336 1337 return -EBUSY; 1338} 1339 1340/* 1341 * Dino calls this function. Beware that we may get called on systems 1342 * which have no IOC (725, B180, C160L, etc) but do have a Dino. 1343 * So it's legal to find no parent IOC. 1344 * 1345 * Some other issues: one of the resources in the ioc may be unassigned. 1346 */ 1347int ccio_allocate_resource(const struct parisc_device *dev, 1348 struct resource *res, unsigned long size, 1349 unsigned long min, unsigned long max, unsigned long align) 1350{ 1351 struct resource *parent = &iomem_resource; 1352 struct ioc *ioc = ccio_get_iommu(dev); 1353 if (!ioc) 1354 goto out; 1355 1356 parent = ioc->mmio_region; 1357 if (parent->parent && 1358 !allocate_resource(parent, res, size, min, max, align, NULL, NULL)) 1359 return 0; 1360 1361 if ((parent + 1)->parent && 1362 !allocate_resource(parent + 1, res, size, min, max, align, 1363 NULL, NULL)) 1364 return 0; 1365 1366 if (!expand_ioc_area(parent, size, min, max, align)) { 1367 __raw_writel(((parent->start)>>16) | 0xffff0000, 1368 &ioc->ioc_regs->io_io_low); 1369 __raw_writel(((parent->end)>>16) | 0xffff0000, 1370 &ioc->ioc_regs->io_io_high); 1371 } else if (!expand_ioc_area(parent + 1, size, min, max, align)) { 1372 parent++; 1373 __raw_writel(((parent->start)>>16) | 0xffff0000, 1374 &ioc->ioc_regs->io_io_low_hv); 1375 __raw_writel(((parent->end)>>16) | 0xffff0000, 1376 &ioc->ioc_regs->io_io_high_hv); 1377 } else { 1378 return -EBUSY; 1379 } 1380 1381 out: 1382 return allocate_resource(parent, res, size, min, max, align, NULL,NULL); 1383} 1384 1385int ccio_request_resource(const struct parisc_device *dev, 1386 struct resource *res) 1387{ 1388 struct resource *parent; 1389 struct ioc *ioc = ccio_get_iommu(dev); 1390 1391 if (!ioc) { 1392 parent = &iomem_resource; 1393 } else if ((ioc->mmio_region->start <= res->start) && 1394 (res->end <= ioc->mmio_region->end)) { 1395 parent = ioc->mmio_region; 1396 } else if (((ioc->mmio_region + 1)->start <= res->start) && 1397 (res->end <= (ioc->mmio_region + 1)->end)) { 1398 parent = ioc->mmio_region + 1; 1399 } else { 1400 return -EBUSY; 1401 } 1402 1403 /* "transparent" bus bridges need to register MMIO resources 1404 * firmware assigned them. e.g. children of hppb.c (e.g. K-class) 1405 * registered their resources in the PDC "bus walk" (See 1406 * arch/parisc/kernel/inventory.c). 1407 */ 1408 return insert_resource(parent, res); 1409} 1410 1411/** 1412 * ccio_probe - Determine if ccio should claim this device. 1413 * @dev: The device which has been found 1414 * 1415 * Determine if ccio should claim this chip (return 0) or not (return 1). 1416 * If so, initialize the chip and tell other partners in crime they 1417 * have work to do. 1418 */ 1419static int __init ccio_probe(struct parisc_device *dev) 1420{ 1421 int i; 1422 struct ioc *ioc, **ioc_p = &ioc_list; 1423 struct proc_dir_entry *info_entry, *bitmap_entry; 1424 1425 ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL); 1426 if (ioc == NULL) { 1427 printk(KERN_ERR MODULE_NAME ": memory allocation failure\n"); 1428 return 1; 1429 } 1430 1431 ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn"; 1432 1433 printk(KERN_INFO "Found %s at 0x%lx\n", ioc->name, dev->hpa.start); 1434 1435 for (i = 0; i < ioc_count; i++) { 1436 ioc_p = &(*ioc_p)->next; 1437 } 1438 *ioc_p = ioc; 1439 1440 ioc->hw_path = dev->hw_path; 1441 ioc->ioc_regs = ioremap_nocache(dev->hpa.start, 4096); 1442 ccio_ioc_init(ioc); 1443 ccio_init_resources(ioc); 1444 hppa_dma_ops = &ccio_ops; 1445 dev->dev.platform_data = kzalloc(sizeof(struct pci_hba_data), GFP_KERNEL); 1446 1447 /* if this fails, no I/O cards will work, so may as well bug */ 1448 BUG_ON(dev->dev.platform_data == NULL); 1449 HBA_DATA(dev->dev.platform_data)->iommu = ioc; 1450 1451 if (ioc_count == 0) { 1452 info_entry = create_proc_entry(MODULE_NAME, 0, proc_runway_root); 1453 if (info_entry) 1454 info_entry->proc_fops = &ccio_proc_info_fops; 1455 1456 bitmap_entry = create_proc_entry(MODULE_NAME"-bitmap", 0, proc_runway_root); 1457 if (bitmap_entry) 1458 bitmap_entry->proc_fops = &ccio_proc_bitmap_fops; 1459 } 1460 1461 ioc_count++; 1462 1463 parisc_vmerge_boundary = IOVP_SIZE; 1464 parisc_vmerge_max_size = BITS_PER_LONG * IOVP_SIZE; 1465 parisc_has_iommu(); 1466 return 0; 1467} 1468 1469/** 1470 * ccio_init - ccio initalization procedure. 1471 * 1472 * Register this driver. 1473 */ 1474void __init ccio_init(void) 1475{ 1476 register_parisc_driver(&ccio_driver); 1477} 1478