1/* 2 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for 3 * CPU modes 0 & 2. 4 * 5 * Author: Ivan Passos <ivan@cyclades.com> 6 * 7 * Copyright: (c) 2000-2001 Cyclades Corp. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * $Log: hd64572.h,v $ 15 * Revision 1.1.1.1 2007/08/03 18:52:49 rnuti 16 * Importing Linux MIPS Kernel 2.6.22 17 * 18 * Revision 3.1 2001/06/15 12:41:10 regina 19 * upping major version number 20 * 21 * Revision 1.1.1.1 2001/06/13 20:24:49 daniela 22 * PC300 initial CVS version (3.4.0-pre1) 23 * 24 * Revision 1.0 2000/01/25 ivan 25 * Initial version. 26 * 27 */ 28 29#ifndef __HD64572_H 30#define __HD64572_H 31 32/* Illegal Access Register */ 33#define ILAR 0x00 34 35/* Wait Controller Registers */ 36#define PABR0L 0x20 /* Physical Addr Boundary Register 0 L */ 37#define PABR0H 0x21 /* Physical Addr Boundary Register 0 H */ 38#define PABR1L 0x22 /* Physical Addr Boundary Register 1 L */ 39#define PABR1H 0x23 /* Physical Addr Boundary Register 1 H */ 40#define WCRL 0x24 /* Wait Control Register L */ 41#define WCRM 0x25 /* Wait Control Register M */ 42#define WCRH 0x26 /* Wait Control Register H */ 43 44/* Interrupt Registers */ 45#define IVR 0x60 /* Interrupt Vector Register */ 46#define IMVR 0x64 /* Interrupt Modified Vector Register */ 47#define ITCR 0x68 /* Interrupt Control Register */ 48#define ISR0 0x6c /* Interrupt Status Register 0 */ 49#define ISR1 0x70 /* Interrupt Status Register 1 */ 50#define IER0 0x74 /* Interrupt Enable Register 0 */ 51#define IER1 0x78 /* Interrupt Enable Register 1 */ 52 53/* Register Access Macros (chan is 0 or 1 in _any_ case) */ 54#define M_REG(reg, chan) (reg + 0x80*chan) /* MSCI */ 55#define DRX_REG(reg, chan) (reg + 0x40*chan) /* DMA Rx */ 56#define DTX_REG(reg, chan) (reg + 0x20*(2*chan + 1)) /* DMA Tx */ 57#define TRX_REG(reg, chan) (reg + 0x20*chan) /* Timer Rx */ 58#define TTX_REG(reg, chan) (reg + 0x10*(2*chan + 1)) /* Timer Tx */ 59#define ST_REG(reg, chan) (reg + 0x80*chan) /* Status Cnt */ 60#define IR0_DRX(val, chan) ((val)<<(8*(chan))) /* Int DMA Rx */ 61#define IR0_DTX(val, chan) ((val)<<(4*(2*chan + 1))) /* Int DMA Tx */ 62#define IR0_M(val, chan) ((val)<<(8*(chan))) /* Int MSCI */ 63 64/* MSCI Channel Registers */ 65#define MSCI0_OFFSET 0x00 66#define MSCI1_OFFSET 0x80 67 68#define MD0 0x138 /* Mode reg 0 */ 69#define MD1 0x139 /* Mode reg 1 */ 70#define MD2 0x13a /* Mode reg 2 */ 71#define MD3 0x13b /* Mode reg 3 */ 72#define CTL 0x130 /* Control reg */ 73#define RXS 0x13c /* RX clock source */ 74#define TXS 0x13d /* TX clock source */ 75#define EXS 0x13e /* External clock input selection */ 76#define TMCT 0x144 /* Time constant (Tx) */ 77#define TMCR 0x145 /* Time constant (Rx) */ 78#define CMD 0x128 /* Command reg */ 79#define ST0 0x118 /* Status reg 0 */ 80#define ST1 0x119 /* Status reg 1 */ 81#define ST2 0x11a /* Status reg 2 */ 82#define ST3 0x11b /* Status reg 3 */ 83#define ST4 0x11c /* Status reg 4 */ 84#define FST 0x11d /* frame Status reg */ 85#define IE0 0x120 /* Interrupt enable reg 0 */ 86#define IE1 0x121 /* Interrupt enable reg 1 */ 87#define IE2 0x122 /* Interrupt enable reg 2 */ 88#define IE4 0x124 /* Interrupt enable reg 4 */ 89#define FIE 0x125 /* Frame Interrupt enable reg */ 90#define SA0 0x140 /* Syn Address reg 0 */ 91#define SA1 0x141 /* Syn Address reg 1 */ 92#define IDL 0x142 /* Idle register */ 93#define TRBL 0x100 /* TX/RX buffer reg L */ 94#define TRBK 0x101 /* TX/RX buffer reg K */ 95#define TRBJ 0x102 /* TX/RX buffer reg J */ 96#define TRBH 0x103 /* TX/RX buffer reg H */ 97#define TRC0 0x148 /* TX Ready control reg 0 */ 98#define TRC1 0x149 /* TX Ready control reg 1 */ 99#define RRC 0x14a /* RX Ready control reg */ 100#define CST0 0x108 /* Current Status Register 0 */ 101#define CST1 0x109 /* Current Status Register 1 */ 102#define CST2 0x10a /* Current Status Register 2 */ 103#define CST3 0x10b /* Current Status Register 3 */ 104#define GPO 0x131 /* General Purpose Output Pin Ctl Reg */ 105#define TFS 0x14b /* Tx Start Threshold Ctl Reg */ 106#define TFN 0x143 /* Inter-transmit-frame Time Fill Ctl Reg */ 107#define TBN 0x110 /* Tx Buffer Number Reg */ 108#define RBN 0x111 /* Rx Buffer Number Reg */ 109#define TNR0 0x150 /* Tx DMA Request Ctl Reg 0 */ 110#define TNR1 0x151 /* Tx DMA Request Ctl Reg 1 */ 111#define TCR 0x152 /* Tx DMA Critical Request Reg */ 112#define RNR 0x154 /* Rx DMA Request Ctl Reg */ 113#define RCR 0x156 /* Rx DMA Critical Request Reg */ 114 115/* Timer Registers */ 116#define TIMER0RX_OFFSET 0x00 117#define TIMER0TX_OFFSET 0x10 118#define TIMER1RX_OFFSET 0x20 119#define TIMER1TX_OFFSET 0x30 120 121#define TCNTL 0x200 /* Timer Upcounter L */ 122#define TCNTH 0x201 /* Timer Upcounter H */ 123#define TCONRL 0x204 /* Timer Constant Register L */ 124#define TCONRH 0x205 /* Timer Constant Register H */ 125#define TCSR 0x206 /* Timer Control/Status Register */ 126#define TEPR 0x207 /* Timer Expand Prescale Register */ 127 128/* DMA registers */ 129#define PCR 0x40 /* DMA priority control reg */ 130#define DRR 0x44 /* DMA reset reg */ 131#define DMER 0x07 /* DMA Master Enable reg */ 132#define BTCR 0x08 /* Burst Tx Ctl Reg */ 133#define BOLR 0x0c /* Back-off Length Reg */ 134#define DSR_RX(chan) (0x48 + 2*chan) /* DMA Status Reg (Rx) */ 135#define DSR_TX(chan) (0x49 + 2*chan) /* DMA Status Reg (Tx) */ 136#define DIR_RX(chan) (0x4c + 2*chan) /* DMA Interrupt Enable Reg (Rx) */ 137#define DIR_TX(chan) (0x4d + 2*chan) /* DMA Interrupt Enable Reg (Tx) */ 138#define FCT_RX(chan) (0x50 + 2*chan) /* Frame End Interrupt Counter (Rx) */ 139#define FCT_TX(chan) (0x51 + 2*chan) /* Frame End Interrupt Counter (Tx) */ 140#define DMR_RX(chan) (0x54 + 2*chan) /* DMA Mode Reg (Rx) */ 141#define DMR_TX(chan) (0x55 + 2*chan) /* DMA Mode Reg (Tx) */ 142#define DCR_RX(chan) (0x58 + 2*chan) /* DMA Command Reg (Rx) */ 143#define DCR_TX(chan) (0x59 + 2*chan) /* DMA Command Reg (Tx) */ 144 145/* DMA Channel Registers */ 146#define DMAC0RX_OFFSET 0x00 147#define DMAC0TX_OFFSET 0x20 148#define DMAC1RX_OFFSET 0x40 149#define DMAC1TX_OFFSET 0x60 150 151#define DARL 0x80 /* Dest Addr Register L (single-block, RX only) */ 152#define DARH 0x81 /* Dest Addr Register H (single-block, RX only) */ 153#define DARB 0x82 /* Dest Addr Register B (single-block, RX only) */ 154#define DARBH 0x83 /* Dest Addr Register BH (single-block, RX only) */ 155#define SARL 0x80 /* Source Addr Register L (single-block, TX only) */ 156#define SARH 0x81 /* Source Addr Register H (single-block, TX only) */ 157#define SARB 0x82 /* Source Addr Register B (single-block, TX only) */ 158#define DARBH 0x83 /* Source Addr Register BH (single-block, TX only) */ 159#define BARL 0x80 /* Buffer Addr Register L (chained-block) */ 160#define BARH 0x81 /* Buffer Addr Register H (chained-block) */ 161#define BARB 0x82 /* Buffer Addr Register B (chained-block) */ 162#define BARBH 0x83 /* Buffer Addr Register BH (chained-block) */ 163#define CDAL 0x84 /* Current Descriptor Addr Register L */ 164#define CDAH 0x85 /* Current Descriptor Addr Register H */ 165#define CDAB 0x86 /* Current Descriptor Addr Register B */ 166#define CDABH 0x87 /* Current Descriptor Addr Register BH */ 167#define EDAL 0x88 /* Error Descriptor Addr Register L */ 168#define EDAH 0x89 /* Error Descriptor Addr Register H */ 169#define EDAB 0x8a /* Error Descriptor Addr Register B */ 170#define EDABH 0x8b /* Error Descriptor Addr Register BH */ 171#define BFLL 0x90 /* RX Buffer Length L (only RX) */ 172#define BFLH 0x91 /* RX Buffer Length H (only RX) */ 173#define BCRL 0x8c /* Byte Count Register L */ 174#define BCRH 0x8d /* Byte Count Register H */ 175 176/* Block Descriptor Structure */ 177typedef struct { 178 unsigned long next; /* pointer to next block descriptor */ 179 unsigned long ptbuf; /* buffer pointer */ 180 unsigned short len; /* data length */ 181 unsigned char status; /* status */ 182 unsigned char filler[5]; /* alignment filler (16 bytes) */ 183} pcsca_bd_t; 184 185/* Block Descriptor Structure */ 186typedef struct { 187 u32 cp; /* pointer to next block descriptor */ 188 u32 bp; /* buffer pointer */ 189 u16 len; /* data length */ 190 u8 stat; /* status */ 191 u8 unused; /* pads to 4-byte boundary */ 192}pkt_desc; 193 194 195/* 196 Descriptor Status definitions: 197 198 Bit Transmission Reception 199 200 7 EOM EOM 201 6 - Short Frame 202 5 - Abort 203 4 - Residual bit 204 3 Underrun Overrun 205 2 - CRC 206 1 Ownership Ownership 207 0 EOT - 208*/ 209#define DST_EOT 0x01 /* End of transmit command */ 210#define DST_OSB 0x02 /* Ownership bit */ 211#define DST_CRC 0x04 /* CRC Error */ 212#define DST_OVR 0x08 /* Overrun */ 213#define DST_UDR 0x08 /* Underrun */ 214#define DST_RBIT 0x10 /* Residual bit */ 215#define DST_ABT 0x20 /* Abort */ 216#define DST_SHRT 0x40 /* Short Frame */ 217#define DST_EOM 0x80 /* End of Message */ 218 219/* Packet Descriptor Status bits */ 220 221#define ST_TX_EOM 0x80 /* End of frame */ 222#define ST_TX_UNDRRUN 0x08 223#define ST_TX_OWNRSHP 0x02 224#define ST_TX_EOT 0x01 /* End of transmition */ 225 226#define ST_RX_EOM 0x80 /* End of frame */ 227#define ST_RX_SHORT 0x40 /* Short frame */ 228#define ST_RX_ABORT 0x20 /* Abort */ 229#define ST_RX_RESBIT 0x10 /* Residual bit */ 230#define ST_RX_OVERRUN 0x08 /* Overrun */ 231#define ST_RX_CRC 0x04 /* CRC */ 232#define ST_RX_OWNRSHP 0x02 233 234#define ST_ERROR_MASK 0x7C 235 236/* Status Counter Registers */ 237#define CMCR 0x158 /* Counter Master Ctl Reg */ 238#define TECNTL 0x160 /* Tx EOM Counter L */ 239#define TECNTM 0x161 /* Tx EOM Counter M */ 240#define TECNTH 0x162 /* Tx EOM Counter H */ 241#define TECCR 0x163 /* Tx EOM Counter Ctl Reg */ 242#define URCNTL 0x164 /* Underrun Counter L */ 243#define URCNTH 0x165 /* Underrun Counter H */ 244#define URCCR 0x167 /* Underrun Counter Ctl Reg */ 245#define RECNTL 0x168 /* Rx EOM Counter L */ 246#define RECNTM 0x169 /* Rx EOM Counter M */ 247#define RECNTH 0x16a /* Rx EOM Counter H */ 248#define RECCR 0x16b /* Rx EOM Counter Ctl Reg */ 249#define ORCNTL 0x16c /* Overrun Counter L */ 250#define ORCNTH 0x16d /* Overrun Counter H */ 251#define ORCCR 0x16f /* Overrun Counter Ctl Reg */ 252#define CECNTL 0x170 /* CRC Counter L */ 253#define CECNTH 0x171 /* CRC Counter H */ 254#define CECCR 0x173 /* CRC Counter Ctl Reg */ 255#define ABCNTL 0x174 /* Abort frame Counter L */ 256#define ABCNTH 0x175 /* Abort frame Counter H */ 257#define ABCCR 0x177 /* Abort frame Counter Ctl Reg */ 258#define SHCNTL 0x178 /* Short frame Counter L */ 259#define SHCNTH 0x179 /* Short frame Counter H */ 260#define SHCCR 0x17b /* Short frame Counter Ctl Reg */ 261#define RSCNTL 0x17c /* Residual bit Counter L */ 262#define RSCNTH 0x17d /* Residual bit Counter H */ 263#define RSCCR 0x17f /* Residual bit Counter Ctl Reg */ 264 265/* Register Programming Constants */ 266 267#define IR0_DMIC 0x00000001 268#define IR0_DMIB 0x00000002 269#define IR0_DMIA 0x00000004 270#define IR0_EFT 0x00000008 271#define IR0_DMAREQ 0x00010000 272#define IR0_TXINT 0x00020000 273#define IR0_RXINTB 0x00040000 274#define IR0_RXINTA 0x00080000 275#define IR0_TXRDY 0x00100000 276#define IR0_RXRDY 0x00200000 277 278#define MD0_CRC16_0 0x00 279#define MD0_CRC16_1 0x01 280#define MD0_CRC32 0x02 281#define MD0_CRC_CCITT 0x03 282#define MD0_CRCC0 0x04 283#define MD0_CRCC1 0x08 284#define MD0_AUTO_ENA 0x10 285#define MD0_ASYNC 0x00 286#define MD0_BY_MSYNC 0x20 287#define MD0_BY_BISYNC 0x40 288#define MD0_BY_EXT 0x60 289#define MD0_BIT_SYNC 0x80 290#define MD0_TRANSP 0xc0 291 292#define MD0_HDLC 0x80 /* Bit-sync HDLC mode */ 293 294#define MD0_CRC_NONE 0x00 295#define MD0_CRC_16_0 0x04 296#define MD0_CRC_16 0x05 297#define MD0_CRC_ITU32 0x06 298#define MD0_CRC_ITU 0x07 299 300#define MD1_NOADDR 0x00 301#define MD1_SADDR1 0x40 302#define MD1_SADDR2 0x80 303#define MD1_DADDR 0xc0 304 305#define MD2_NRZI_IEEE 0x40 306#define MD2_MANCHESTER 0x80 307#define MD2_FM_MARK 0xA0 308#define MD2_FM_SPACE 0xC0 309#define MD2_LOOPBACK 0x03 /* Local data Loopback */ 310 311#define MD2_F_DUPLEX 0x00 312#define MD2_AUTO_ECHO 0x01 313#define MD2_LOOP_HI_Z 0x02 314#define MD2_LOOP_MIR 0x03 315#define MD2_ADPLL_X8 0x00 316#define MD2_ADPLL_X16 0x08 317#define MD2_ADPLL_X32 0x10 318#define MD2_NRZ 0x00 319#define MD2_NRZI 0x20 320#define MD2_NRZ_IEEE 0x40 321#define MD2_MANCH 0x00 322#define MD2_FM1 0x20 323#define MD2_FM0 0x40 324#define MD2_FM 0x80 325 326#define CTL_RTS 0x01 327#define CTL_DTR 0x02 328#define CTL_SYN 0x04 329#define CTL_IDLC 0x10 330#define CTL_UDRNC 0x20 331#define CTL_URSKP 0x40 332#define CTL_URCT 0x80 333 334#define CTL_NORTS 0x01 335#define CTL_NODTR 0x02 336#define CTL_IDLE 0x10 337 338#define RXS_BR0 0x01 339#define RXS_BR1 0x02 340#define RXS_BR2 0x04 341#define RXS_BR3 0x08 342#define RXS_ECLK 0x00 343#define RXS_ECLK_NS 0x20 344#define RXS_IBRG 0x40 345#define RXS_PLL1 0x50 346#define RXS_PLL2 0x60 347#define RXS_PLL3 0x70 348#define RXS_DRTXC 0x80 349 350#define TXS_BR0 0x01 351#define TXS_BR1 0x02 352#define TXS_BR2 0x04 353#define TXS_BR3 0x08 354#define TXS_ECLK 0x00 355#define TXS_IBRG 0x40 356#define TXS_RCLK 0x60 357#define TXS_DTRXC 0x80 358 359#define EXS_RES0 0x01 360#define EXS_RES1 0x02 361#define EXS_RES2 0x04 362#define EXS_TES0 0x10 363#define EXS_TES1 0x20 364#define EXS_TES2 0x40 365 366#define CLK_BRG_MASK 0x0F 367#define CLK_PIN_OUT 0x80 368#define CLK_LINE 0x00 /* clock line input */ 369#define CLK_BRG 0x40 /* internal baud rate generator */ 370#define CLK_TX_RXCLK 0x60 /* TX clock from RX clock */ 371 372#define CMD_RX_RST 0x11 373#define CMD_RX_ENA 0x12 374#define CMD_RX_DIS 0x13 375#define CMD_RX_CRC_INIT 0x14 376#define CMD_RX_MSG_REJ 0x15 377#define CMD_RX_MP_SRCH 0x16 378#define CMD_RX_CRC_EXC 0x17 379#define CMD_RX_CRC_FRC 0x18 380#define CMD_TX_RST 0x01 381#define CMD_TX_ENA 0x02 382#define CMD_TX_DISA 0x03 383#define CMD_TX_CRC_INIT 0x04 384#define CMD_TX_CRC_EXC 0x05 385#define CMD_TX_EOM 0x06 386#define CMD_TX_ABORT 0x07 387#define CMD_TX_MP_ON 0x08 388#define CMD_TX_BUF_CLR 0x09 389#define CMD_TX_DISB 0x0b 390#define CMD_CH_RST 0x21 391#define CMD_SRCH_MODE 0x31 392#define CMD_NOP 0x00 393 394#define CMD_RESET 0x21 395#define CMD_TX_ENABLE 0x02 396#define CMD_RX_ENABLE 0x12 397 398#define ST0_RXRDY 0x01 399#define ST0_TXRDY 0x02 400#define ST0_RXINTB 0x20 401#define ST0_RXINTA 0x40 402#define ST0_TXINT 0x80 403 404#define ST1_IDLE 0x01 405#define ST1_ABORT 0x02 406#define ST1_CDCD 0x04 407#define ST1_CCTS 0x08 408#define ST1_SYN_FLAG 0x10 409#define ST1_CLMD 0x20 410#define ST1_TXIDLE 0x40 411#define ST1_UDRN 0x80 412 413#define ST2_CRCE 0x04 414#define ST2_ONRN 0x08 415#define ST2_RBIT 0x10 416#define ST2_ABORT 0x20 417#define ST2_SHORT 0x40 418#define ST2_EOM 0x80 419 420#define ST3_RX_ENA 0x01 421#define ST3_TX_ENA 0x02 422#define ST3_DCD 0x04 423#define ST3_CTS 0x08 424#define ST3_SRCH_MODE 0x10 425#define ST3_SLOOP 0x20 426#define ST3_GPI 0x80 427 428#define ST4_RDNR 0x01 429#define ST4_RDCR 0x02 430#define ST4_TDNR 0x04 431#define ST4_TDCR 0x08 432#define ST4_OCLM 0x20 433#define ST4_CFT 0x40 434#define ST4_CGPI 0x80 435 436#define FST_CRCEF 0x04 437#define FST_OVRNF 0x08 438#define FST_RBIF 0x10 439#define FST_ABTF 0x20 440#define FST_SHRTF 0x40 441#define FST_EOMF 0x80 442 443#define IE0_RXRDY 0x01 444#define IE0_TXRDY 0x02 445#define IE0_RXINTB 0x20 446#define IE0_RXINTA 0x40 447#define IE0_TXINT 0x80 448#define IE0_UDRN 0x00008000 /* TX underrun MSCI interrupt enable */ 449#define IE0_CDCD 0x00000400 /* CD level change interrupt enable */ 450 451#define IE1_IDLD 0x01 452#define IE1_ABTD 0x02 453#define IE1_CDCD 0x04 454#define IE1_CCTS 0x08 455#define IE1_SYNCD 0x10 456#define IE1_CLMD 0x20 457#define IE1_IDL 0x40 458#define IE1_UDRN 0x80 459 460#define IE2_CRCE 0x04 461#define IE2_OVRN 0x08 462#define IE2_RBIT 0x10 463#define IE2_ABT 0x20 464#define IE2_SHRT 0x40 465#define IE2_EOM 0x80 466 467#define IE4_RDNR 0x01 468#define IE4_RDCR 0x02 469#define IE4_TDNR 0x04 470#define IE4_TDCR 0x08 471#define IE4_OCLM 0x20 472#define IE4_CFT 0x40 473#define IE4_CGPI 0x80 474 475#define FIE_CRCEF 0x04 476#define FIE_OVRNF 0x08 477#define FIE_RBIF 0x10 478#define FIE_ABTF 0x20 479#define FIE_SHRTF 0x40 480#define FIE_EOMF 0x80 481 482#define DSR_DWE 0x01 483#define DSR_DE 0x02 484#define DSR_REF 0x04 485#define DSR_UDRF 0x04 486#define DSR_COA 0x08 487#define DSR_COF 0x10 488#define DSR_BOF 0x20 489#define DSR_EOM 0x40 490#define DSR_EOT 0x80 491 492#define DIR_REF 0x04 493#define DIR_UDRF 0x04 494#define DIR_COA 0x08 495#define DIR_COF 0x10 496#define DIR_BOF 0x20 497#define DIR_EOM 0x40 498#define DIR_EOT 0x80 499 500#define DIR_REFE 0x04 501#define DIR_UDRFE 0x04 502#define DIR_COAE 0x08 503#define DIR_COFE 0x10 504#define DIR_BOFE 0x20 505#define DIR_EOME 0x40 506#define DIR_EOTE 0x80 507 508#define DMR_CNTE 0x02 509#define DMR_NF 0x04 510#define DMR_SEOME 0x08 511#define DMR_TMOD 0x10 512 513#define DMER_DME 0x80 /* DMA Master Enable */ 514 515#define DCR_SW_ABT 0x01 516#define DCR_FCT_CLR 0x02 517 518#define DCR_ABORT 0x01 519#define DCR_CLEAR_EOF 0x02 520 521#define PCR_COTE 0x80 522#define PCR_PR0 0x01 523#define PCR_PR1 0x02 524#define PCR_PR2 0x04 525#define PCR_CCC 0x08 526#define PCR_BRC 0x10 527#define PCR_OSB 0x40 528#define PCR_BURST 0x80 529 530#endif /* (__HD64572_H) */ 531