1/************************************************************************ 2 * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC 3 * Copyright(c) 2002-2007 Neterion Inc. 4 5 * This software may be used and distributed according to the terms of 6 * the GNU General Public License (GPL), incorporated herein by reference. 7 * Drivers based on or derived from this code fall under the GPL and must 8 * retain the authorship, copyright and license notice. This file is not 9 * a complete program and may only be used when the entire operating 10 * system is licensed under the GPL. 11 * See the file COPYING in this distribution for more information. 12 ************************************************************************/ 13#ifndef _REGS_H 14#define _REGS_H 15 16#define TBD 0 17 18struct XENA_dev_config { 19/* Convention: mHAL_XXX is mask, vHAL_XXX is value */ 20 21/* General Control-Status Registers */ 22 u64 general_int_status; 23#define GEN_INTR_TXPIC BIT(0) 24#define GEN_INTR_TXDMA BIT(1) 25#define GEN_INTR_TXMAC BIT(2) 26#define GEN_INTR_TXXGXS BIT(3) 27#define GEN_INTR_TXTRAFFIC BIT(8) 28#define GEN_INTR_RXPIC BIT(32) 29#define GEN_INTR_RXDMA BIT(33) 30#define GEN_INTR_RXMAC BIT(34) 31#define GEN_INTR_MC BIT(35) 32#define GEN_INTR_RXXGXS BIT(36) 33#define GEN_INTR_RXTRAFFIC BIT(40) 34#define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \ 35 GEN_INTR_TXDMA | GEN_INTR_RXDMA | \ 36 GEN_INTR_TXMAC | GEN_INTR_RXMAC | \ 37 GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \ 38 GEN_INTR_MC 39 40 u64 general_int_mask; 41 42 u8 unused0[0x100 - 0x10]; 43 44 u64 sw_reset; 45/* XGXS must be removed from reset only once. */ 46#define SW_RESET_XENA vBIT(0xA5,0,8) 47#define SW_RESET_FLASH vBIT(0xA5,8,8) 48#define SW_RESET_EOI vBIT(0xA5,16,8) 49#define SW_RESET_ALL (SW_RESET_XENA | \ 50 SW_RESET_FLASH | \ 51 SW_RESET_EOI) 52/* The SW_RESET register must read this value after a successful reset. */ 53#define SW_RESET_RAW_VAL 0xA5000000 54 55 56 u64 adapter_status; 57#define ADAPTER_STATUS_TDMA_READY BIT(0) 58#define ADAPTER_STATUS_RDMA_READY BIT(1) 59#define ADAPTER_STATUS_PFC_READY BIT(2) 60#define ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3) 61#define ADAPTER_STATUS_PIC_QUIESCENT BIT(5) 62#define ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6) 63#define ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7) 64#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8) 65#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8) 66#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8) 67#define ADAPTER_STATUS_MC_DRAM_READY BIT(24) 68#define ADAPTER_STATUS_MC_QUEUES_READY BIT(25) 69#define ADAPTER_STATUS_M_PLL_LOCK BIT(30) 70#define ADAPTER_STATUS_P_PLL_LOCK BIT(31) 71 72 u64 adapter_control; 73#define ADAPTER_CNTL_EN BIT(7) 74#define ADAPTER_EOI_TX_ON BIT(15) 75#define ADAPTER_LED_ON BIT(23) 76#define ADAPTER_UDPI(val) vBIT(val,36,4) 77#define ADAPTER_WAIT_INT BIT(48) 78#define ADAPTER_ECC_EN BIT(55) 79 80 u64 serr_source; 81#define SERR_SOURCE_PIC BIT(0) 82#define SERR_SOURCE_TXDMA BIT(1) 83#define SERR_SOURCE_RXDMA BIT(2) 84#define SERR_SOURCE_MAC BIT(3) 85#define SERR_SOURCE_MC BIT(4) 86#define SERR_SOURCE_XGXS BIT(5) 87#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \ 88 SERR_SOURCE_TXDMA | \ 89 SERR_SOURCE_RXDMA | \ 90 SERR_SOURCE_MAC | \ 91 SERR_SOURCE_MC | \ 92 SERR_SOURCE_XGXS) 93 94 u64 pci_mode; 95#define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60) 96#define PCI_MODE_PCI_33 0 97#define PCI_MODE_PCI_66 0x1 98#define PCI_MODE_PCIX_M1_66 0x2 99#define PCI_MODE_PCIX_M1_100 0x3 100#define PCI_MODE_PCIX_M1_133 0x4 101#define PCI_MODE_PCIX_M2_66 0x5 102#define PCI_MODE_PCIX_M2_100 0x6 103#define PCI_MODE_PCIX_M2_133 0x7 104#define PCI_MODE_UNSUPPORTED BIT(0) 105#define PCI_MODE_32_BITS BIT(8) 106#define PCI_MODE_UNKNOWN_MODE BIT(9) 107 108 u8 unused_0[0x800 - 0x128]; 109 110/* PCI-X Controller registers */ 111 u64 pic_int_status; 112 u64 pic_int_mask; 113#define PIC_INT_TX BIT(0) 114#define PIC_INT_FLSH BIT(1) 115#define PIC_INT_MDIO BIT(2) 116#define PIC_INT_IIC BIT(3) 117#define PIC_INT_GPIO BIT(4) 118#define PIC_INT_RX BIT(32) 119 120 u64 txpic_int_reg; 121 u64 txpic_int_mask; 122#define PCIX_INT_REG_ECC_SG_ERR BIT(0) 123#define PCIX_INT_REG_ECC_DB_ERR BIT(1) 124#define PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8) 125#define PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9) 126#define PCIX_INT_REG_INI_TX_FSM_SERR BIT(10) 127#define PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11) 128#define PCIX_INT_REG_TRT_FSM_SERR BIT(13) 129#define PCIX_INT_REG_SRT_FSM_SERR BIT(14) 130#define PCIX_INT_REG_PIFR_FSM_SERR BIT(15) 131#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21) 132#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23) 133#define PCIX_INT_REG_INI_RX_FSM_SERR BIT(48) 134#define PCIX_INT_REG_RA_RX_FSM_SERR BIT(50) 135/* 136#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52) 137#define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54) 138#define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58) 139*/ 140 u64 txpic_alarms; 141 u64 rxpic_int_reg; 142 u64 rxpic_int_mask; 143 u64 rxpic_alarms; 144 145 u64 flsh_int_reg; 146 u64 flsh_int_mask; 147#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63) 148#define PIC_FLSH_INT_REG_ERR BIT(62) 149 u64 flash_alarms; 150 151 u64 mdio_int_reg; 152 u64 mdio_int_mask; 153#define MDIO_INT_REG_MDIO_BUS_ERR BIT(0) 154#define MDIO_INT_REG_DTX_BUS_ERR BIT(8) 155#define MDIO_INT_REG_LASI BIT(39) 156 u64 mdio_alarms; 157 158 u64 iic_int_reg; 159 u64 iic_int_mask; 160#define IIC_INT_REG_BUS_FSM_ERR BIT(4) 161#define IIC_INT_REG_BIT_FSM_ERR BIT(5) 162#define IIC_INT_REG_CYCLE_FSM_ERR BIT(6) 163#define IIC_INT_REG_REQ_FSM_ERR BIT(7) 164#define IIC_INT_REG_ACK_ERR BIT(8) 165 u64 iic_alarms; 166 167 u8 unused4[0x08]; 168 169 u64 gpio_int_reg; 170#define GPIO_INT_REG_DP_ERR_INT BIT(0) 171#define GPIO_INT_REG_LINK_DOWN BIT(1) 172#define GPIO_INT_REG_LINK_UP BIT(2) 173 u64 gpio_int_mask; 174#define GPIO_INT_MASK_LINK_DOWN BIT(1) 175#define GPIO_INT_MASK_LINK_UP BIT(2) 176 u64 gpio_alarms; 177 178 u8 unused5[0x38]; 179 180 u64 tx_traffic_int; 181#define TX_TRAFFIC_INT_n(n) BIT(n) 182 u64 tx_traffic_mask; 183 184 u64 rx_traffic_int; 185#define RX_TRAFFIC_INT_n(n) BIT(n) 186 u64 rx_traffic_mask; 187 188/* PIC Control registers */ 189 u64 pic_control; 190#define PIC_CNTL_RX_ALARM_MAP_1 BIT(0) 191#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5) 192 193 u64 swapper_ctrl; 194#define SWAPPER_CTRL_PIF_R_FE BIT(0) 195#define SWAPPER_CTRL_PIF_R_SE BIT(1) 196#define SWAPPER_CTRL_PIF_W_FE BIT(8) 197#define SWAPPER_CTRL_PIF_W_SE BIT(9) 198#define SWAPPER_CTRL_TXP_FE BIT(16) 199#define SWAPPER_CTRL_TXP_SE BIT(17) 200#define SWAPPER_CTRL_TXD_R_FE BIT(18) 201#define SWAPPER_CTRL_TXD_R_SE BIT(19) 202#define SWAPPER_CTRL_TXD_W_FE BIT(20) 203#define SWAPPER_CTRL_TXD_W_SE BIT(21) 204#define SWAPPER_CTRL_TXF_R_FE BIT(22) 205#define SWAPPER_CTRL_TXF_R_SE BIT(23) 206#define SWAPPER_CTRL_RXD_R_FE BIT(32) 207#define SWAPPER_CTRL_RXD_R_SE BIT(33) 208#define SWAPPER_CTRL_RXD_W_FE BIT(34) 209#define SWAPPER_CTRL_RXD_W_SE BIT(35) 210#define SWAPPER_CTRL_RXF_W_FE BIT(36) 211#define SWAPPER_CTRL_RXF_W_SE BIT(37) 212#define SWAPPER_CTRL_XMSI_FE BIT(40) 213#define SWAPPER_CTRL_XMSI_SE BIT(41) 214#define SWAPPER_CTRL_STATS_FE BIT(48) 215#define SWAPPER_CTRL_STATS_SE BIT(49) 216 217 u64 pif_rd_swapper_fb; 218#define IF_RD_SWAPPER_FB 0x0123456789ABCDEF 219 220 u64 scheduled_int_ctrl; 221#define SCHED_INT_CTRL_TIMER_EN BIT(0) 222#define SCHED_INT_CTRL_ONE_SHOT BIT(1) 223#define SCHED_INT_CTRL_INT2MSI TBD 224#define SCHED_INT_PERIOD TBD 225 226 u64 txreqtimeout; 227#define TXREQTO_VAL(val) vBIT(val,0,32) 228#define TXREQTO_EN BIT(63) 229 230 u64 statsreqtimeout; 231#define STATREQTO_VAL(n) TBD 232#define STATREQTO_EN BIT(63) 233 234 u64 read_retry_delay; 235 u64 read_retry_acceleration; 236 u64 write_retry_delay; 237 u64 write_retry_acceleration; 238 239 u64 xmsi_control; 240 u64 xmsi_access; 241 u64 xmsi_address; 242 u64 xmsi_data; 243 244 u64 rx_mat; 245#define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8) 246 247 u8 unused6[0x8]; 248 249 u64 tx_mat0_n[0x8]; 250#define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8) 251 252 u8 unused_1[0x8]; 253 u64 stat_byte_cnt; 254#define STAT_BC(n) vBIT(n,4,12) 255 256 /* Automated statistics collection */ 257 u64 stat_cfg; 258#define STAT_CFG_STAT_EN BIT(0) 259#define STAT_CFG_ONE_SHOT_EN BIT(1) 260#define STAT_CFG_STAT_NS_EN BIT(8) 261#define STAT_CFG_STAT_RO BIT(9) 262#define STAT_TRSF_PER(n) TBD 263#define PER_SEC 0x208d5 264#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32) 265#define SET_UPDT_CLICKS(val) vBIT(val, 32, 32) 266 267 u64 stat_addr; 268 269 /* General Configuration */ 270 u64 mdio_control; 271#define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16) 272#define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5) 273#define MDIO_MMD_PMA_DEV_ADDR 0x1 274#define MDIO_MMD_PMD_DEV_ADDR 0x1 275#define MDIO_MMD_WIS_DEV_ADDR 0x2 276#define MDIO_MMD_PCS_DEV_ADDR 0x3 277#define MDIO_MMD_PHYXS_DEV_ADDR 0x4 278#define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5) 279#define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4) 280#define MDIO_OP(val) vBIT(val, 60, 2) 281#define MDIO_OP_ADDR_TRANS 0x0 282#define MDIO_OP_WRITE_TRANS 0x1 283#define MDIO_OP_READ_POST_INC_TRANS 0x2 284#define MDIO_OP_READ_TRANS 0x3 285#define MDIO_MDIO_DATA(val) vBIT(val, 32, 16) 286 287 u64 dtx_control; 288 289 u64 i2c_control; 290#define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) 291#define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) 292#define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) 293#define I2C_CONTROL_READ BIT(24) 294#define I2C_CONTROL_NACK BIT(25) 295#define I2C_CONTROL_CNTL_START vBIT(0xE,28,4) 296#define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) 297#define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) 298#define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) 299 300 u64 gpio_control; 301#define GPIO_CTRL_GPIO_0 BIT(8) 302 u64 misc_control; 303#define FAULT_BEHAVIOUR BIT(0) 304#define EXT_REQ_EN BIT(1) 305#define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3) 306 307 u8 unused7_1[0x230 - 0x208]; 308 309 u64 pic_control2; 310 u64 ini_dperr_ctrl; 311 312 u64 wreq_split_mask; 313#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12) 314 315 u8 unused7_2[0x800 - 0x248]; 316 317/* TxDMA registers */ 318 u64 txdma_int_status; 319 u64 txdma_int_mask; 320#define TXDMA_PFC_INT BIT(0) 321#define TXDMA_TDA_INT BIT(1) 322#define TXDMA_PCC_INT BIT(2) 323#define TXDMA_TTI_INT BIT(3) 324#define TXDMA_LSO_INT BIT(4) 325#define TXDMA_TPA_INT BIT(5) 326#define TXDMA_SM_INT BIT(6) 327 u64 pfc_err_reg; 328 u64 pfc_err_mask; 329 u64 pfc_err_alarm; 330 331 u64 tda_err_reg; 332 u64 tda_err_mask; 333 u64 tda_err_alarm; 334 335 u64 pcc_err_reg; 336#define PCC_FB_ECC_DB_ERR vBIT(0xFF, 16, 8) 337#define PCC_ENABLE_FOUR vBIT(0x0F,0,8) 338 339 u64 pcc_err_mask; 340 u64 pcc_err_alarm; 341 342 u64 tti_err_reg; 343 u64 tti_err_mask; 344 u64 tti_err_alarm; 345 346 u64 lso_err_reg; 347 u64 lso_err_mask; 348 u64 lso_err_alarm; 349 350 u64 tpa_err_reg; 351 u64 tpa_err_mask; 352 u64 tpa_err_alarm; 353 354 u64 sm_err_reg; 355 u64 sm_err_mask; 356 u64 sm_err_alarm; 357 358 u8 unused8[0x100 - 0xB8]; 359 360/* TxDMA arbiter */ 361 u64 tx_dma_wrap_stat; 362 363/* Tx FIFO controller */ 364#define X_MAX_FIFOS 8 365#define X_FIFO_MAX_LEN 0x1FFF /*8191 */ 366 u64 tx_fifo_partition_0; 367#define TX_FIFO_PARTITION_EN BIT(0) 368#define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) 369#define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) 370#define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) 371#define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 ) 372 373 u64 tx_fifo_partition_1; 374#define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3) 375#define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13) 376#define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3) 377#define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13) 378 379 u64 tx_fifo_partition_2; 380#define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3) 381#define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13) 382#define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3) 383#define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13) 384 385 u64 tx_fifo_partition_3; 386#define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3) 387#define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13) 388#define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3) 389#define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13) 390 391#define TX_FIFO_PARTITION_PRI_0 0 /* highest */ 392#define TX_FIFO_PARTITION_PRI_1 1 393#define TX_FIFO_PARTITION_PRI_2 2 394#define TX_FIFO_PARTITION_PRI_3 3 395#define TX_FIFO_PARTITION_PRI_4 4 396#define TX_FIFO_PARTITION_PRI_5 5 397#define TX_FIFO_PARTITION_PRI_6 6 398#define TX_FIFO_PARTITION_PRI_7 7 /* lowest */ 399 400 u64 tx_w_round_robin_0; 401 u64 tx_w_round_robin_1; 402 u64 tx_w_round_robin_2; 403 u64 tx_w_round_robin_3; 404 u64 tx_w_round_robin_4; 405 406 u64 tti_command_mem; 407#define TTI_CMD_MEM_WE BIT(7) 408#define TTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 409#define TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15) 410#define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) 411 412 u64 tti_data1_mem; 413#define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) 414#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) 415#define TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38) 416#define TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39) 417#define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) 418#define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) 419#define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) 420 421 u64 tti_data2_mem; 422#define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16) 423#define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16) 424#define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16) 425#define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16) 426 427/* Tx Protocol assist */ 428 u64 tx_pa_cfg; 429#define TX_PA_CFG_IGNORE_FRM_ERR BIT(1) 430#define TX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 431#define TX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 432#define TX_PA_CFG_IGNORE_L2_ERR BIT(6) 433#define RX_PA_CFG_STRIP_VLAN_TAG BIT(15) 434 435/* Recent add, used only debug purposes. */ 436 u64 pcc_enable; 437 438 u8 unused9[0x700 - 0x178]; 439 440 u64 txdma_debug_ctrl; 441 442 u8 unused10[0x1800 - 0x1708]; 443 444/* RxDMA Registers */ 445 u64 rxdma_int_status; 446 u64 rxdma_int_mask; 447#define RXDMA_INT_RC_INT_M BIT(0) 448#define RXDMA_INT_RPA_INT_M BIT(1) 449#define RXDMA_INT_RDA_INT_M BIT(2) 450#define RXDMA_INT_RTI_INT_M BIT(3) 451 452 u64 rda_err_reg; 453 u64 rda_err_mask; 454 u64 rda_err_alarm; 455 456 u64 rc_err_reg; 457 u64 rc_err_mask; 458 u64 rc_err_alarm; 459 460 u64 prc_pcix_err_reg; 461 u64 prc_pcix_err_mask; 462 u64 prc_pcix_err_alarm; 463 464 u64 rpa_err_reg; 465 u64 rpa_err_mask; 466 u64 rpa_err_alarm; 467 468 u64 rti_err_reg; 469 u64 rti_err_mask; 470 u64 rti_err_alarm; 471 472 u8 unused11[0x100 - 0x88]; 473 474/* DMA arbiter */ 475 u64 rx_queue_priority; 476#define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3) 477#define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3) 478#define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3) 479#define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3) 480#define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3) 481#define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3) 482#define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3) 483#define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3) 484 485#define RX_QUEUE_PRI_0 0 /* highest */ 486#define RX_QUEUE_PRI_1 1 487#define RX_QUEUE_PRI_2 2 488#define RX_QUEUE_PRI_3 3 489#define RX_QUEUE_PRI_4 4 490#define RX_QUEUE_PRI_5 5 491#define RX_QUEUE_PRI_6 6 492#define RX_QUEUE_PRI_7 7 /* lowest */ 493 494 u64 rx_w_round_robin_0; 495 u64 rx_w_round_robin_1; 496 u64 rx_w_round_robin_2; 497 u64 rx_w_round_robin_3; 498 u64 rx_w_round_robin_4; 499 500 /* Per-ring controller regs */ 501#define RX_MAX_RINGS 8 502 u64 prc_rxd0_n[RX_MAX_RINGS]; 503 u64 prc_ctrl_n[RX_MAX_RINGS]; 504#define PRC_CTRL_RC_ENABLED BIT(7) 505#define PRC_CTRL_RING_MODE (BIT(14)|BIT(15)) 506#define PRC_CTRL_RING_MODE_1 vBIT(0,14,2) 507#define PRC_CTRL_RING_MODE_3 vBIT(1,14,2) 508#define PRC_CTRL_RING_MODE_5 vBIT(2,14,2) 509#define PRC_CTRL_RING_MODE_x vBIT(3,14,2) 510#define PRC_CTRL_NO_SNOOP (BIT(22)|BIT(23)) 511#define PRC_CTRL_NO_SNOOP_DESC BIT(22) 512#define PRC_CTRL_NO_SNOOP_BUFF BIT(23) 513#define PRC_CTRL_BIMODAL_INTERRUPT BIT(37) 514#define PRC_CTRL_GROUP_READS BIT(38) 515#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) 516 517 u64 prc_alarm_action; 518#define PRC_ALARM_ACTION_RR_R0_STOP BIT(3) 519#define PRC_ALARM_ACTION_RW_R0_STOP BIT(7) 520#define PRC_ALARM_ACTION_RR_R1_STOP BIT(11) 521#define PRC_ALARM_ACTION_RW_R1_STOP BIT(15) 522#define PRC_ALARM_ACTION_RR_R2_STOP BIT(19) 523#define PRC_ALARM_ACTION_RW_R2_STOP BIT(23) 524#define PRC_ALARM_ACTION_RR_R3_STOP BIT(27) 525#define PRC_ALARM_ACTION_RW_R3_STOP BIT(31) 526#define PRC_ALARM_ACTION_RR_R4_STOP BIT(35) 527#define PRC_ALARM_ACTION_RW_R4_STOP BIT(39) 528#define PRC_ALARM_ACTION_RR_R5_STOP BIT(43) 529#define PRC_ALARM_ACTION_RW_R5_STOP BIT(47) 530#define PRC_ALARM_ACTION_RR_R6_STOP BIT(51) 531#define PRC_ALARM_ACTION_RW_R6_STOP BIT(55) 532#define PRC_ALARM_ACTION_RR_R7_STOP BIT(59) 533#define PRC_ALARM_ACTION_RW_R7_STOP BIT(63) 534 535/* Receive traffic interrupts */ 536 u64 rti_command_mem; 537#define RTI_CMD_MEM_WE BIT(7) 538#define RTI_CMD_MEM_STROBE BIT(15) 539#define RTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 540#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15) 541#define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) 542 543 u64 rti_data1_mem; 544#define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) 545#define RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38) 546#define RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39) 547#define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) 548#define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) 549#define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) 550 551 u64 rti_data2_mem; 552#define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16) 553#define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16) 554#define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16) 555#define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) 556 557 u64 rx_pa_cfg; 558#define RX_PA_CFG_IGNORE_FRM_ERR BIT(1) 559#define RX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 560#define RX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 561#define RX_PA_CFG_IGNORE_L2_ERR BIT(6) 562 563 u64 unused_11_1; 564 565 u64 ring_bump_counter1; 566 u64 ring_bump_counter2; 567 568 u8 unused12[0x700 - 0x1F0]; 569 570 u64 rxdma_debug_ctrl; 571 572 u8 unused13[0x2000 - 0x1f08]; 573 574/* Media Access Controller Register */ 575 u64 mac_int_status; 576 u64 mac_int_mask; 577#define MAC_INT_STATUS_TMAC_INT BIT(0) 578#define MAC_INT_STATUS_RMAC_INT BIT(1) 579 580 u64 mac_tmac_err_reg; 581#define TMAC_ERR_REG_TMAC_ECC_DB_ERR BIT(15) 582#define TMAC_ERR_REG_TMAC_TX_BUF_OVRN BIT(23) 583#define TMAC_ERR_REG_TMAC_TX_CRI_ERR BIT(31) 584 u64 mac_tmac_err_mask; 585 u64 mac_tmac_err_alarm; 586 587 u64 mac_rmac_err_reg; 588#define RMAC_ERR_REG_RX_BUFF_OVRN BIT(0) 589#define RMAC_ERR_REG_RTS_ECC_DB_ERR BIT(14) 590#define RMAC_ERR_REG_ECC_DB_ERR BIT(15) 591#define RMAC_LINK_STATE_CHANGE_INT BIT(31) 592 u64 mac_rmac_err_mask; 593 u64 mac_rmac_err_alarm; 594 595 u8 unused14[0x100 - 0x40]; 596 597 u64 mac_cfg; 598#define MAC_CFG_TMAC_ENABLE BIT(0) 599#define MAC_CFG_RMAC_ENABLE BIT(1) 600#define MAC_CFG_LAN_NOT_WAN BIT(2) 601#define MAC_CFG_TMAC_LOOPBACK BIT(3) 602#define MAC_CFG_TMAC_APPEND_PAD BIT(4) 603#define MAC_CFG_RMAC_STRIP_FCS BIT(5) 604#define MAC_CFG_RMAC_STRIP_PAD BIT(6) 605#define MAC_CFG_RMAC_PROM_ENABLE BIT(7) 606#define MAC_RMAC_DISCARD_PFRM BIT(8) 607#define MAC_RMAC_BCAST_ENABLE BIT(9) 608#define MAC_RMAC_ALL_ADDR_ENABLE BIT(10) 609#define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) 610 611 u64 tmac_avg_ipg; 612#define TMAC_AVG_IPG(val) vBIT(val,0,8) 613 614 u64 rmac_max_pyld_len; 615#define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14) 616#define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14) 617#define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14) 618 619 u64 rmac_err_cfg; 620#define RMAC_ERR_FCS BIT(0) 621#define RMAC_ERR_FCS_ACCEPT BIT(1) 622#define RMAC_ERR_TOO_LONG BIT(1) 623#define RMAC_ERR_TOO_LONG_ACCEPT BIT(1) 624#define RMAC_ERR_RUNT BIT(2) 625#define RMAC_ERR_RUNT_ACCEPT BIT(2) 626#define RMAC_ERR_LEN_MISMATCH BIT(3) 627#define RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3) 628 629 u64 rmac_cfg_key; 630#define RMAC_CFG_KEY(val) vBIT(val,0,16) 631 632#define MAX_MAC_ADDRESSES 16 633#define MAX_MC_ADDRESSES 32 /* Multicast addresses */ 634#define MAC_MAC_ADDR_START_OFFSET 0 635#define MAC_MC_ADDR_START_OFFSET 16 636#define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */ 637 u64 rmac_addr_cmd_mem; 638#define RMAC_ADDR_CMD_MEM_WE BIT(7) 639#define RMAC_ADDR_CMD_MEM_RD 0 640#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15) 641#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15) 642#define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) 643 644 u64 rmac_addr_data0_mem; 645#define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) 646#define RMAC_ADDR_DATA0_MEM_USER BIT(48) 647 648 u64 rmac_addr_data1_mem; 649#define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) 650 651 u8 unused15[0x8]; 652 653/* 654 u64 rmac_addr_cfg; 655#define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) 656#define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) 657#define RMAC_ADDR_BCAST_EN vBIT(0)_48 658#define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49 659*/ 660 u64 tmac_ipg_cfg; 661 662 u64 rmac_pause_cfg; 663#define RMAC_PAUSE_GEN BIT(0) 664#define RMAC_PAUSE_GEN_ENABLE BIT(0) 665#define RMAC_PAUSE_RX BIT(1) 666#define RMAC_PAUSE_RX_ENABLE BIT(1) 667#define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16) 668#define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) 669 670 u64 rmac_red_cfg; 671 672 u64 rmac_red_rate_q0q3; 673 u64 rmac_red_rate_q4q7; 674 675 u64 mac_link_util; 676#define MAC_TX_LINK_UTIL vBIT(0xFE,1,7) 677#define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4) 678#define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4) 679#define MAC_RX_LINK_UTIL vBIT(0xFE,33,7) 680#define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4) 681#define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4) 682 683#define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \ 684 MAC_RX_LINK_UTIL_DISABLE 685 686 u64 rmac_invalid_ipg; 687 688/* rx traffic steering */ 689#define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) 690 u64 rts_frm_len_n[8]; 691 692 u64 rts_qos_steering; 693 694#define MAX_DIX_MAP 4 695 u64 rts_dix_map_n[MAX_DIX_MAP]; 696#define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) 697#define RTS_DIX_MAP_SCW(val) BIT(val,21) 698 699 u64 rts_q_alternates; 700 u64 rts_default_q; 701 702 u64 rts_ctrl; 703#define RTS_CTRL_IGNORE_SNAP_OUI BIT(2) 704#define RTS_CTRL_IGNORE_LLC_CTRL BIT(3) 705 706 u64 rts_pn_cam_ctrl; 707#define RTS_PN_CAM_CTRL_WE BIT(7) 708#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15) 709#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15) 710#define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) 711 u64 rts_pn_cam_data; 712#define RTS_PN_CAM_DATA_TCP_SELECT BIT(7) 713#define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) 714#define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) 715 716 u64 rts_ds_mem_ctrl; 717#define RTS_DS_MEM_CTRL_WE BIT(7) 718#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15) 719#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15) 720#define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) 721 u64 rts_ds_mem_data; 722#define RTS_DS_MEM_DATA(n) vBIT(n,0,8) 723 724 u8 unused16[0x700 - 0x220]; 725 726 u64 mac_debug_ctrl; 727#define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL 728 729 u8 unused17[0x2800 - 0x2708]; 730 731/* memory controller registers */ 732 u64 mc_int_status; 733#define MC_INT_STATUS_MC_INT BIT(0) 734 u64 mc_int_mask; 735#define MC_INT_MASK_MC_INT BIT(0) 736 737 u64 mc_err_reg; 738#define MC_ERR_REG_ECC_DB_ERR_L BIT(14) 739#define MC_ERR_REG_ECC_DB_ERR_U BIT(15) 740#define MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18) 741#define MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20) 742#define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22) 743#define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23) 744#define MC_ERR_REG_SM_ERR BIT(31) 745#define MC_ERR_REG_ECC_ALL_SNG (BIT(2) | BIT(3) | BIT(4) | BIT(5) |\ 746 BIT(6) | BIT(7) | BIT(17) | BIT(19)) 747#define MC_ERR_REG_ECC_ALL_DBL (BIT(10) | BIT(11) | BIT(12) |\ 748 BIT(13) | BIT(14) | BIT(15) |\ 749 BIT(18) | BIT(20)) 750 u64 mc_err_mask; 751 u64 mc_err_alarm; 752 753 u8 unused18[0x100 - 0x28]; 754 755/* MC configuration */ 756 u64 rx_queue_cfg; 757#define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8) 758#define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8) 759#define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8) 760#define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8) 761#define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8) 762#define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8) 763#define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8) 764#define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) 765 766 u64 mc_rldram_mrs; 767#define MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39) 768#define MC_RLDRAM_MRS_ENABLE BIT(47) 769 770 u64 mc_rldram_interleave; 771 772 u64 mc_pause_thresh_q0q3; 773 u64 mc_pause_thresh_q4q7; 774 775 u64 mc_red_thresh_q[8]; 776 777 u8 unused19[0x200 - 0x168]; 778 u64 mc_rldram_ref_per; 779 u8 unused20[0x220 - 0x208]; 780 u64 mc_rldram_test_ctrl; 781#define MC_RLDRAM_TEST_MODE BIT(47) 782#define MC_RLDRAM_TEST_WRITE BIT(7) 783#define MC_RLDRAM_TEST_GO BIT(15) 784#define MC_RLDRAM_TEST_DONE BIT(23) 785#define MC_RLDRAM_TEST_PASS BIT(31) 786 787 u8 unused21[0x240 - 0x228]; 788 u64 mc_rldram_test_add; 789 u8 unused22[0x260 - 0x248]; 790 u64 mc_rldram_test_d0; 791 u8 unused23[0x280 - 0x268]; 792 u64 mc_rldram_test_d1; 793 u8 unused24[0x300 - 0x288]; 794 u64 mc_rldram_test_d2; 795 796 u8 unused24_1[0x360 - 0x308]; 797 u64 mc_rldram_ctrl; 798#define MC_RLDRAM_ENABLE_ODT BIT(7) 799 800 u8 unused24_2[0x640 - 0x368]; 801 u64 mc_rldram_ref_per_herc; 802#define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16) 803 804 u8 unused24_3[0x660 - 0x648]; 805 u64 mc_rldram_mrs_herc; 806 807 u8 unused25[0x700 - 0x668]; 808 u64 mc_debug_ctrl; 809 810 u8 unused26[0x3000 - 0x2f08]; 811 812/* XGXG */ 813 /* XGXS control registers */ 814 815 u64 xgxs_int_status; 816#define XGXS_INT_STATUS_TXGXS BIT(0) 817#define XGXS_INT_STATUS_RXGXS BIT(1) 818 u64 xgxs_int_mask; 819#define XGXS_INT_MASK_TXGXS BIT(0) 820#define XGXS_INT_MASK_RXGXS BIT(1) 821 822 u64 xgxs_txgxs_err_reg; 823#define TXGXS_ECC_DB_ERR BIT(15) 824 u64 xgxs_txgxs_err_mask; 825 u64 xgxs_txgxs_err_alarm; 826 827 u64 xgxs_rxgxs_err_reg; 828 u64 xgxs_rxgxs_err_mask; 829 u64 xgxs_rxgxs_err_alarm; 830 831 u8 unused27[0x100 - 0x40]; 832 833 u64 xgxs_cfg; 834 u64 xgxs_status; 835 836 u64 xgxs_cfg_key; 837 u64 xgxs_efifo_cfg; /* CHANGED */ 838 u64 rxgxs_ber_0; /* CHANGED */ 839 u64 rxgxs_ber_1; /* CHANGED */ 840 841 u64 spi_control; 842#define SPI_CONTROL_KEY(key) vBIT(key,0,4) 843#define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3) 844#define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8) 845#define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24) 846#define SPI_CONTROL_SEL1 BIT(4) 847#define SPI_CONTROL_REQ BIT(7) 848#define SPI_CONTROL_NACK BIT(5) 849#define SPI_CONTROL_DONE BIT(6) 850 u64 spi_data; 851#define SPI_DATA_WRITE(data,len) vBIT(data,0,len) 852}; 853 854#define XENA_REG_SPACE sizeof(struct XENA_dev_config) 855#define XENA_EEPROM_SPACE (0x01 << 11) 856 857#endif /* _REGS_H */ 858