1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card. 7 * 8 * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle 9 * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc. 10 * 11 * References: 12 * o IOC3 ASIC specification 4.51, 1996-04-18 13 * o IEEE 802.3 specification, 2000 edition 14 * o DP38840A Specification, National Semiconductor, March 1997 15 * 16 * To do: 17 * 18 * o Handle allocation failures in ioc3_alloc_skb() more gracefully. 19 * o Handle allocation failures in ioc3_init_rings(). 20 * o Use prefetching for large packets. What is a good lower limit for 21 * prefetching? 22 * o We're probably allocating a bit too much memory. 23 * o Use hardware checksums. 24 * o Convert to using a IOC3 meta driver. 25 * o Which PHYs might possibly be attached to the IOC3 in real live, 26 * which workarounds are required for them? Do we ever have Lucent's? 27 * o For the 2.5 branch kill the mii-tool ioctls. 28 */ 29 30#define IOC3_NAME "ioc3-eth" 31#define IOC3_VERSION "2.6.3-4" 32 33#include <linux/init.h> 34#include <linux/delay.h> 35#include <linux/kernel.h> 36#include <linux/mm.h> 37#include <linux/errno.h> 38#include <linux/module.h> 39#include <linux/pci.h> 40#include <linux/crc32.h> 41#include <linux/mii.h> 42#include <linux/in.h> 43#include <linux/ip.h> 44#include <linux/tcp.h> 45#include <linux/udp.h> 46#include <linux/dma-mapping.h> 47 48#ifdef CONFIG_SERIAL_8250 49#include <linux/serial_core.h> 50#include <linux/serial_8250.h> 51#endif 52 53#include <linux/netdevice.h> 54#include <linux/etherdevice.h> 55#include <linux/ethtool.h> 56#include <linux/skbuff.h> 57#include <net/ip.h> 58 59#include <asm/byteorder.h> 60#include <asm/io.h> 61#include <asm/pgtable.h> 62#include <asm/uaccess.h> 63#include <asm/sn/types.h> 64#include <asm/sn/ioc3.h> 65#include <asm/pci/bridge.h> 66 67/* 68 * 64 RX buffers. This is tunable in the range of 16 <= x < 512. The 69 * value must be a power of two. 70 */ 71#define RX_BUFFS 64 72 73#define ETCSR_FD ((17<<ETCSR_IPGR2_SHIFT) | (11<<ETCSR_IPGR1_SHIFT) | 21) 74#define ETCSR_HD ((21<<ETCSR_IPGR2_SHIFT) | (21<<ETCSR_IPGR1_SHIFT) | 21) 75 76/* Private per NIC data of the driver. */ 77struct ioc3_private { 78 struct ioc3 *regs; 79 unsigned long *rxr; /* pointer to receiver ring */ 80 struct ioc3_etxd *txr; 81 struct sk_buff *rx_skbs[512]; 82 struct sk_buff *tx_skbs[128]; 83 struct net_device_stats stats; 84 int rx_ci; /* RX consumer index */ 85 int rx_pi; /* RX producer index */ 86 int tx_ci; /* TX consumer index */ 87 int tx_pi; /* TX producer index */ 88 int txqlen; 89 u32 emcr, ehar_h, ehar_l; 90 spinlock_t ioc3_lock; 91 struct mii_if_info mii; 92 unsigned long flags; 93#define IOC3_FLAG_RX_CHECKSUMS 1 94 95 struct pci_dev *pdev; 96 97 /* Members used by autonegotiation */ 98 struct timer_list ioc3_timer; 99}; 100 101static inline struct net_device *priv_netdev(struct ioc3_private *dev) 102{ 103 return (void *)dev - ((sizeof(struct net_device) + 31) & ~31); 104} 105 106static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 107static void ioc3_set_multicast_list(struct net_device *dev); 108static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev); 109static void ioc3_timeout(struct net_device *dev); 110static inline unsigned int ioc3_hash(const unsigned char *addr); 111static inline void ioc3_stop(struct ioc3_private *ip); 112static void ioc3_init(struct net_device *dev); 113 114static const char ioc3_str[] = "IOC3 Ethernet"; 115static const struct ethtool_ops ioc3_ethtool_ops; 116 117/* We use this to acquire receive skb's that we can DMA directly into. */ 118 119#define IOC3_CACHELINE 128UL 120 121static inline unsigned long aligned_rx_skb_addr(unsigned long addr) 122{ 123 return (~addr + 1) & (IOC3_CACHELINE - 1UL); 124} 125 126static inline struct sk_buff * ioc3_alloc_skb(unsigned long length, 127 unsigned int gfp_mask) 128{ 129 struct sk_buff *skb; 130 131 skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask); 132 if (likely(skb)) { 133 int offset = aligned_rx_skb_addr((unsigned long) skb->data); 134 if (offset) 135 skb_reserve(skb, offset); 136 } 137 138 return skb; 139} 140 141static inline unsigned long ioc3_map(void *ptr, unsigned long vdev) 142{ 143#ifdef CONFIG_SGI_IP27 144 vdev <<= 57; /* Shift to PCI64_ATTR_VIRTUAL */ 145 146 return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF | 147 ((unsigned long)ptr & TO_PHYS_MASK); 148#else 149 return virt_to_bus(ptr); 150#endif 151} 152 153/* BEWARE: The IOC3 documentation documents the size of rx buffers as 154 1644 while it's actually 1664. This one was nasty to track down ... */ 155#define RX_OFFSET 10 156#define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE) 157 158/* DMA barrier to separate cached and uncached accesses. */ 159#define BARRIER() \ 160 __asm__("sync" ::: "memory") 161 162 163#define IOC3_SIZE 0x100000 164 165/* 166 * IOC3 is a big endian device 167 * 168 * Unorthodox but makes the users of these macros more readable - the pointer 169 * to the IOC3's memory mapped registers is expected as struct ioc3 * ioc3 170 * in the environment. 171 */ 172#define ioc3_r_mcr() be32_to_cpu(ioc3->mcr) 173#define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0) 174#define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0) 175#define ioc3_r_emcr() be32_to_cpu(ioc3->emcr) 176#define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0) 177#define ioc3_r_eisr() be32_to_cpu(ioc3->eisr) 178#define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0) 179#define ioc3_r_eier() be32_to_cpu(ioc3->eier) 180#define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0) 181#define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr) 182#define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0) 183#define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h) 184#define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0) 185#define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l) 186#define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0) 187#define ioc3_r_erbar() be32_to_cpu(ioc3->erbar) 188#define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0) 189#define ioc3_r_ercir() be32_to_cpu(ioc3->ercir) 190#define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0) 191#define ioc3_r_erpir() be32_to_cpu(ioc3->erpir) 192#define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0) 193#define ioc3_r_ertr() be32_to_cpu(ioc3->ertr) 194#define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0) 195#define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr) 196#define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0) 197#define ioc3_r_ersr() be32_to_cpu(ioc3->ersr) 198#define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0) 199#define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc) 200#define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0) 201#define ioc3_r_ebir() be32_to_cpu(ioc3->ebir) 202#define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0) 203#define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h) 204#define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0) 205#define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l) 206#define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0) 207#define ioc3_r_etcir() be32_to_cpu(ioc3->etcir) 208#define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0) 209#define ioc3_r_etpir() be32_to_cpu(ioc3->etpir) 210#define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0) 211#define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h) 212#define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0) 213#define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l) 214#define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0) 215#define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h) 216#define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0) 217#define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l) 218#define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0) 219#define ioc3_r_micr() be32_to_cpu(ioc3->micr) 220#define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0) 221#define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r) 222#define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0) 223#define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w) 224#define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0) 225 226static inline u32 mcr_pack(u32 pulse, u32 sample) 227{ 228 return (pulse << 10) | (sample << 2); 229} 230 231static int nic_wait(struct ioc3 *ioc3) 232{ 233 u32 mcr; 234 235 do { 236 mcr = ioc3_r_mcr(); 237 } while (!(mcr & 2)); 238 239 return mcr & 1; 240} 241 242static int nic_reset(struct ioc3 *ioc3) 243{ 244 int presence; 245 246 ioc3_w_mcr(mcr_pack(500, 65)); 247 presence = nic_wait(ioc3); 248 249 ioc3_w_mcr(mcr_pack(0, 500)); 250 nic_wait(ioc3); 251 252 return presence; 253} 254 255static inline int nic_read_bit(struct ioc3 *ioc3) 256{ 257 int result; 258 259 ioc3_w_mcr(mcr_pack(6, 13)); 260 result = nic_wait(ioc3); 261 ioc3_w_mcr(mcr_pack(0, 100)); 262 nic_wait(ioc3); 263 264 return result; 265} 266 267static inline void nic_write_bit(struct ioc3 *ioc3, int bit) 268{ 269 if (bit) 270 ioc3_w_mcr(mcr_pack(6, 110)); 271 else 272 ioc3_w_mcr(mcr_pack(80, 30)); 273 274 nic_wait(ioc3); 275} 276 277/* 278 * Read a byte from an iButton device 279 */ 280static u32 nic_read_byte(struct ioc3 *ioc3) 281{ 282 u32 result = 0; 283 int i; 284 285 for (i = 0; i < 8; i++) 286 result = (result >> 1) | (nic_read_bit(ioc3) << 7); 287 288 return result; 289} 290 291/* 292 * Write a byte to an iButton device 293 */ 294static void nic_write_byte(struct ioc3 *ioc3, int byte) 295{ 296 int i, bit; 297 298 for (i = 8; i; i--) { 299 bit = byte & 1; 300 byte >>= 1; 301 302 nic_write_bit(ioc3, bit); 303 } 304} 305 306static u64 nic_find(struct ioc3 *ioc3, int *last) 307{ 308 int a, b, index, disc; 309 u64 address = 0; 310 311 nic_reset(ioc3); 312 /* Search ROM. */ 313 nic_write_byte(ioc3, 0xf0); 314 315 /* Algorithm from ``Book of iButton Standards''. */ 316 for (index = 0, disc = 0; index < 64; index++) { 317 a = nic_read_bit(ioc3); 318 b = nic_read_bit(ioc3); 319 320 if (a && b) { 321 printk("NIC search failed (not fatal).\n"); 322 *last = 0; 323 return 0; 324 } 325 326 if (!a && !b) { 327 if (index == *last) { 328 address |= 1UL << index; 329 } else if (index > *last) { 330 address &= ~(1UL << index); 331 disc = index; 332 } else if ((address & (1UL << index)) == 0) 333 disc = index; 334 nic_write_bit(ioc3, address & (1UL << index)); 335 continue; 336 } else { 337 if (a) 338 address |= 1UL << index; 339 else 340 address &= ~(1UL << index); 341 nic_write_bit(ioc3, a); 342 continue; 343 } 344 } 345 346 *last = disc; 347 348 return address; 349} 350 351static int nic_init(struct ioc3 *ioc3) 352{ 353 const char *type; 354 u8 crc; 355 u8 serial[6]; 356 int save = 0, i; 357 358 type = "unknown"; 359 360 while (1) { 361 u64 reg; 362 reg = nic_find(ioc3, &save); 363 364 switch (reg & 0xff) { 365 case 0x91: 366 type = "DS1981U"; 367 break; 368 default: 369 if (save == 0) { 370 /* Let the caller try again. */ 371 return -1; 372 } 373 continue; 374 } 375 376 nic_reset(ioc3); 377 378 /* Match ROM. */ 379 nic_write_byte(ioc3, 0x55); 380 for (i = 0; i < 8; i++) 381 nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff); 382 383 reg >>= 8; /* Shift out type. */ 384 for (i = 0; i < 6; i++) { 385 serial[i] = reg & 0xff; 386 reg >>= 8; 387 } 388 crc = reg & 0xff; 389 break; 390 } 391 392 printk("Found %s NIC", type); 393 if (type != "unknown") { 394 printk (" registration number %02x:%02x:%02x:%02x:%02x:%02x," 395 " CRC %02x", serial[0], serial[1], serial[2], 396 serial[3], serial[4], serial[5], crc); 397 } 398 printk(".\n"); 399 400 return 0; 401} 402 403/* 404 * Read the NIC (Number-In-a-Can) device used to store the MAC address on 405 * SN0 / SN00 nodeboards and PCI cards. 406 */ 407static void ioc3_get_eaddr_nic(struct ioc3_private *ip) 408{ 409 struct ioc3 *ioc3 = ip->regs; 410 u8 nic[14]; 411 int tries = 2; /* There may be some problem with the battery? */ 412 int i; 413 414 ioc3_w_gpcr_s(1 << 21); 415 416 while (tries--) { 417 if (!nic_init(ioc3)) 418 break; 419 udelay(500); 420 } 421 422 if (tries < 0) { 423 printk("Failed to read MAC address\n"); 424 return; 425 } 426 427 /* Read Memory. */ 428 nic_write_byte(ioc3, 0xf0); 429 nic_write_byte(ioc3, 0x00); 430 nic_write_byte(ioc3, 0x00); 431 432 for (i = 13; i >= 0; i--) 433 nic[i] = nic_read_byte(ioc3); 434 435 for (i = 2; i < 8; i++) 436 priv_netdev(ip)->dev_addr[i - 2] = nic[i]; 437} 438 439/* 440 * Ok, this is hosed by design. It's necessary to know what machine the 441 * NIC is in in order to know how to read the NIC address. We also have 442 * to know if it's a PCI card or a NIC in on the node board ... 443 */ 444static void ioc3_get_eaddr(struct ioc3_private *ip) 445{ 446 int i; 447 448 449 ioc3_get_eaddr_nic(ip); 450 451 printk("Ethernet address is "); 452 for (i = 0; i < 6; i++) { 453 printk("%02x", priv_netdev(ip)->dev_addr[i]); 454 if (i < 5) 455 printk(":"); 456 } 457 printk(".\n"); 458} 459 460static void __ioc3_set_mac_address(struct net_device *dev) 461{ 462 struct ioc3_private *ip = netdev_priv(dev); 463 struct ioc3 *ioc3 = ip->regs; 464 465 ioc3_w_emar_h((dev->dev_addr[5] << 8) | dev->dev_addr[4]); 466 ioc3_w_emar_l((dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | 467 (dev->dev_addr[1] << 8) | dev->dev_addr[0]); 468} 469 470static int ioc3_set_mac_address(struct net_device *dev, void *addr) 471{ 472 struct ioc3_private *ip = netdev_priv(dev); 473 struct sockaddr *sa = addr; 474 475 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); 476 477 spin_lock_irq(&ip->ioc3_lock); 478 __ioc3_set_mac_address(dev); 479 spin_unlock_irq(&ip->ioc3_lock); 480 481 return 0; 482} 483 484/* 485 * Caller must hold the ioc3_lock ever for MII readers. This is also 486 * used to protect the transmitter side but it's low contention. 487 */ 488static int ioc3_mdio_read(struct net_device *dev, int phy, int reg) 489{ 490 struct ioc3_private *ip = netdev_priv(dev); 491 struct ioc3 *ioc3 = ip->regs; 492 493 while (ioc3_r_micr() & MICR_BUSY); 494 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG); 495 while (ioc3_r_micr() & MICR_BUSY); 496 497 return ioc3_r_midr_r() & MIDR_DATA_MASK; 498} 499 500static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data) 501{ 502 struct ioc3_private *ip = netdev_priv(dev); 503 struct ioc3 *ioc3 = ip->regs; 504 505 while (ioc3_r_micr() & MICR_BUSY); 506 ioc3_w_midr_w(data); 507 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg); 508 while (ioc3_r_micr() & MICR_BUSY); 509} 510 511static int ioc3_mii_init(struct ioc3_private *ip); 512 513static struct net_device_stats *ioc3_get_stats(struct net_device *dev) 514{ 515 struct ioc3_private *ip = netdev_priv(dev); 516 struct ioc3 *ioc3 = ip->regs; 517 518 ip->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK); 519 return &ip->stats; 520} 521 522static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len) 523{ 524 struct ethhdr *eh = eth_hdr(skb); 525 uint32_t csum, ehsum; 526 unsigned int proto; 527 struct iphdr *ih; 528 uint16_t *ew; 529 unsigned char *cp; 530 531 /* 532 * Did hardware handle the checksum at all? The cases we can handle 533 * are: 534 * 535 * - TCP and UDP checksums of IPv4 only. 536 * - IPv6 would be doable but we keep that for later ... 537 * - Only unfragmented packets. Did somebody already tell you 538 * fragmentation is evil? 539 * - don't care about packet size. Worst case when processing a 540 * malformed packet we'll try to access the packet at ip header + 541 * 64 bytes which is still inside the skb. Even in the unlikely 542 * case where the checksum is right the higher layers will still 543 * drop the packet as appropriate. 544 */ 545 if (eh->h_proto != ntohs(ETH_P_IP)) 546 return; 547 548 ih = (struct iphdr *) ((char *)eh + ETH_HLEN); 549 if (ih->frag_off & htons(IP_MF | IP_OFFSET)) 550 return; 551 552 proto = ih->protocol; 553 if (proto != IPPROTO_TCP && proto != IPPROTO_UDP) 554 return; 555 556 /* Same as tx - compute csum of pseudo header */ 557 csum = hwsum + 558 (ih->tot_len - (ih->ihl << 2)) + 559 htons((uint16_t)ih->protocol) + 560 (ih->saddr >> 16) + (ih->saddr & 0xffff) + 561 (ih->daddr >> 16) + (ih->daddr & 0xffff); 562 563 /* Sum up ethernet dest addr, src addr and protocol */ 564 ew = (uint16_t *) eh; 565 ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6]; 566 567 ehsum = (ehsum & 0xffff) + (ehsum >> 16); 568 ehsum = (ehsum & 0xffff) + (ehsum >> 16); 569 570 csum += 0xffff ^ ehsum; 571 572 /* In the next step we also subtract the 1's complement 573 checksum of the trailing ethernet CRC. */ 574 cp = (char *)eh + len; /* points at trailing CRC */ 575 if (len & 1) { 576 csum += 0xffff ^ (uint16_t) ((cp[1] << 8) | cp[0]); 577 csum += 0xffff ^ (uint16_t) ((cp[3] << 8) | cp[2]); 578 } else { 579 csum += 0xffff ^ (uint16_t) ((cp[0] << 8) | cp[1]); 580 csum += 0xffff ^ (uint16_t) ((cp[2] << 8) | cp[3]); 581 } 582 583 csum = (csum & 0xffff) + (csum >> 16); 584 csum = (csum & 0xffff) + (csum >> 16); 585 586 if (csum == 0xffff) 587 skb->ip_summed = CHECKSUM_UNNECESSARY; 588} 589 590static inline void ioc3_rx(struct ioc3_private *ip) 591{ 592 struct sk_buff *skb, *new_skb; 593 struct ioc3 *ioc3 = ip->regs; 594 int rx_entry, n_entry, len; 595 struct ioc3_erxbuf *rxb; 596 unsigned long *rxr; 597 u32 w0, err; 598 599 rxr = (unsigned long *) ip->rxr; /* Ring base */ 600 rx_entry = ip->rx_ci; /* RX consume index */ 601 n_entry = ip->rx_pi; 602 603 skb = ip->rx_skbs[rx_entry]; 604 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET); 605 w0 = be32_to_cpu(rxb->w0); 606 607 while (w0 & ERXBUF_V) { 608 err = be32_to_cpu(rxb->err); /* It's valid ... */ 609 if (err & ERXBUF_GOODPKT) { 610 len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4; 611 skb_trim(skb, len); 612 skb->protocol = eth_type_trans(skb, priv_netdev(ip)); 613 614 new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC); 615 if (!new_skb) { 616 /* Ouch, drop packet and just recycle packet 617 to keep the ring filled. */ 618 ip->stats.rx_dropped++; 619 new_skb = skb; 620 goto next; 621 } 622 623 if (likely(ip->flags & IOC3_FLAG_RX_CHECKSUMS)) 624 ioc3_tcpudp_checksum(skb, 625 w0 & ERXBUF_IPCKSUM_MASK, len); 626 627 netif_rx(skb); 628 629 ip->rx_skbs[rx_entry] = NULL; /* Poison */ 630 631 /* Because we reserve afterwards. */ 632 skb_put(new_skb, (1664 + RX_OFFSET)); 633 rxb = (struct ioc3_erxbuf *) new_skb->data; 634 skb_reserve(new_skb, RX_OFFSET); 635 636 priv_netdev(ip)->last_rx = jiffies; 637 ip->stats.rx_packets++; /* Statistics */ 638 ip->stats.rx_bytes += len; 639 } else { 640 /* The frame is invalid and the skb never 641 reached the network layer so we can just 642 recycle it. */ 643 new_skb = skb; 644 ip->stats.rx_errors++; 645 } 646 if (err & ERXBUF_CRCERR) /* Statistics */ 647 ip->stats.rx_crc_errors++; 648 if (err & ERXBUF_FRAMERR) 649 ip->stats.rx_frame_errors++; 650next: 651 ip->rx_skbs[n_entry] = new_skb; 652 rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1)); 653 rxb->w0 = 0; /* Clear valid flag */ 654 n_entry = (n_entry + 1) & 511; /* Update erpir */ 655 656 /* Now go on to the next ring entry. */ 657 rx_entry = (rx_entry + 1) & 511; 658 skb = ip->rx_skbs[rx_entry]; 659 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET); 660 w0 = be32_to_cpu(rxb->w0); 661 } 662 ioc3_w_erpir((n_entry << 3) | ERPIR_ARM); 663 ip->rx_pi = n_entry; 664 ip->rx_ci = rx_entry; 665} 666 667static inline void ioc3_tx(struct ioc3_private *ip) 668{ 669 unsigned long packets, bytes; 670 struct ioc3 *ioc3 = ip->regs; 671 int tx_entry, o_entry; 672 struct sk_buff *skb; 673 u32 etcir; 674 675 spin_lock(&ip->ioc3_lock); 676 etcir = ioc3_r_etcir(); 677 678 tx_entry = (etcir >> 7) & 127; 679 o_entry = ip->tx_ci; 680 packets = 0; 681 bytes = 0; 682 683 while (o_entry != tx_entry) { 684 packets++; 685 skb = ip->tx_skbs[o_entry]; 686 bytes += skb->len; 687 dev_kfree_skb_irq(skb); 688 ip->tx_skbs[o_entry] = NULL; 689 690 o_entry = (o_entry + 1) & 127; /* Next */ 691 692 etcir = ioc3_r_etcir(); /* More pkts sent? */ 693 tx_entry = (etcir >> 7) & 127; 694 } 695 696 ip->stats.tx_packets += packets; 697 ip->stats.tx_bytes += bytes; 698 ip->txqlen -= packets; 699 700 if (ip->txqlen < 128) 701 netif_wake_queue(priv_netdev(ip)); 702 703 ip->tx_ci = o_entry; 704 spin_unlock(&ip->ioc3_lock); 705} 706 707/* 708 * Deal with fatal IOC3 errors. This condition might be caused by a hard or 709 * software problems, so we should try to recover 710 * more gracefully if this ever happens. In theory we might be flooded 711 * with such error interrupts if something really goes wrong, so we might 712 * also consider to take the interface down. 713 */ 714static void ioc3_error(struct ioc3_private *ip, u32 eisr) 715{ 716 struct net_device *dev = priv_netdev(ip); 717 unsigned char *iface = dev->name; 718 719 spin_lock(&ip->ioc3_lock); 720 721 if (eisr & EISR_RXOFLO) 722 printk(KERN_ERR "%s: RX overflow.\n", iface); 723 if (eisr & EISR_RXBUFOFLO) 724 printk(KERN_ERR "%s: RX buffer overflow.\n", iface); 725 if (eisr & EISR_RXMEMERR) 726 printk(KERN_ERR "%s: RX PCI error.\n", iface); 727 if (eisr & EISR_RXPARERR) 728 printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface); 729 if (eisr & EISR_TXBUFUFLO) 730 printk(KERN_ERR "%s: TX buffer underflow.\n", iface); 731 if (eisr & EISR_TXMEMERR) 732 printk(KERN_ERR "%s: TX PCI error.\n", iface); 733 734 ioc3_stop(ip); 735 ioc3_init(dev); 736 ioc3_mii_init(ip); 737 738 netif_wake_queue(dev); 739 740 spin_unlock(&ip->ioc3_lock); 741} 742 743/* The interrupt handler does all of the Rx thread work and cleans up 744 after the Tx thread. */ 745static irqreturn_t ioc3_interrupt(int irq, void *_dev) 746{ 747 struct net_device *dev = (struct net_device *)_dev; 748 struct ioc3_private *ip = netdev_priv(dev); 749 struct ioc3 *ioc3 = ip->regs; 750 const u32 enabled = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO | 751 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO | 752 EISR_TXEXPLICIT | EISR_TXMEMERR; 753 u32 eisr; 754 755 eisr = ioc3_r_eisr() & enabled; 756 757 ioc3_w_eisr(eisr); 758 (void) ioc3_r_eisr(); /* Flush */ 759 760 if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR | 761 EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR)) 762 ioc3_error(ip, eisr); 763 if (eisr & EISR_RXTIMERINT) 764 ioc3_rx(ip); 765 if (eisr & EISR_TXEXPLICIT) 766 ioc3_tx(ip); 767 768 return IRQ_HANDLED; 769} 770 771static inline void ioc3_setup_duplex(struct ioc3_private *ip) 772{ 773 struct ioc3 *ioc3 = ip->regs; 774 775 if (ip->mii.full_duplex) { 776 ioc3_w_etcsr(ETCSR_FD); 777 ip->emcr |= EMCR_DUPLEX; 778 } else { 779 ioc3_w_etcsr(ETCSR_HD); 780 ip->emcr &= ~EMCR_DUPLEX; 781 } 782 ioc3_w_emcr(ip->emcr); 783} 784 785static void ioc3_timer(unsigned long data) 786{ 787 struct ioc3_private *ip = (struct ioc3_private *) data; 788 789 /* Print the link status if it has changed */ 790 mii_check_media(&ip->mii, 1, 0); 791 ioc3_setup_duplex(ip); 792 793 ip->ioc3_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2s */ 794 add_timer(&ip->ioc3_timer); 795} 796 797/* 798 * Try to find a PHY. There is no apparent relation between the MII addresses 799 * in the SGI documentation and what we find in reality, so we simply probe 800 * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my 801 * onboard IOC3s has the special oddity that probing doesn't seem to find it 802 * yet the interface seems to work fine, so if probing fails we for now will 803 * simply default to PHY 31 instead of bailing out. 804 */ 805static int ioc3_mii_init(struct ioc3_private *ip) 806{ 807 struct net_device *dev = priv_netdev(ip); 808 int i, found = 0, res = 0; 809 int ioc3_phy_workaround = 1; 810 u16 word; 811 812 for (i = 0; i < 32; i++) { 813 word = ioc3_mdio_read(dev, i, MII_PHYSID1); 814 815 if (word != 0xffff && word != 0x0000) { 816 found = 1; 817 break; /* Found a PHY */ 818 } 819 } 820 821 if (!found) { 822 if (ioc3_phy_workaround) 823 i = 31; 824 else { 825 ip->mii.phy_id = -1; 826 res = -ENODEV; 827 goto out; 828 } 829 } 830 831 ip->mii.phy_id = i; 832 833out: 834 return res; 835} 836 837static void ioc3_mii_start(struct ioc3_private *ip) 838{ 839 ip->ioc3_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */ 840 ip->ioc3_timer.data = (unsigned long) ip; 841 ip->ioc3_timer.function = &ioc3_timer; 842 add_timer(&ip->ioc3_timer); 843} 844 845static inline void ioc3_clean_rx_ring(struct ioc3_private *ip) 846{ 847 struct sk_buff *skb; 848 int i; 849 850 for (i = ip->rx_ci; i & 15; i++) { 851 ip->rx_skbs[ip->rx_pi] = ip->rx_skbs[ip->rx_ci]; 852 ip->rxr[ip->rx_pi++] = ip->rxr[ip->rx_ci++]; 853 } 854 ip->rx_pi &= 511; 855 ip->rx_ci &= 511; 856 857 for (i = ip->rx_ci; i != ip->rx_pi; i = (i+1) & 511) { 858 struct ioc3_erxbuf *rxb; 859 skb = ip->rx_skbs[i]; 860 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET); 861 rxb->w0 = 0; 862 } 863} 864 865static inline void ioc3_clean_tx_ring(struct ioc3_private *ip) 866{ 867 struct sk_buff *skb; 868 int i; 869 870 for (i=0; i < 128; i++) { 871 skb = ip->tx_skbs[i]; 872 if (skb) { 873 ip->tx_skbs[i] = NULL; 874 dev_kfree_skb_any(skb); 875 } 876 ip->txr[i].cmd = 0; 877 } 878 ip->tx_pi = 0; 879 ip->tx_ci = 0; 880} 881 882static void ioc3_free_rings(struct ioc3_private *ip) 883{ 884 struct sk_buff *skb; 885 int rx_entry, n_entry; 886 887 if (ip->txr) { 888 ioc3_clean_tx_ring(ip); 889 free_pages((unsigned long)ip->txr, 2); 890 ip->txr = NULL; 891 } 892 893 if (ip->rxr) { 894 n_entry = ip->rx_ci; 895 rx_entry = ip->rx_pi; 896 897 while (n_entry != rx_entry) { 898 skb = ip->rx_skbs[n_entry]; 899 if (skb) 900 dev_kfree_skb_any(skb); 901 902 n_entry = (n_entry + 1) & 511; 903 } 904 free_page((unsigned long)ip->rxr); 905 ip->rxr = NULL; 906 } 907} 908 909static void ioc3_alloc_rings(struct net_device *dev) 910{ 911 struct ioc3_private *ip = netdev_priv(dev); 912 struct ioc3_erxbuf *rxb; 913 unsigned long *rxr; 914 int i; 915 916 if (ip->rxr == NULL) { 917 /* Allocate and initialize rx ring. 4kb = 512 entries */ 918 ip->rxr = (unsigned long *) get_zeroed_page(GFP_ATOMIC); 919 rxr = (unsigned long *) ip->rxr; 920 if (!rxr) 921 printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n"); 922 923 /* Now the rx buffers. The RX ring may be larger but 924 we only allocate 16 buffers for now. Need to tune 925 this for performance and memory later. */ 926 for (i = 0; i < RX_BUFFS; i++) { 927 struct sk_buff *skb; 928 929 skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC); 930 if (!skb) { 931 show_free_areas(); 932 continue; 933 } 934 935 ip->rx_skbs[i] = skb; 936 937 /* Because we reserve afterwards. */ 938 skb_put(skb, (1664 + RX_OFFSET)); 939 rxb = (struct ioc3_erxbuf *) skb->data; 940 rxr[i] = cpu_to_be64(ioc3_map(rxb, 1)); 941 skb_reserve(skb, RX_OFFSET); 942 } 943 ip->rx_ci = 0; 944 ip->rx_pi = RX_BUFFS; 945 } 946 947 if (ip->txr == NULL) { 948 /* Allocate and initialize tx rings. 16kb = 128 bufs. */ 949 ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2); 950 if (!ip->txr) 951 printk("ioc3_alloc_rings(): __get_free_pages() failed!\n"); 952 ip->tx_pi = 0; 953 ip->tx_ci = 0; 954 } 955} 956 957static void ioc3_init_rings(struct net_device *dev) 958{ 959 struct ioc3_private *ip = netdev_priv(dev); 960 struct ioc3 *ioc3 = ip->regs; 961 unsigned long ring; 962 963 ioc3_free_rings(ip); 964 ioc3_alloc_rings(dev); 965 966 ioc3_clean_rx_ring(ip); 967 ioc3_clean_tx_ring(ip); 968 969 /* Now the rx ring base, consume & produce registers. */ 970 ring = ioc3_map(ip->rxr, 0); 971 ioc3_w_erbr_h(ring >> 32); 972 ioc3_w_erbr_l(ring & 0xffffffff); 973 ioc3_w_ercir(ip->rx_ci << 3); 974 ioc3_w_erpir((ip->rx_pi << 3) | ERPIR_ARM); 975 976 ring = ioc3_map(ip->txr, 0); 977 978 ip->txqlen = 0; /* nothing queued */ 979 980 /* Now the tx ring base, consume & produce registers. */ 981 ioc3_w_etbr_h(ring >> 32); 982 ioc3_w_etbr_l(ring & 0xffffffff); 983 ioc3_w_etpir(ip->tx_pi << 7); 984 ioc3_w_etcir(ip->tx_ci << 7); 985 (void) ioc3_r_etcir(); /* Flush */ 986} 987 988static inline void ioc3_ssram_disc(struct ioc3_private *ip) 989{ 990 struct ioc3 *ioc3 = ip->regs; 991 volatile u32 *ssram0 = &ioc3->ssram[0x0000]; 992 volatile u32 *ssram1 = &ioc3->ssram[0x4000]; 993 unsigned int pattern = 0x5555; 994 995 /* Assume the larger size SSRAM and enable parity checking */ 996 ioc3_w_emcr(ioc3_r_emcr() | (EMCR_BUFSIZ | EMCR_RAMPAR)); 997 998 *ssram0 = pattern; 999 *ssram1 = ~pattern & IOC3_SSRAM_DM; 1000 1001 if ((*ssram0 & IOC3_SSRAM_DM) != pattern || 1002 (*ssram1 & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) { 1003 /* set ssram size to 64 KB */ 1004 ip->emcr = EMCR_RAMPAR; 1005 ioc3_w_emcr(ioc3_r_emcr() & ~EMCR_BUFSIZ); 1006 } else 1007 ip->emcr = EMCR_BUFSIZ | EMCR_RAMPAR; 1008} 1009 1010static void ioc3_init(struct net_device *dev) 1011{ 1012 struct ioc3_private *ip = netdev_priv(dev); 1013 struct ioc3 *ioc3 = ip->regs; 1014 1015 del_timer_sync(&ip->ioc3_timer); /* Kill if running */ 1016 1017 ioc3_w_emcr(EMCR_RST); /* Reset */ 1018 (void) ioc3_r_emcr(); /* Flush WB */ 1019 udelay(4); /* Give it time ... */ 1020 ioc3_w_emcr(0); 1021 (void) ioc3_r_emcr(); 1022 1023 /* Misc registers */ 1024#ifdef CONFIG_SGI_IP27 1025 ioc3_w_erbar(PCI64_ATTR_BAR >> 32); /* Barrier on last store */ 1026#else 1027 ioc3_w_erbar(0); /* Let PCI API get it right */ 1028#endif 1029 (void) ioc3_r_etcdc(); /* Clear on read */ 1030 ioc3_w_ercsr(15); /* RX low watermark */ 1031 ioc3_w_ertr(0); /* Interrupt immediately */ 1032 __ioc3_set_mac_address(dev); 1033 ioc3_w_ehar_h(ip->ehar_h); 1034 ioc3_w_ehar_l(ip->ehar_l); 1035 ioc3_w_ersr(42); 1036 1037 ioc3_init_rings(dev); 1038 1039 ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN | 1040 EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN; 1041 ioc3_w_emcr(ip->emcr); 1042 ioc3_w_eier(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO | 1043 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO | 1044 EISR_TXEXPLICIT | EISR_TXMEMERR); 1045 (void) ioc3_r_eier(); 1046} 1047 1048static inline void ioc3_stop(struct ioc3_private *ip) 1049{ 1050 struct ioc3 *ioc3 = ip->regs; 1051 1052 ioc3_w_emcr(0); /* Shutup */ 1053 ioc3_w_eier(0); /* Disable interrupts */ 1054 (void) ioc3_r_eier(); /* Flush */ 1055} 1056 1057static int ioc3_open(struct net_device *dev) 1058{ 1059 struct ioc3_private *ip = netdev_priv(dev); 1060 1061 if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) { 1062 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq); 1063 1064 return -EAGAIN; 1065 } 1066 1067 ip->ehar_h = 0; 1068 ip->ehar_l = 0; 1069 ioc3_init(dev); 1070 ioc3_mii_start(ip); 1071 1072 netif_start_queue(dev); 1073 return 0; 1074} 1075 1076static int ioc3_close(struct net_device *dev) 1077{ 1078 struct ioc3_private *ip = netdev_priv(dev); 1079 1080 del_timer_sync(&ip->ioc3_timer); 1081 1082 netif_stop_queue(dev); 1083 1084 ioc3_stop(ip); 1085 free_irq(dev->irq, dev); 1086 1087 ioc3_free_rings(ip); 1088 return 0; 1089} 1090 1091/* 1092 * MENET cards have four IOC3 chips, which are attached to two sets of 1093 * PCI slot resources each: the primary connections are on slots 1094 * 0..3 and the secondaries are on 4..7 1095 * 1096 * All four ethernets are brought out to connectors; six serial ports 1097 * (a pair from each of the first three IOC3s) are brought out to 1098 * MiniDINs; all other subdevices are left swinging in the wind, leave 1099 * them disabled. 1100 */ 1101static inline int ioc3_is_menet(struct pci_dev *pdev) 1102{ 1103 struct pci_dev *dev; 1104 1105 return pdev->bus->parent == NULL 1106 && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(0, 0))) 1107 && dev->vendor == PCI_VENDOR_ID_SGI 1108 && dev->device == PCI_DEVICE_ID_SGI_IOC3 1109 && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(1, 0))) 1110 && dev->vendor == PCI_VENDOR_ID_SGI 1111 && dev->device == PCI_DEVICE_ID_SGI_IOC3 1112 && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(2, 0))) 1113 && dev->vendor == PCI_VENDOR_ID_SGI 1114 && dev->device == PCI_DEVICE_ID_SGI_IOC3; 1115} 1116 1117#ifdef CONFIG_SERIAL_8250 1118/* 1119 * Note about serial ports and consoles: 1120 * For console output, everyone uses the IOC3 UARTA (offset 0x178) 1121 * connected to the master node (look in ip27_setup_console() and 1122 * ip27prom_console_write()). 1123 * 1124 * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port 1125 * addresses on a partitioned machine. Since we currently use the ioc3 1126 * serial ports, we use dynamic serial port discovery that the serial.c 1127 * driver uses for pci/pnp ports (there is an entry for the SGI ioc3 1128 * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater 1129 * than UARTB's, although UARTA on o200s has traditionally been known as 1130 * port 0. So, we just use one serial port from each ioc3 (since the 1131 * serial driver adds addresses to get to higher ports). 1132 * 1133 * The first one to do a register_console becomes the preferred console 1134 * (if there is no kernel command line console= directive). /dev/console 1135 * (ie 5, 1) is then "aliased" into the device number returned by the 1136 * "device" routine referred to in this console structure 1137 * (ip27prom_console_dev). 1138 * 1139 * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working 1140 * around ioc3 oddities in this respect. 1141 * 1142 * The IOC3 serials use a 22MHz clock rate with an additional divider by 3. 1143 */ 1144 1145static void __devinit ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3) 1146{ 1147 struct uart_port port; 1148 1149 /* 1150 * We need to recognice and treat the fourth MENET serial as it 1151 * does not have an SuperIO chip attached to it, therefore attempting 1152 * to access it will result in bus errors. We call something an 1153 * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3 1154 * in it. This is paranoid but we want to avoid blowing up on a 1155 * showhorn PCI box that happens to have 4 IOC3 cards in it so it's 1156 * not paranoid enough ... 1157 */ 1158 if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3) 1159 return; 1160 1161 /* 1162 * Register to interrupt zero because we share the interrupt with 1163 * the serial driver which we don't properly support yet. 1164 * 1165 * Can't use UPF_IOREMAP as the whole of IOC3 resources have already 1166 * been registered. 1167 */ 1168 memset(&port, 0, sizeof(port)); 1169 port.irq = 0; 1170 port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; 1171 port.iotype = UPIO_MEM; 1172 port.regshift = 0; 1173 port.uartclk = 22000000 / 3; 1174 1175 port.membase = (unsigned char *) &ioc3->sregs.uarta; 1176 serial8250_register_port(&port); 1177 1178 port.membase = (unsigned char *) &ioc3->sregs.uartb; 1179 serial8250_register_port(&port); 1180} 1181#endif 1182 1183static int ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1184{ 1185 unsigned int sw_physid1, sw_physid2; 1186 struct net_device *dev = NULL; 1187 struct ioc3_private *ip; 1188 struct ioc3 *ioc3; 1189 unsigned long ioc3_base, ioc3_size; 1190 u32 vendor, model, rev; 1191 int err, pci_using_dac; 1192 1193 /* Configure DMA attributes. */ 1194 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK); 1195 if (!err) { 1196 pci_using_dac = 1; 1197 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 1198 if (err < 0) { 1199 printk(KERN_ERR "%s: Unable to obtain 64 bit DMA " 1200 "for consistent allocations\n", pci_name(pdev)); 1201 goto out; 1202 } 1203 } else { 1204 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1205 if (err) { 1206 printk(KERN_ERR "%s: No usable DMA configuration, " 1207 "aborting.\n", pci_name(pdev)); 1208 goto out; 1209 } 1210 pci_using_dac = 0; 1211 } 1212 1213 if (pci_enable_device(pdev)) 1214 return -ENODEV; 1215 1216 dev = alloc_etherdev(sizeof(struct ioc3_private)); 1217 if (!dev) { 1218 err = -ENOMEM; 1219 goto out_disable; 1220 } 1221 1222 if (pci_using_dac) 1223 dev->features |= NETIF_F_HIGHDMA; 1224 1225 err = pci_request_regions(pdev, "ioc3"); 1226 if (err) 1227 goto out_free; 1228 1229 SET_MODULE_OWNER(dev); 1230 SET_NETDEV_DEV(dev, &pdev->dev); 1231 1232 ip = netdev_priv(dev); 1233 1234 dev->irq = pdev->irq; 1235 1236 ioc3_base = pci_resource_start(pdev, 0); 1237 ioc3_size = pci_resource_len(pdev, 0); 1238 ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size); 1239 if (!ioc3) { 1240 printk(KERN_CRIT "ioc3eth(%s): ioremap failed, goodbye.\n", 1241 pci_name(pdev)); 1242 err = -ENOMEM; 1243 goto out_res; 1244 } 1245 ip->regs = ioc3; 1246 1247#ifdef CONFIG_SERIAL_8250 1248 ioc3_serial_probe(pdev, ioc3); 1249#endif 1250 1251 spin_lock_init(&ip->ioc3_lock); 1252 init_timer(&ip->ioc3_timer); 1253 1254 ioc3_stop(ip); 1255 ioc3_init(dev); 1256 1257 ip->pdev = pdev; 1258 1259 ip->mii.phy_id_mask = 0x1f; 1260 ip->mii.reg_num_mask = 0x1f; 1261 ip->mii.dev = dev; 1262 ip->mii.mdio_read = ioc3_mdio_read; 1263 ip->mii.mdio_write = ioc3_mdio_write; 1264 1265 ioc3_mii_init(ip); 1266 1267 if (ip->mii.phy_id == -1) { 1268 printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n", 1269 pci_name(pdev)); 1270 err = -ENODEV; 1271 goto out_stop; 1272 } 1273 1274 ioc3_mii_start(ip); 1275 ioc3_ssram_disc(ip); 1276 ioc3_get_eaddr(ip); 1277 1278 /* The IOC3-specific entries in the device structure. */ 1279 dev->open = ioc3_open; 1280 dev->hard_start_xmit = ioc3_start_xmit; 1281 dev->tx_timeout = ioc3_timeout; 1282 dev->watchdog_timeo = 5 * HZ; 1283 dev->stop = ioc3_close; 1284 dev->get_stats = ioc3_get_stats; 1285 dev->do_ioctl = ioc3_ioctl; 1286 dev->set_multicast_list = ioc3_set_multicast_list; 1287 dev->set_mac_address = ioc3_set_mac_address; 1288 dev->ethtool_ops = &ioc3_ethtool_ops; 1289 dev->features = NETIF_F_IP_CSUM; 1290 1291 sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1); 1292 sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2); 1293 1294 err = register_netdev(dev); 1295 if (err) 1296 goto out_stop; 1297 1298 mii_check_media(&ip->mii, 1, 1); 1299 ioc3_setup_duplex(ip); 1300 1301 vendor = (sw_physid1 << 12) | (sw_physid2 >> 4); 1302 model = (sw_physid2 >> 4) & 0x3f; 1303 rev = sw_physid2 & 0xf; 1304 printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, " 1305 "rev %d.\n", dev->name, ip->mii.phy_id, vendor, model, rev); 1306 printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name, 1307 ip->emcr & EMCR_BUFSIZ ? 128 : 64); 1308 1309 return 0; 1310 1311out_stop: 1312 ioc3_stop(ip); 1313 del_timer_sync(&ip->ioc3_timer); 1314 ioc3_free_rings(ip); 1315out_res: 1316 pci_release_regions(pdev); 1317out_free: 1318 free_netdev(dev); 1319out_disable: 1320 /* 1321 * We should call pci_disable_device(pdev); here if the IOC3 wasn't 1322 * such a weird device ... 1323 */ 1324out: 1325 return err; 1326} 1327 1328static void __devexit ioc3_remove_one (struct pci_dev *pdev) 1329{ 1330 struct net_device *dev = pci_get_drvdata(pdev); 1331 struct ioc3_private *ip = netdev_priv(dev); 1332 struct ioc3 *ioc3 = ip->regs; 1333 1334 unregister_netdev(dev); 1335 del_timer_sync(&ip->ioc3_timer); 1336 1337 iounmap(ioc3); 1338 pci_release_regions(pdev); 1339 free_netdev(dev); 1340 /* 1341 * We should call pci_disable_device(pdev); here if the IOC3 wasn't 1342 * such a weird device ... 1343 */ 1344} 1345 1346static struct pci_device_id ioc3_pci_tbl[] = { 1347 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID }, 1348 { 0 } 1349}; 1350MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl); 1351 1352static struct pci_driver ioc3_driver = { 1353 .name = "ioc3-eth", 1354 .id_table = ioc3_pci_tbl, 1355 .probe = ioc3_probe, 1356 .remove = __devexit_p(ioc3_remove_one), 1357}; 1358 1359static int __init ioc3_init_module(void) 1360{ 1361 return pci_register_driver(&ioc3_driver); 1362} 1363 1364static void __exit ioc3_cleanup_module(void) 1365{ 1366 pci_unregister_driver(&ioc3_driver); 1367} 1368 1369static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev) 1370{ 1371 unsigned long data; 1372 struct ioc3_private *ip = netdev_priv(dev); 1373 struct ioc3 *ioc3 = ip->regs; 1374 unsigned int len; 1375 struct ioc3_etxd *desc; 1376 uint32_t w0 = 0; 1377 int produce; 1378 1379 /* 1380 * IOC3 has a fairly simple minded checksumming hardware which simply 1381 * adds up the 1's complement checksum for the entire packet and 1382 * inserts it at an offset which can be specified in the descriptor 1383 * into the transmit packet. This means we have to compensate for the 1384 * MAC header which should not be summed and the TCP/UDP pseudo headers 1385 * manually. 1386 */ 1387 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1388 const struct iphdr *ih = ip_hdr(skb); 1389 const int proto = ntohs(ih->protocol); 1390 unsigned int csoff; 1391 uint32_t csum, ehsum; 1392 uint16_t *eh; 1393 1394 /* The MAC header. skb->mac seem the logic approach 1395 to find the MAC header - except it's a NULL pointer ... */ 1396 eh = (uint16_t *) skb->data; 1397 1398 /* Sum up dest addr, src addr and protocol */ 1399 ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6]; 1400 1401 /* Fold ehsum. can't use csum_fold which negates also ... */ 1402 ehsum = (ehsum & 0xffff) + (ehsum >> 16); 1403 ehsum = (ehsum & 0xffff) + (ehsum >> 16); 1404 1405 /* Skip IP header; it's sum is always zero and was 1406 already filled in by ip_output.c */ 1407 csum = csum_tcpudp_nofold(ih->saddr, ih->daddr, 1408 ih->tot_len - (ih->ihl << 2), 1409 proto, 0xffff ^ ehsum); 1410 1411 csum = (csum & 0xffff) + (csum >> 16); /* Fold again */ 1412 csum = (csum & 0xffff) + (csum >> 16); 1413 1414 csoff = ETH_HLEN + (ih->ihl << 2); 1415 if (proto == IPPROTO_UDP) { 1416 csoff += offsetof(struct udphdr, check); 1417 udp_hdr(skb)->check = csum; 1418 } 1419 if (proto == IPPROTO_TCP) { 1420 csoff += offsetof(struct tcphdr, check); 1421 tcp_hdr(skb)->check = csum; 1422 } 1423 1424 w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT); 1425 } 1426 1427 spin_lock_irq(&ip->ioc3_lock); 1428 1429 data = (unsigned long) skb->data; 1430 len = skb->len; 1431 1432 produce = ip->tx_pi; 1433 desc = &ip->txr[produce]; 1434 1435 if (len <= 104) { 1436 /* Short packet, let's copy it directly into the ring. */ 1437 skb_copy_from_linear_data(skb, desc->data, skb->len); 1438 if (len < ETH_ZLEN) { 1439 /* Very short packet, pad with zeros at the end. */ 1440 memset(desc->data + len, 0, ETH_ZLEN - len); 1441 len = ETH_ZLEN; 1442 } 1443 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0); 1444 desc->bufcnt = cpu_to_be32(len); 1445 } else if ((data ^ (data + len - 1)) & 0x4000) { 1446 unsigned long b2 = (data | 0x3fffUL) + 1UL; 1447 unsigned long s1 = b2 - data; 1448 unsigned long s2 = data + len - b2; 1449 1450 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | 1451 ETXD_B1V | ETXD_B2V | w0); 1452 desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) | 1453 (s2 << ETXD_B2CNT_SHIFT)); 1454 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1)); 1455 desc->p2 = cpu_to_be64(ioc3_map((void *) b2, 1)); 1456 } else { 1457 /* Normal sized packet that doesn't cross a page boundary. */ 1458 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0); 1459 desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT); 1460 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1)); 1461 } 1462 1463 BARRIER(); 1464 1465 dev->trans_start = jiffies; 1466 ip->tx_skbs[produce] = skb; /* Remember skb */ 1467 produce = (produce + 1) & 127; 1468 ip->tx_pi = produce; 1469 ioc3_w_etpir(produce << 7); /* Fire ... */ 1470 1471 ip->txqlen++; 1472 1473 if (ip->txqlen >= 127) 1474 netif_stop_queue(dev); 1475 1476 spin_unlock_irq(&ip->ioc3_lock); 1477 1478 return 0; 1479} 1480 1481static void ioc3_timeout(struct net_device *dev) 1482{ 1483 struct ioc3_private *ip = netdev_priv(dev); 1484 1485 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name); 1486 1487 spin_lock_irq(&ip->ioc3_lock); 1488 1489 ioc3_stop(ip); 1490 ioc3_init(dev); 1491 ioc3_mii_init(ip); 1492 ioc3_mii_start(ip); 1493 1494 spin_unlock_irq(&ip->ioc3_lock); 1495 1496 netif_wake_queue(dev); 1497} 1498 1499/* 1500 * Given a multicast ethernet address, this routine calculates the 1501 * address's bit index in the logical address filter mask 1502 */ 1503 1504static inline unsigned int ioc3_hash(const unsigned char *addr) 1505{ 1506 unsigned int temp = 0; 1507 u32 crc; 1508 int bits; 1509 1510 crc = ether_crc_le(ETH_ALEN, addr); 1511 1512 crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */ 1513 for (bits = 6; --bits >= 0; ) { 1514 temp <<= 1; 1515 temp |= (crc & 0x1); 1516 crc >>= 1; 1517 } 1518 1519 return temp; 1520} 1521 1522static void ioc3_get_drvinfo (struct net_device *dev, 1523 struct ethtool_drvinfo *info) 1524{ 1525 struct ioc3_private *ip = netdev_priv(dev); 1526 1527 strcpy (info->driver, IOC3_NAME); 1528 strcpy (info->version, IOC3_VERSION); 1529 strcpy (info->bus_info, pci_name(ip->pdev)); 1530} 1531 1532static int ioc3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1533{ 1534 struct ioc3_private *ip = netdev_priv(dev); 1535 int rc; 1536 1537 spin_lock_irq(&ip->ioc3_lock); 1538 rc = mii_ethtool_gset(&ip->mii, cmd); 1539 spin_unlock_irq(&ip->ioc3_lock); 1540 1541 return rc; 1542} 1543 1544static int ioc3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1545{ 1546 struct ioc3_private *ip = netdev_priv(dev); 1547 int rc; 1548 1549 spin_lock_irq(&ip->ioc3_lock); 1550 rc = mii_ethtool_sset(&ip->mii, cmd); 1551 spin_unlock_irq(&ip->ioc3_lock); 1552 1553 return rc; 1554} 1555 1556static int ioc3_nway_reset(struct net_device *dev) 1557{ 1558 struct ioc3_private *ip = netdev_priv(dev); 1559 int rc; 1560 1561 spin_lock_irq(&ip->ioc3_lock); 1562 rc = mii_nway_restart(&ip->mii); 1563 spin_unlock_irq(&ip->ioc3_lock); 1564 1565 return rc; 1566} 1567 1568static u32 ioc3_get_link(struct net_device *dev) 1569{ 1570 struct ioc3_private *ip = netdev_priv(dev); 1571 int rc; 1572 1573 spin_lock_irq(&ip->ioc3_lock); 1574 rc = mii_link_ok(&ip->mii); 1575 spin_unlock_irq(&ip->ioc3_lock); 1576 1577 return rc; 1578} 1579 1580static u32 ioc3_get_rx_csum(struct net_device *dev) 1581{ 1582 struct ioc3_private *ip = netdev_priv(dev); 1583 1584 return ip->flags & IOC3_FLAG_RX_CHECKSUMS; 1585} 1586 1587static int ioc3_set_rx_csum(struct net_device *dev, u32 data) 1588{ 1589 struct ioc3_private *ip = netdev_priv(dev); 1590 1591 spin_lock_bh(&ip->ioc3_lock); 1592 if (data) 1593 ip->flags |= IOC3_FLAG_RX_CHECKSUMS; 1594 else 1595 ip->flags &= ~IOC3_FLAG_RX_CHECKSUMS; 1596 spin_unlock_bh(&ip->ioc3_lock); 1597 1598 return 0; 1599} 1600 1601static const struct ethtool_ops ioc3_ethtool_ops = { 1602 .get_drvinfo = ioc3_get_drvinfo, 1603 .get_settings = ioc3_get_settings, 1604 .set_settings = ioc3_set_settings, 1605 .nway_reset = ioc3_nway_reset, 1606 .get_link = ioc3_get_link, 1607 .get_rx_csum = ioc3_get_rx_csum, 1608 .set_rx_csum = ioc3_set_rx_csum, 1609 .get_tx_csum = ethtool_op_get_tx_csum, 1610 .set_tx_csum = ethtool_op_set_tx_csum 1611}; 1612 1613static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1614{ 1615 struct ioc3_private *ip = netdev_priv(dev); 1616 int rc; 1617 1618 spin_lock_irq(&ip->ioc3_lock); 1619 rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL); 1620 spin_unlock_irq(&ip->ioc3_lock); 1621 1622 return rc; 1623} 1624 1625static void ioc3_set_multicast_list(struct net_device *dev) 1626{ 1627 struct dev_mc_list *dmi = dev->mc_list; 1628 struct ioc3_private *ip = netdev_priv(dev); 1629 struct ioc3 *ioc3 = ip->regs; 1630 u64 ehar = 0; 1631 int i; 1632 1633 netif_stop_queue(dev); /* Lock out others. */ 1634 1635 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 1636 ip->emcr |= EMCR_PROMISC; 1637 ioc3_w_emcr(ip->emcr); 1638 (void) ioc3_r_emcr(); 1639 } else { 1640 ip->emcr &= ~EMCR_PROMISC; 1641 ioc3_w_emcr(ip->emcr); /* Clear promiscuous. */ 1642 (void) ioc3_r_emcr(); 1643 1644 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) { 1645 /* Too many for hashing to make sense or we want all 1646 multicast packets anyway, so skip computing all the 1647 hashes and just accept all packets. */ 1648 ip->ehar_h = 0xffffffff; 1649 ip->ehar_l = 0xffffffff; 1650 } else { 1651 for (i = 0; i < dev->mc_count; i++) { 1652 char *addr = dmi->dmi_addr; 1653 dmi = dmi->next; 1654 1655 if (!(*addr & 1)) 1656 continue; 1657 1658 ehar |= (1UL << ioc3_hash(addr)); 1659 } 1660 ip->ehar_h = ehar >> 32; 1661 ip->ehar_l = ehar & 0xffffffff; 1662 } 1663 ioc3_w_ehar_h(ip->ehar_h); 1664 ioc3_w_ehar_l(ip->ehar_l); 1665 } 1666 1667 netif_wake_queue(dev); /* Let us get going again. */ 1668} 1669 1670MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); 1671MODULE_DESCRIPTION("SGI IOC3 Ethernet driver"); 1672MODULE_LICENSE("GPL"); 1673 1674module_init(ioc3_init_module); 1675module_exit(ioc3_cleanup_module); 1676