1/* 2 * Freescale Ethernet controllers 3 * 4 * Copyright (c) 2005 Intracom S.A. 5 * by Pantelis Antoniou <panto@intracom.gr> 6 * 7 * 2005 (c) MontaVista Software, Inc. 8 * Vitaly Bordug <vbordug@ru.mvista.com> 9 * 10 * This file is licensed under the terms of the GNU General Public License 11 * version 2. This program is licensed "as is" without any warranty of any 12 * kind, whether express or implied. 13 */ 14 15#include <linux/module.h> 16#include <linux/kernel.h> 17#include <linux/types.h> 18#include <linux/string.h> 19#include <linux/ptrace.h> 20#include <linux/errno.h> 21#include <linux/ioport.h> 22#include <linux/slab.h> 23#include <linux/interrupt.h> 24#include <linux/init.h> 25#include <linux/delay.h> 26#include <linux/netdevice.h> 27#include <linux/etherdevice.h> 28#include <linux/skbuff.h> 29#include <linux/spinlock.h> 30#include <linux/mii.h> 31#include <linux/ethtool.h> 32#include <linux/bitops.h> 33#include <linux/fs.h> 34#include <linux/platform_device.h> 35 36#include <asm/irq.h> 37#include <asm/uaccess.h> 38 39#ifdef CONFIG_8xx 40#include <asm/8xx_immap.h> 41#include <asm/pgtable.h> 42#include <asm/mpc8xx.h> 43#include <asm/commproc.h> 44#endif 45 46#include "fs_enet.h" 47#include "fec.h" 48 49/*************************************************/ 50 51#if defined(CONFIG_CPM1) 52/* for a CPM1 __raw_xxx's are sufficient */ 53#define __fs_out32(addr, x) __raw_writel(x, addr) 54#define __fs_out16(addr, x) __raw_writew(x, addr) 55#define __fs_in32(addr) __raw_readl(addr) 56#define __fs_in16(addr) __raw_readw(addr) 57#else 58/* for others play it safe */ 59#define __fs_out32(addr, x) out_be32(addr, x) 60#define __fs_out16(addr, x) out_be16(addr, x) 61#define __fs_in32(addr) in_be32(addr) 62#define __fs_in16(addr) in_be16(addr) 63#endif 64 65/* write */ 66#define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v)) 67 68/* read */ 69#define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg) 70 71/* set bits */ 72#define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v)) 73 74/* clear bits */ 75#define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v)) 76 77/* 78 * Delay to wait for FEC reset command to complete (in us) 79 */ 80#define FEC_RESET_DELAY 50 81 82static int whack_reset(fec_t * fecp) 83{ 84 int i; 85 86 FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET); 87 for (i = 0; i < FEC_RESET_DELAY; i++) { 88 if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0) 89 return 0; /* OK */ 90 udelay(1); 91 } 92 93 return -1; 94} 95 96static int do_pd_setup(struct fs_enet_private *fep) 97{ 98 struct platform_device *pdev = to_platform_device(fep->dev); 99 struct resource *r; 100 101 /* Fill out IRQ field */ 102 fep->interrupt = platform_get_irq_byname(pdev,"interrupt"); 103 if (fep->interrupt < 0) 104 return -EINVAL; 105 106 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); 107 fep->fec.fecp = ioremap(r->start, r->end - r->start + 1); 108 109 if(fep->fec.fecp == NULL) 110 return -EINVAL; 111 112 return 0; 113 114} 115 116#define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF | FEC_ENET_RXB) 117#define FEC_RX_EVENT (FEC_ENET_RXF) 118#define FEC_TX_EVENT (FEC_ENET_TXF) 119#define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR | FEC_ENET_BABR | \ 120 FEC_ENET_BABT | FEC_ENET_EBERR) 121 122static int setup_data(struct net_device *dev) 123{ 124 struct fs_enet_private *fep = netdev_priv(dev); 125 126 if (do_pd_setup(fep) != 0) 127 return -EINVAL; 128 129 fep->fec.hthi = 0; 130 fep->fec.htlo = 0; 131 132 fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK; 133 fep->ev_rx = FEC_RX_EVENT; 134 fep->ev_tx = FEC_TX_EVENT; 135 fep->ev_err = FEC_ERR_EVENT_MSK; 136 137 return 0; 138} 139 140static int allocate_bd(struct net_device *dev) 141{ 142 struct fs_enet_private *fep = netdev_priv(dev); 143 const struct fs_platform_info *fpi = fep->fpi; 144 145 fep->ring_base = dma_alloc_coherent(fep->dev, 146 (fpi->tx_ring + fpi->rx_ring) * 147 sizeof(cbd_t), &fep->ring_mem_addr, 148 GFP_KERNEL); 149 if (fep->ring_base == NULL) 150 return -ENOMEM; 151 152 return 0; 153} 154 155static void free_bd(struct net_device *dev) 156{ 157 struct fs_enet_private *fep = netdev_priv(dev); 158 const struct fs_platform_info *fpi = fep->fpi; 159 160 if(fep->ring_base) 161 dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring) 162 * sizeof(cbd_t), 163 fep->ring_base, 164 fep->ring_mem_addr); 165} 166 167static void cleanup_data(struct net_device *dev) 168{ 169 /* nothing */ 170} 171 172static void set_promiscuous_mode(struct net_device *dev) 173{ 174 struct fs_enet_private *fep = netdev_priv(dev); 175 fec_t *fecp = fep->fec.fecp; 176 177 FS(fecp, r_cntrl, FEC_RCNTRL_PROM); 178} 179 180static void set_multicast_start(struct net_device *dev) 181{ 182 struct fs_enet_private *fep = netdev_priv(dev); 183 184 fep->fec.hthi = 0; 185 fep->fec.htlo = 0; 186} 187 188static void set_multicast_one(struct net_device *dev, const u8 *mac) 189{ 190 struct fs_enet_private *fep = netdev_priv(dev); 191 int temp, hash_index, i, j; 192 u32 crc, csrVal; 193 u8 byte, msb; 194 195 crc = 0xffffffff; 196 for (i = 0; i < 6; i++) { 197 byte = mac[i]; 198 for (j = 0; j < 8; j++) { 199 msb = crc >> 31; 200 crc <<= 1; 201 if (msb ^ (byte & 0x1)) 202 crc ^= FEC_CRC_POLY; 203 byte >>= 1; 204 } 205 } 206 207 temp = (crc & 0x3f) >> 1; 208 hash_index = ((temp & 0x01) << 4) | 209 ((temp & 0x02) << 2) | 210 ((temp & 0x04)) | 211 ((temp & 0x08) >> 2) | 212 ((temp & 0x10) >> 4); 213 csrVal = 1 << hash_index; 214 if (crc & 1) 215 fep->fec.hthi |= csrVal; 216 else 217 fep->fec.htlo |= csrVal; 218} 219 220static void set_multicast_finish(struct net_device *dev) 221{ 222 struct fs_enet_private *fep = netdev_priv(dev); 223 fec_t *fecp = fep->fec.fecp; 224 225 /* if all multi or too many multicasts; just enable all */ 226 if ((dev->flags & IFF_ALLMULTI) != 0 || 227 dev->mc_count > FEC_MAX_MULTICAST_ADDRS) { 228 fep->fec.hthi = 0xffffffffU; 229 fep->fec.htlo = 0xffffffffU; 230 } 231 232 FC(fecp, r_cntrl, FEC_RCNTRL_PROM); 233 FW(fecp, hash_table_high, fep->fec.hthi); 234 FW(fecp, hash_table_low, fep->fec.htlo); 235} 236 237static void set_multicast_list(struct net_device *dev) 238{ 239 struct dev_mc_list *pmc; 240 241 if ((dev->flags & IFF_PROMISC) == 0) { 242 set_multicast_start(dev); 243 for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next) 244 set_multicast_one(dev, pmc->dmi_addr); 245 set_multicast_finish(dev); 246 } else 247 set_promiscuous_mode(dev); 248} 249 250static void restart(struct net_device *dev) 251{ 252#ifdef CONFIG_DUET 253 immap_t *immap = fs_enet_immap; 254 u32 cptr; 255#endif 256 struct fs_enet_private *fep = netdev_priv(dev); 257 fec_t *fecp = fep->fec.fecp; 258 const struct fs_platform_info *fpi = fep->fpi; 259 dma_addr_t rx_bd_base_phys, tx_bd_base_phys; 260 int r; 261 u32 addrhi, addrlo; 262 263 struct mii_bus* mii = fep->phydev->bus; 264 struct fec_info* fec_inf = mii->priv; 265 266 r = whack_reset(fep->fec.fecp); 267 if (r != 0) 268 printk(KERN_ERR DRV_MODULE_NAME 269 ": %s FEC Reset FAILED!\n", dev->name); 270 /* 271 * Set station address. 272 */ 273 addrhi = ((u32) dev->dev_addr[0] << 24) | 274 ((u32) dev->dev_addr[1] << 16) | 275 ((u32) dev->dev_addr[2] << 8) | 276 (u32) dev->dev_addr[3]; 277 addrlo = ((u32) dev->dev_addr[4] << 24) | 278 ((u32) dev->dev_addr[5] << 16); 279 FW(fecp, addr_low, addrhi); 280 FW(fecp, addr_high, addrlo); 281 282 /* 283 * Reset all multicast. 284 */ 285 FW(fecp, hash_table_high, fep->fec.hthi); 286 FW(fecp, hash_table_low, fep->fec.htlo); 287 288 /* 289 * Set maximum receive buffer size. 290 */ 291 FW(fecp, r_buff_size, PKT_MAXBLR_SIZE); 292 FW(fecp, r_hash, PKT_MAXBUF_SIZE); 293 294 /* get physical address */ 295 rx_bd_base_phys = fep->ring_mem_addr; 296 tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring; 297 298 /* 299 * Set receive and transmit descriptor base. 300 */ 301 FW(fecp, r_des_start, rx_bd_base_phys); 302 FW(fecp, x_des_start, tx_bd_base_phys); 303 304 fs_init_bds(dev); 305 306 /* 307 * Enable big endian and don't care about SDMA FC. 308 */ 309 FW(fecp, fun_code, 0x78000000); 310 311 /* 312 * Set MII speed. 313 */ 314 FW(fecp, mii_speed, fec_inf->mii_speed); 315 316 /* 317 * Clear any outstanding interrupt. 318 */ 319 FW(fecp, ievent, 0xffc0); 320#ifndef CONFIG_PPC_MERGE 321 FW(fecp, ivec, (fep->interrupt / 2) << 29); 322#else 323 FW(fecp, ivec, (virq_to_hw(fep->interrupt) / 2) << 29); 324#endif 325 326 /* 327 * adjust to speed (only for DUET & RMII) 328 */ 329#ifdef CONFIG_DUET 330 if (fpi->use_rmii) { 331 cptr = in_be32(&immap->im_cpm.cp_cptr); 332 switch (fs_get_fec_index(fpi->fs_no)) { 333 case 0: 334 cptr |= 0x100; 335 if (fep->speed == 10) 336 cptr |= 0x0000010; 337 else if (fep->speed == 100) 338 cptr &= ~0x0000010; 339 break; 340 case 1: 341 cptr |= 0x80; 342 if (fep->speed == 10) 343 cptr |= 0x0000008; 344 else if (fep->speed == 100) 345 cptr &= ~0x0000008; 346 break; 347 default: 348 BUG(); /* should never happen */ 349 break; 350 } 351 out_be32(&immap->im_cpm.cp_cptr, cptr); 352 } 353#endif 354 355 356 FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */ 357 /* 358 * adjust to duplex mode 359 */ 360 if (fep->phydev->duplex) { 361 FC(fecp, r_cntrl, FEC_RCNTRL_DRT); 362 FS(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */ 363 } else { 364 FS(fecp, r_cntrl, FEC_RCNTRL_DRT); 365 FC(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */ 366 } 367 368 /* 369 * Enable interrupts we wish to service. 370 */ 371 FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB | 372 FEC_ENET_RXF | FEC_ENET_RXB); 373 374 /* 375 * And last, enable the transmit and receive processing. 376 */ 377 FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN); 378 FW(fecp, r_des_active, 0x01000000); 379} 380 381static void stop(struct net_device *dev) 382{ 383 struct fs_enet_private *fep = netdev_priv(dev); 384 const struct fs_platform_info *fpi = fep->fpi; 385 fec_t *fecp = fep->fec.fecp; 386 387 struct fec_info* feci= fep->phydev->bus->priv; 388 389 int i; 390 391 if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0) 392 return; /* already down */ 393 394 FW(fecp, x_cntrl, 0x01); /* Graceful transmit stop */ 395 for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) && 396 i < FEC_RESET_DELAY; i++) 397 udelay(1); 398 399 if (i == FEC_RESET_DELAY) 400 printk(KERN_WARNING DRV_MODULE_NAME 401 ": %s FEC timeout on graceful transmit stop\n", 402 dev->name); 403 /* 404 * Disable FEC. Let only MII interrupts. 405 */ 406 FW(fecp, imask, 0); 407 FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN); 408 409 fs_cleanup_bds(dev); 410 411 /* shut down FEC1? that's where the mii bus is */ 412 if (fpi->has_phy) { 413 FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */ 414 FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN); 415 FW(fecp, ievent, FEC_ENET_MII); 416 FW(fecp, mii_speed, feci->mii_speed); 417 } 418} 419 420static void pre_request_irq(struct net_device *dev, int irq) 421{ 422#ifndef CONFIG_PPC_MERGE 423 immap_t *immap = fs_enet_immap; 424 u32 siel; 425 426 /* SIU interrupt */ 427 if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) { 428 429 siel = in_be32(&immap->im_siu_conf.sc_siel); 430 if ((irq & 1) == 0) 431 siel |= (0x80000000 >> irq); 432 else 433 siel &= ~(0x80000000 >> (irq & ~1)); 434 out_be32(&immap->im_siu_conf.sc_siel, siel); 435 } 436#endif 437} 438 439static void post_free_irq(struct net_device *dev, int irq) 440{ 441 /* nothing */ 442} 443 444static void napi_clear_rx_event(struct net_device *dev) 445{ 446 struct fs_enet_private *fep = netdev_priv(dev); 447 fec_t *fecp = fep->fec.fecp; 448 449 FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK); 450} 451 452static void napi_enable_rx(struct net_device *dev) 453{ 454 struct fs_enet_private *fep = netdev_priv(dev); 455 fec_t *fecp = fep->fec.fecp; 456 457 FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK); 458} 459 460static void napi_disable_rx(struct net_device *dev) 461{ 462 struct fs_enet_private *fep = netdev_priv(dev); 463 fec_t *fecp = fep->fec.fecp; 464 465 FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK); 466} 467 468static void rx_bd_done(struct net_device *dev) 469{ 470 struct fs_enet_private *fep = netdev_priv(dev); 471 fec_t *fecp = fep->fec.fecp; 472 473 FW(fecp, r_des_active, 0x01000000); 474} 475 476static void tx_kickstart(struct net_device *dev) 477{ 478 struct fs_enet_private *fep = netdev_priv(dev); 479 fec_t *fecp = fep->fec.fecp; 480 481 FW(fecp, x_des_active, 0x01000000); 482} 483 484static u32 get_int_events(struct net_device *dev) 485{ 486 struct fs_enet_private *fep = netdev_priv(dev); 487 fec_t *fecp = fep->fec.fecp; 488 489 return FR(fecp, ievent) & FR(fecp, imask); 490} 491 492static void clear_int_events(struct net_device *dev, u32 int_events) 493{ 494 struct fs_enet_private *fep = netdev_priv(dev); 495 fec_t *fecp = fep->fec.fecp; 496 497 FW(fecp, ievent, int_events); 498} 499 500static void ev_error(struct net_device *dev, u32 int_events) 501{ 502 printk(KERN_WARNING DRV_MODULE_NAME 503 ": %s FEC ERROR(s) 0x%x\n", dev->name, int_events); 504} 505 506int get_regs(struct net_device *dev, void *p, int *sizep) 507{ 508 struct fs_enet_private *fep = netdev_priv(dev); 509 510 if (*sizep < sizeof(fec_t)) 511 return -EINVAL; 512 513 memcpy_fromio(p, fep->fec.fecp, sizeof(fec_t)); 514 515 return 0; 516} 517 518int get_regs_len(struct net_device *dev) 519{ 520 return sizeof(fec_t); 521} 522 523void tx_restart(struct net_device *dev) 524{ 525 /* nothing */ 526} 527 528/*************************************************************************/ 529 530const struct fs_ops fs_fec_ops = { 531 .setup_data = setup_data, 532 .cleanup_data = cleanup_data, 533 .set_multicast_list = set_multicast_list, 534 .restart = restart, 535 .stop = stop, 536 .pre_request_irq = pre_request_irq, 537 .post_free_irq = post_free_irq, 538 .napi_clear_rx_event = napi_clear_rx_event, 539 .napi_enable_rx = napi_enable_rx, 540 .napi_disable_rx = napi_disable_rx, 541 .rx_bd_done = rx_bd_done, 542 .tx_kickstart = tx_kickstart, 543 .get_int_events = get_int_events, 544 .clear_int_events = clear_int_events, 545 .ev_error = ev_error, 546 .get_regs = get_regs, 547 .get_regs_len = get_regs_len, 548 .tx_restart = tx_restart, 549 .allocate_bd = allocate_bd, 550 .free_bd = free_bd, 551}; 552