1/*
2 * drivers/net/big_sur_ge.c - Driver for PMC-Sierra Big Sur ethernet ports
3 *
4 * Copyright (C) 2003 PMC-Sierra Inc.
5 * Author : Manish Lachwani (lachwani@pmc-sierra.com)
6 * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
21 *
22 */
23
24/*************************************************************************
25 * Description :
26 *
27 * The driver has three modes of operation: FIFO non-DMA, Simple DMA
28 * and SG DMA. There is also a Polled mode and an Interrupt mode of
29 * operation. SG DMA should do zerocopy and check offload. Probably,
30 * zerocopy on the Rx might also work. Simple DMA is the non-zerocpy
31 * case on the Tx and the Rx.
32 *
33 * We turn on Simple DMA and interrupt mode. Although, support has been
34 * added for the SG mode also but not for the polled mode. This is a
35 * Fast Ethernet driver although there will be support for Gigabit soon.
36 *
37 * The driver is divided into two parts: Hardware dependent and a
38 * Hardware independent. There is currently no support for checksum offload
39 * zerocopy and Rx NAPI. There is support for Interrupt Mitigation.
40 ****************************************************************************/
41
42/*************************************************************
43 * Hardware Indepenent Part of the driver
44 *************************************************************/
45
46#include <linux/module.h>
47#include <linux/init.h>
48#include <linux/netdevice.h>
49#include <linux/etherdevice.h>
50#include <linux/skbuff.h>
51#include <linux/mii.h>
52#include <asm/io.h>
53#include <asm/irq.h>
54
55#include "big_sur_ge.h"
56
57#define TX_TIMEOUT (60*HZ)	/* Transmission timeout is 60 seconds. */
58
59static struct net_device *dev_list = NULL;
60static DEFINE_SPINLOCK(dev_lock);
61
62typedef enum DUPLEX { UNKNOWN, HALF_DUPLEX, FULL_DUPLEX } DUPLEX;
63
64/* Big Sur Ethernet MAC structure */
65struct big_sur_ge_enet {
66	struct net_device_stats stats;	/* Statistics for this device */
67	struct net_device *next_dev;	/* The next device in dev_list */
68	struct timer_list phy_timer;	/* PHY monitoring timer */
69	u32 index;		/* Which interface is this */
70	u32 save_base_address;	/* Saved physical base address */
71	struct sk_buff *saved_skb;	/* skb being transmitted */
72	spinlock_t lock;	/* For atomic access to saved_skb */
73	u8 mii_addr;		/* The MII address of the PHY */
74	big_sur_ge emac;	/* GE driver structure */
75};
76
77/* Manish : For testing purposes only */
78static unsigned char big_sur_mac_addr_base[6] = "00:11:22:33:44:55";
79
80/*********************************************************************
81 * Function Prototypes (whole bunch of them)
82 *********************************************************************/
83unsigned long big_sur_ge_dma_control(xdma_channel *);
84void big_sur_ge_dma_reset(xdma_channel *);
85static void handle_fifo_intr(big_sur_ge *);
86void big_sur_ge_check_fifo_recv_error(big_sur_ge *);
87void big_sur_ge_check_fifo_send_error(big_sur_ge *);
88static int big_sur_ge_config_fifo(big_sur_ge *);
89big_sur_ge_config *big_sur_ge_lookup_config(unsigned int);
90static int big_sur_ge_config_dma(big_sur_ge *);
91void big_sur_ge_enet_reset(big_sur_ge *);
92void big_sur_ge_check_mac_error(big_sur_ge *, unsigned long);
93
94/*********************************************************************
95 * DMA Channel Initialization
96 **********************************************************************/
97static int big_sur_ge_dma_init(xdma_channel * dma, unsigned long base_address)
98{
99	dma->reg_base_address = base_address;
100	dma->get_ptr = NULL;
101	dma->put_ptr = NULL;
102	dma->commit_ptr = NULL;
103	dma->last_ptr = NULL;
104	dma->total_desc_count = (unsigned long) NULL;
105	dma->active_desc_count = (unsigned long) NULL;
106	dma->ready = 1;		/* DMA channel is ready */
107
108	big_sur_ge_dma_reset(dma);
109
110	return 0;
111}
112
113/*********************************************************************
114 * Is the DMA channel ready yet ?
115 **********************************************************************/
116static int big_sur_ge_dma_ready(xdma_channel * dma)
117{
118	return dma->ready == 1;
119}
120
121/*********************************************************************
122 * Perform the self test on the DMA channel
123 **********************************************************************/
124#define BIG_SUR_GE_CONTROL_REG_RESET_MASK	0x98000000
125
126static int big_sur_ge_dma_self_test(xdma_channel * dma)
127{
128	unsigned long reg_data;
129
130	big_sur_ge_dma_reset(dma);
131
132	reg_data = big_sur_ge_dma_control(dma);
133	if (reg_data != BIG_SUR_GE_CONTROL_REG_RESET_MASK) {
134		printk(KERN_ERR "DMA Channel Self Test Failed \n");
135		return -1;
136	}
137
138	return 0;
139}
140
141/*********************************************************************
142 * Reset the DMA channel
143 **********************************************************************/
144static void big_sur_ge_dma_reset(xdma_channel * dma)
145{
146	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_RST_REG_OFFSET,
147			 BIG_SUR_GE_RESET_MASK);
148}
149
150/*********************************************************************
151 * Get control of the DMA channel
152 **********************************************************************/
153static unsigned long big_sur_ge_dma_control(xdma_channel * dma)
154{
155	return BIG_SUR_GE_READ(dma->reg_base_address +
156			       BIG_SUR_GE_DMAC_REG_OFFSET);
157}
158
159/*********************************************************************
160 * Set control of the DMA channel
161 **********************************************************************/
162static void big_sur_ge_set_dma_control(xdma_channel * dma, unsigned long control)
163{
164	BIG_SUR_GE_WRITE(dma->reg_base_address +
165			 BIG_SUR_GE_DMAC_REG_OFFSET, control);
166}
167
168/*********************************************************************
169 * Get the status of the DMA channel
170 *********************************************************************/
171static unsigned long big_sur_ge_dma_status(xdma_channel * dma)
172{
173	return BIG_SUR_GE_READ(dma->reg_base_address +
174			       BIG_SUR_GE_DMAS_REG_OFFSET);
175}
176
177/*********************************************************************
178 * Set the interrupt status of the DMA channel
179 *********************************************************************/
180static void big_sur_ge_set_intr_status(xdma_channel * dma, unsigned long status)
181{
182	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_IS_REG_OFFSET,
183			 status);
184}
185
186/*********************************************************************
187 * Get the interrupt status of the DMA channel
188 *********************************************************************/
189static unsigned long big_sur_ge_get_intr_status(xdma_channel * dma)
190{
191	return BIG_SUR_GE_READ(dma->reg_base_address +
192			       BIG_SUR_GE_IS_REG_OFFSET);
193}
194
195/*********************************************************************
196 * Set the Interrupt Enable
197 *********************************************************************/
198static void big_sur_ge_set_intr_enable(xdma_channel * dma, unsigned long enable)
199{
200	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_IE_REG_OFFSET,
201			 enable);
202}
203
204/*********************************************************************
205 * Get the Interrupt Enable field to make a check
206 *********************************************************************/
207static unsigned long big_sur_ge_get_intr_enable(xdma_channel * dma)
208{
209	return BIG_SUR_GE_READ(dma->reg_base_address +
210			       BIG_SUR_GE_IE_REG_OFFSET);
211}
212
213/*********************************************************************
214 * Transfer the data over the DMA channel
215 *********************************************************************/
216static void big_sur_ge_dma_transfer(xdma_channel * dma, unsigned long *source,
217			     unsigned long *dest, unsigned long length)
218{
219	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_SA_REG_OFFSET,
220			 (unsigned long) source);
221
222	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_DA_REG_OFFSET,
223			 (unsigned long) dest);
224
225	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_LEN_REG_OFFSET,
226			 length);
227}
228
229/*********************************************************************
230 * Get the DMA descriptor
231 *********************************************************************/
232static int big_sur_ge_get_descriptor(xdma_channel * dma,
233			      xbuf_descriptor ** buffer_desc)
234{
235	unsigned long reg_data;
236
237	reg_data = xbuf_descriptor_GetControl(dma->get_ptr);
238	xbuf_descriptor_SetControl(dma->get_ptr, reg_data |
239				   BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
240
241	*buffer_desc = dma->get_ptr;
242
243	dma->get_ptr = xbuf_descriptor_GetNextPtr(dma->get_ptr);
244	dma->active_desc_count--;
245
246	return 0;
247}
248
249/*********************************************************************
250 * Get the packet count
251 *********************************************************************/
252static int big_sur_ge_get_packet_count(xdma_channel * dma)
253{
254	return (BIG_SUR_GE_READ
255		(dma->reg_base_address + BIG_SUR_GE_UPC_REG_OFFSET));
256}
257
258/*********************************************************************
259 * Descrement the packet count
260 *********************************************************************/
261static void big_sur_ge_decr_packet_count(xdma_channel * dma)
262{
263	unsigned long reg_data;
264
265	reg_data =
266	    BIG_SUR_GE_READ(dma->base_address + BIG_SUR_GE_UPC_REG_OFFSET);
267	if (reg_data > 0)
268		BIG_SUR_GE_WRITE(dma->base_address +
269				 BIG_SUR_GE_UPC_REG_OFFSET, 1);
270}
271
272/****************************************************************************
273 * Start of the code that deals with the Packet Fifo
274 *****************************************************************************/
275
276/****************************************************************************
277 * Init the packet fifo
278 ****************************************************************************/
279static int packet_fifo_init(packet_fifo * fifo, u32 reg, u32 data)
280{
281	fifo->reg_base_addr = reg;
282	fifo->data_base_address = data;
283	fifo->ready_status = 1;
284
285	BIG_SUR_GE_FIFO_RESET(fifo);
286
287	return 0;
288}
289
290/****************************************************************************
291 * Packet fifo self test
292 ****************************************************************************/
293static int packet_fifo_self_test(packet_fifo * fifo, unsigned long type)
294{
295	unsigned long reg_data;
296
297	BIG_SUR_GE_FIFO_RESET(fifo);
298	reg_data =
299	    BIG_SUR_GE_READ(fifo->reg_base_addr +
300			    BIG_SUR_GE_COUNT_STATUS_REG_OFFSET);
301
302	if (type == BIG_SUR_GE_READ_FIFO_TYPE) {
303		if (reg_data != BIG_SUR_GE_EMPTY_FULL_MASK) {
304			printk(KERN_ERR "Read FIFO not empty \n");
305			return -1;
306		}
307	} else if (!(reg_data & BIG_SUR_GE_EMPTY_FULL_MASK)) {
308		printk(KERN_ERR "Write FIFO is full \n");
309		return -1;
310	}
311
312	return 0;
313}
314
315/****************************************************************************
316 * Packet FIFO read
317 ****************************************************************************/
318static int packet_fifo_read(packet_fifo * fifo, u8 * buffer, unsigned int len)
319{
320	unsigned long fifo_count, word_count, extra_byte;
321	unsigned long *buffer_data = (unsigned long *) buffer;
322
323	fifo_count =
324	    BIG_SUR_GE_READ(fifo->reg_base_addr +
325			    BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT);
326	fifo_count &= BIG_SUR_GE_COUNT_MASK;
327
328	if ((fifo_count * BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT) < len)
329		return -1;
330
331	word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
332	extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
333
334	for (fifo_count = 0; fifo_count < word_count; fifo_count++)
335		buffer_data[fifo_count] =
336		    BIG_SUR_GE_READ(fifo->reg_base_addr);
337
338	if (extra_byte > 0) {
339		unsigned long last_word;
340		int *extra_buffer_data =
341		    (int *) (buffer_data + word_count);
342
343		last_word = BIG_SUR_GE_READ(fifo->data_base_address);
344		if (extra_byte == 1)
345			extra_buffer_data[0] = (int) (last_word << 24);
346		else if (extra_byte == 2) {
347			extra_buffer_data[0] = (int) (last_word << 24);
348			extra_buffer_data[1] = (int) (last_word << 16);
349		} else if (extra_byte == 3) {
350			extra_buffer_data[0] = (int) (last_word << 24);
351			extra_buffer_data[1] = (int) (last_word << 16);
352			extra_buffer_data[2] = (int) (last_word << 8);
353		}
354	}
355
356	return 0;
357}
358
359/*****************************************************************************
360 * Write the data into the packet fifo
361 *****************************************************************************/
362static int packet_fifo_write(packet_fifo * fifo, int *buffer, int len)
363{
364	unsigned long fifo_count, word_count, extra_byte;
365	unsigned long *buffer_data = (unsigned long *) buffer;
366
367	fifo_count =
368	    BIG_SUR_GE_READ(fifo->reg_base_addr +
369			    BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT);
370	fifo_count &= BIG_SUR_GE_COUNT_MASK;
371
372	word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
373	extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
374
375	/* You should see what the ppc driver does here. It just slobbers */
376	if (extra_byte > 0)
377		if (fifo_count > (word_count + 1)) {
378			printk(KERN_ERR
379			       "No room in the packet send fifo \n");
380			return -1;
381		}
382
383	for (fifo_count = 0; fifo_count < word_count; fifo_count++)
384		BIG_SUR_GE_WRITE(fifo->data_base_address,
385				 buffer_data[fifo_count]);
386
387
388	if (extra_byte > 0) {
389		unsigned long last_word = 0;
390		int *extra_buffer_data =
391		    (int *) (buffer_data + word_count);
392
393		if (extra_byte == 1)
394			last_word = extra_buffer_data[0] << 24;
395		else if (extra_byte == 2)
396			last_word = (extra_buffer_data[0] << 24 |
397				     extra_buffer_data[1] << 16);
398
399		else if (extra_byte == 3)
400			last_word = (extra_buffer_data[0] << 24 |
401				     extra_buffer_data[1] << 16 |
402				     extra_buffer_data[2] << 8);
403
404
405		BIG_SUR_GE_WRITE(fifo->data_base_address, last_word);
406	}
407
408	return 0;
409}
410
411
412/*****************************************************************************
413 * Interrupt handlers: We handle any errors associated with the FIFO.
414 * FIFO is for simple dma case and we do want to handle the simple DMA
415 * case. We dont handle the Scatter Gather DMA for now since it is not working.
416 ******************************************************************************/
417
418/*********************************************************************************
419 * FIFO send for Simple DMA with Interrupts
420 **********************************************************************************/
421static int big_sur_ge_enet_fifo_send(big_sur_ge * emac, u8 * buffer,
422			      unsigned long byte_cnt)
423{
424	unsigned long int_status, reg_data;
425
426	/* Silly checks here that we really dont need */
427	if (!emac->started)
428		return -1;
429
430	if (emac->polled)
431		return -1;
432
433	if (emac->dma_sg)
434		return -1;
435
436	int_status =
437	    BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
438	if (int_status & BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK) {
439		printk(KERN_ERR "Tx FIFO error: Queue is Full \n");
440		return -1;
441	}
442
443	/*
444	 * Write the data to the FIFO in the hardware
445	 */
446	if ((BIG_SUR_GE_GET_COUNT(&emac->send_fifo) *
447	     sizeof(unsigned long)) < byte_cnt) {
448		printk(KERN_ERR "Send FIFO on chip is full \n");
449		return -1;
450	}
451
452	if (big_sur_ge_dma_status(&emac->send_channel) &
453	    BIG_SUR_GE_DMASR_BUSY_MASK) {
454		printk(KERN_ERR "Send channel FIFO engine busy \n");
455		return -1;
456	}
457
458	big_sur_ge_set_dma_control(&emac->send_channel,
459				   BIG_SUR_GE_DMACR_SOURCE_INCR_MASK |
460				   BIG_SUR_GE_DMACR_DEST_LOCAL_MASK |
461				   BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
462
463	big_sur_ge_dma_transfer(&emac->send_channel,
464				(unsigned long *) buffer,
465				(unsigned long *) (emac->base_address +
466						   BIG_SUR_GE_PFIFO_TXDATA_OFFSET),
467				byte_cnt);
468
469	reg_data = big_sur_ge_dma_status(&emac->send_channel);
470	while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) {
471		reg_data = big_sur_ge_dma_status(&emac->recv_channel);
472		if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK))
473			break;
474	}
475
476	if ((reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) ||
477	    (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) {
478		printk(KERN_ERR "Send side DMA error \n");
479		return -1;
480	}
481
482	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_TPLR_OFFSET,
483			 byte_cnt);
484
485	return 0;
486}
487
488/*************************************************************************
489 * FIFO receive for Simple DMA case
490 *************************************************************************/
491static int big_sur_ge_enet_fifo_recv(big_sur_ge * emac, u8 * buffer,
492			      unsigned long *byte_cnt)
493{
494	unsigned long int_status, reg_data;
495
496	/* Silly checks here that we really dont need */
497	if (!emac->started)
498		return -1;
499
500	if (emac->polled)
501		return -1;
502
503	if (emac->dma_sg)
504		return -1;
505
506	if (*byte_cnt < BIG_SUR_GE_MAX_FRAME_SIZE)
507		return -1;
508
509	int_status =
510	    BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
511	if (int_status & BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK) {
512		BIG_SUR_GE_WRITE(emac->base_address +
513				 XIIF_V123B_IISR_OFFSET,
514				 BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK);
515		return -1;
516	}
517
518	if (big_sur_ge_dma_status(&emac->recv_channel) &
519	    BIG_SUR_GE_DMASR_BUSY_MASK) {
520		printk(KERN_ERR "Rx side DMA Engine busy \n");
521		return -1;
522	}
523
524	if (BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET) ==
525	    0) {
526		printk(KERN_ERR "MAC has the FIFO packet length 0 \n");
527		return -1;
528	}
529
530	/* For the simple DMA case only */
531	big_sur_ge_set_dma_control(&emac->recv_channel,
532				   BIG_SUR_GE_DMACR_DEST_INCR_MASK |
533				   BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK |
534				   BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
535
536	if (packet_fifo_read(&emac->recv_fifo, buffer,
537			     BIG_SUR_GE_READ(emac->base_address +
538					     BIG_SUR_GE_RPLR_OFFSET)) ==
539	    -1) {
540		printk(KERN_ERR "Not enough space in the FIFO \n");
541		return -1;
542	}
543
544	big_sur_ge_dma_transfer(&emac->recv_channel,
545				(unsigned long *) (emac->base_address +
546						   BIG_SUR_GE_PFIFO_RXDATA_OFFSET),
547				(unsigned long *)
548				buffer,
549				BIG_SUR_GE_READ(emac->base_address +
550						BIG_SUR_GE_RPLR_OFFSET));
551
552	reg_data = big_sur_ge_dma_status(&emac->recv_channel);
553	while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) {
554		reg_data = big_sur_ge_dma_status(&emac->recv_channel);
555		if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK))
556			break;
557	}
558
559	if ((reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) ||
560	    (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) {
561		printk(KERN_ERR "DMA Bus Error \n");
562		return -1;
563	}
564
565	*byte_cnt =
566	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET);
567
568	return 0;
569}
570
571static irqreturn_t big_sur_ge_int_handler(int irq, void *dev_id)
572{
573	struct net_device *netdev = dev_id;
574	struct big_sur_ge_enet *lp = netdev->priv;
575	big_sur_ge *emac = (big_sur_ge *)emac_ptr;
576	void *emac_ptr = &lp->emac;
577	unsigned long int_status;
578
579	int_status =
580	    BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_DIPR_OFFSET);
581	if (int_status & BIG_SUR_GE_IPIF_EMAC_MASK)
582		handle_fifo_intr(emac);
583
584	if (int_status & BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
585		big_sur_ge_check_fifo_recv_error(emac);
586
587	if (int_status & BIG_SUR_GE_IPIF_SEND_FIFO_MASK)
588		big_sur_ge_check_fifo_send_error(emac);
589
590	if (int_status & XIIF_V123B_ERROR_MASK)
591		BIG_SUR_GE_WRITE(emac->base_address +
592				 XIIF_V123B_DISR_OFFSET,
593				 XIIF_V123B_ERROR_MASK);
594
595	return IRQ_HANDLED;
596}
597
598/****************************************************************************
599 * Set the FIFO send handler
600 ***************************************************************************/
601static void big_sur_ge_set_fifo_send_handler(big_sur_ge * emac, void *call_back,
602				      big_sur_fifo_handler function)
603{
604	emac->big_sur_ge_fifo_send_handler = function;
605	emac->fifo_send_ref = call_back;
606}
607
608/****************************************************************************
609 * Set the FIFO recv handler
610 ***************************************************************************/
611static void big_sur_ge_set_fifo_recv_handler(big_sur_ge * emac, void *call_back,
612				      big_sur_fifo_handler function)
613{
614	emac->big_sur_ge_fifo_recv_handler = function;
615	emac->fifo_recv_ref = call_back;
616}
617
618/****************************************************************************
619 * Main Fifo intr handler
620 ***************************************************************************/
621static void handle_fifo_intr(big_sur_ge * emac)
622{
623	unsigned long int_status;
624
625	/* Ack the interrupts asap */
626	int_status =
627	    BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
628	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IISR_OFFSET,
629			 int_status);
630
631	/* Process the Rx side */
632	if (int_status & BIG_SUR_GE_EIR_RECV_DONE_MASK) {
633		emac->big_sur_ge_fifo_recv_handler(&emac->fifo_recv_ref);
634		BIG_SUR_GE_WRITE(emac->base_address +
635				 XIIF_V123B_IISR_OFFSET,
636				 BIG_SUR_GE_EIR_RECV_DONE_MASK);
637	}
638
639	if (int_status & BIG_SUR_GE_EIR_XMIT_DONE_MASK) {
640		/* We dont collect stats and hence we dont need to get status */
641
642		emac->big_sur_ge_fifo_send_handler(emac->fifo_recv_ref);
643		BIG_SUR_GE_WRITE(emac->base_address +
644				 XIIF_V123B_IISR_OFFSET,
645				 BIG_SUR_GE_EIR_XMIT_DONE_MASK);
646	}
647
648	big_sur_ge_check_mac_error(emac, int_status);
649}
650
651/******************************************************************
652 * Handle the Receive side DMA interrupts. The PPC driver has
653 * callbacks all over the place. This has been eliminated here by
654 * using the following approach:
655 *
656 * The ISR is set to the main interrrupt handler. This will handle
657 * all the interrupts including the ones for DMA. In this main isr,
658 * we determine if we need to call recv or send side intr functions.
659 * Pretty complex but thats the way it is now.
660 *******************************************************************/
661static void big_sur_ge_handle_recv_intr(big_sur_ge * emac)
662{
663	unsigned long int_status;
664
665	int_status = big_sur_ge_get_intr_status(&emac->recv_channel);
666	if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK |
667			  BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK)) {
668		u32 num_packets;
669		u32 num_processed;
670		u32 num_buffers;
671		u32 num_bytes;
672		xbuf_descriptor *first_desc_ptr = NULL;
673		xbuf_descriptor *buffer_desc;
674		int is_last = 0;
675
676		/* The number of packets we need to process on the Rx */
677		num_packets =
678		    big_sur_ge_get_packet_count(&emac->recv_channel);
679
680		for (num_processed = 0; num_processed < num_packets;
681		     num_processed++) {
682			while (!is_last) {
683				if (big_sur_ge_get_descriptor
684				    (&emac->recv_channel,
685				     &buffer_desc) == -1)
686					break;
687
688				if (first_desc_ptr == NULL)
689					first_desc_ptr = buffer_desc;
690
691				num_bytes +=
692				    xbuf_descriptor_GetLength(buffer_desc);
693
694				if (xbuf_descriptor_IsLastStatus
695				    (buffer_desc)) {
696					is_last = 1;
697				}
698
699				num_buffers++;
700			}
701
702			/* Number of buffers is always 1 since we dont do SG */
703
704			/*
705			 * Only for SG DMA which is currently not supported. In the
706			 * future, as we have SG channel working, we will code this
707			 * receive side routine. For now, do nothing. This is never
708			 * called from FIFO mode - Manish
709			 */
710			big_sur_ge_decr_packet_count(&emac->recv_channel);
711		}
712	}
713
714	/* Ack the interrupts */
715	big_sur_ge_set_intr_status(&emac->recv_channel, int_status);
716
717	if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) {
718		/* We need a reset here */
719	}
720
721	big_sur_ge_set_intr_status(&emac->recv_channel, int_status);
722}
723
724/****************************************************************
725 * Handle the send side DMA interrupt
726 ****************************************************************/
727static void big_sur_ge_handle_send_intr(big_sur_ge * emac)
728{
729	unsigned long int_status;
730
731	int_status = big_sur_ge_get_intr_status(&emac->send_channel);
732
733	if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK |
734			  BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK)) {
735		unsigned long num_frames = 0;
736		unsigned long num_processed = 0;
737		unsigned long num_buffers = 0;
738		unsigned long num_bytes = 0;
739		unsigned long is_last = 0;
740		xbuf_descriptor *first_desc_ptr = NULL;
741		xbuf_descriptor *buffer_desc;
742
743		num_frames =
744		    big_sur_ge_get_packet_count(&emac->send_channel);
745
746		for (num_processed = 0; num_processed < num_frames;
747		     num_processed++) {
748			while (!is_last) {
749				if (big_sur_ge_get_descriptor
750				    (&emac->send_channel, &buffer_desc)
751				    == -1) {
752					break;
753				}
754
755				if (first_desc_ptr == NULL)
756					first_desc_ptr = buffer_desc;
757
758				num_bytes +=
759				    xbuf_descriptor_GetLength(buffer_desc);
760				if (xbuf_descriptor_IsLastControl
761				    (buffer_desc))
762					is_last = 1;
763
764				num_buffers++;
765			}
766
767			/*
768			 * Only for SG DMA which is currently not supported. In the
769			 * future, as we have SG channel working, we will code this
770			 * receive side routine. For now, do nothing. This is never
771			 * called from FIFO mode - Manish
772			 */
773			big_sur_ge_decr_packet_count(&emac->send_channel);
774		}
775	}
776
777	/* Ack the interrupts and reset DMA channel if necessary */
778	big_sur_ge_set_intr_status(&emac->send_channel, int_status);
779	if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) {
780		/* Manish : need reset */
781	}
782
783	big_sur_ge_set_intr_status(&emac->send_channel, int_status);
784}
785
786/*****************************************************************
787 * For now, the MAC address errors dont trigger a update of the
788 * stats. There is no stats framework in place. Hence, we just
789 * check for the errors below and do a reset if needed.
790 *****************************************************************/
791static void big_sur_ge_check_mac_error(big_sur_ge * emac,
792				unsigned long int_status)
793{
794	if (int_status & (BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK |
795			  BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK |
796			  BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK |
797			  BIG_SUR_GE_EIR_RECV_ERROR_MASK |
798			  BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK |
799			  BIG_SUR_GE_EIR_RECV_COLLISION_MASK |
800			  BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK |
801			  BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK |
802			  BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK |
803			  BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK |
804			  BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK |
805			  BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK |
806			  BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK |
807			  BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK |
808			  BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK)) {
809
810		BIG_SUR_GE_WRITE(emac->base_address +
811				 XIIF_V123B_IIER_OFFSET, 0);
812		/*
813		 * Manish Reset the MAC here
814		 */
815	}
816}
817
818/*****************************************************************
819 * Check for FIFO Recv errors
820 *****************************************************************/
821static void big_sur_ge_check_fifo_recv_error(big_sur_ge * emac)
822{
823	if (BIG_SUR_GE_IS_DEADLOCKED(&emac->recv_fifo)) {
824		unsigned long intr_enable;
825
826		intr_enable =
827		    BIG_SUR_GE_READ(emac->base_address +
828				    XIIF_V123B_DIER_OFFSET);
829		BIG_SUR_GE_WRITE(emac->base_address +
830				 XIIF_V123B_DIER_OFFSET,
831				 intr_enable &
832				 ~(BIG_SUR_GE_IPIF_RECV_FIFO_MASK));
833
834	}
835}
836
837/*****************************************************************
838 * Check for FIFO Send errors
839 *****************************************************************/
840static void big_sur_ge_check_fifo_send_error(big_sur_ge * emac)
841{
842	if (BIG_SUR_GE_IS_DEADLOCKED(&emac->send_fifo)) {
843		unsigned long intr_enable;
844
845		intr_enable =
846		    BIG_SUR_GE_READ(emac->base_address +
847				    XIIF_V123B_DIER_OFFSET);
848		BIG_SUR_GE_WRITE(emac->base_address +
849				 XIIF_V123B_DIER_OFFSET,
850				 intr_enable &
851				 ~(BIG_SUR_GE_IPIF_SEND_FIFO_MASK));
852	}
853}
854
855/*****************************************************************
856 * GE unit init
857 ****************************************************************/
858static int big_sur_ge_enet_init(big_sur_ge * emac, unsigned int device_id)
859{
860	unsigned long reg_data;
861	big_sur_ge_config *config;
862	int err;
863
864	/* Assume that the device has been stopped */
865
866	config = big_sur_ge_lookup_config(device_id);
867	if (config == NULL)
868		return -1;
869
870	emac->ready = 0;
871	emac->started = 0;
872	emac->dma_sg = 0;	/* This MAC has no support for Scatter Gather DMA */
873	emac->has_mii = config->has_mii;
874	emac->has_mcast_hash_table = 0;
875	emac->dma_config = config->dma_config;
876
877	/*
878	 * Initialize the FIFO send and recv handlers to the stub handlers.
879	 * We only deal with the FIFO mode of operation since SG is not supported.
880	 * Also, there is no error handler. We try to handle as much of error as
881	 * possible and then return. No error codes also.
882	 */
883
884	emac->base_address = config->base_address;
885
886	if (big_sur_ge_config_dma(emac) == -1)
887		return -1;
888
889	err = big_sur_ge_config_fifo(emac);
890	if (err == -1)
891		return err;
892
893	/* Now, we know that the FIFO initialized successfully. So, set the ready flag */
894	emac->ready = 1;
895
896	/* Do we need a PHY reset here also. It did cause problems on some boards */
897	big_sur_ge_enet_reset(emac);
898
899	/* PHY reset code. Remove if causes a problem on the board */
900	reg_data =
901	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
902	reg_data &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK);
903	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
904			 reg_data);
905	reg_data |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK;
906	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
907			 reg_data);
908
909	return 0;
910}
911
912/*******************************************************************
913 * Start the GE unit for Tx, Rx and Interrupts
914 *******************************************************************/
915static int big_sur_ge_start(big_sur_ge * emac)
916{
917	unsigned long reg_data;
918
919	/*
920	 * Basic mode of operation is polled and interrupt mode. We disable the polled
921	 * mode for good. We may use the polled mode for Rx NAPI but that does not
922	 * require all the interrupts to be disabled
923	 */
924
925	emac->polled = 0;
926
927	/*
928	 * DMA: Three modes of operation - simple, FIFO, SG. SG is surely not working
929	 * and so is kept off using the dma_sg flag. Simple and FIFO work. But, we may
930	 * not use FIFO at all. So, we enable the interrupts below
931	 */
932
933	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DIER_OFFSET,
934			 BIG_SUR_GE_IPIF_FIFO_DFT_MASK |
935			 XIIF_V123B_ERROR_MASK);
936
937	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IIER_OFFSET,
938			 BIG_SUR_GE_EIR_DFT_FIFO_MASK);
939
940	/* Toggle the started flag */
941	emac->started = 1;
942
943	/* Start the Tx and Rx units respectively */
944	reg_data =
945	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
946	reg_data &=
947	    ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK |
948	      BIG_SUR_GE_ECR_RECV_RESET_MASK);
949	reg_data |=
950	    (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK |
951	     BIG_SUR_GE_ECR_RECV_ENABLE_MASK);
952
953	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
954			 reg_data);
955
956	return 0;
957}
958
959/**************************************************************************
960 * Stop the GE unit
961 **************************************************************************/
962static int big_sur_ge_stop(big_sur_ge * emac)
963{
964	unsigned long reg_data;
965
966	/* We assume that the device is not already stopped */
967	if (!emac->started)
968		return 0;
969
970	/* Disable the Tx and Rx unit respectively */
971	reg_data =
972	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
973	reg_data &=
974	    ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK |
975	      BIG_SUR_GE_ECR_RECV_ENABLE_MASK);
976	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
977			 reg_data);
978
979	/* Disable the interrupts */
980	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DGIER_OFFSET, 0);
981
982	/* Toggle the started flag */
983	emac->started = 0;
984
985	return 0;
986}
987
988/************************************************************************
989 * Reset the GE MAC unit
990 *************************************************************************/
991static void big_sur_ge_enet_reset(big_sur_ge * emac)
992{
993	unsigned long reg_data;
994
995	(void) big_sur_ge_stop(emac);
996
997	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_RESETR_OFFSET,
998			 XIIF_V123B_RESET_MASK);
999
1000	/*
1001	 * For now, configure the receiver to not strip off FCS and padding since
1002	 * this is not currently supported. In the future, just take the default
1003	 * and provide the option for the user to change this behavior.
1004	 */
1005	reg_data =
1006	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
1007	reg_data &=
1008	    ~(BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK |
1009	      BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK);
1010	reg_data &= ~(BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK);
1011	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
1012			 reg_data);
1013}
1014
1015/*************************************************************************
1016 * Set the MAC address of the GE mac unit
1017 *************************************************************************/
1018static int big_sur_ge_set_mac_address(big_sur_ge * emac, unsigned char *addr)
1019{
1020	unsigned long mac_addr = 0;
1021
1022	/* Device is started and so mac address must be set */
1023	if (emac->started == 1)
1024		return 0;
1025
1026	mac_addr = ((addr[0] << 8) | addr[1]);
1027	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAH_OFFSET,
1028			 mac_addr);
1029
1030	mac_addr |= ((addr[2] << 24) | (addr[3] << 16) |
1031		     (addr[4] << 8) | addr[5]);
1032
1033	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAL_OFFSET,
1034			 mac_addr);
1035
1036	return 0;
1037}
1038
1039/****************************************************************************
1040 * Get the MAC address of the GE MAC unit
1041 ***************************************************************************/
1042static void big_sur_ge_get_mac_unit(big_sur_ge * emac, unsigned int *addr)
1043{
1044	unsigned long mac_addr_hi, mac_addr_lo;
1045
1046	mac_addr_hi =
1047	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAH_OFFSET);
1048	mac_addr_lo =
1049	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAL_OFFSET);
1050
1051	addr[0] = (mac_addr_hi >> 8);
1052	addr[1] = mac_addr_hi;
1053
1054	addr[2] = (mac_addr_lo >> 24);
1055	addr[3] = (mac_addr_lo >> 16);
1056	addr[4] = (mac_addr_lo >> 8);
1057	addr[5] = mac_addr_lo;
1058}
1059
1060/*********************************************************************************
1061 * Configure the GE MAC for DMA capabilities. Not for Scatter Gather, only Simple
1062 *********************************************************************************/
1063static int big_sur_ge_config_dma(big_sur_ge * emac)
1064{
1065	if (big_sur_ge_dma_init(&emac->recv_channel, emac->base_address +
1066				BIG_SUR_GE_DMA_RECV_OFFSET) == -1) {
1067		printk(KERN_ERR "Could not initialize the DMA unit  \n");
1068		return -1;
1069	}
1070
1071	if (big_sur_ge_dma_init(&emac->send_channel, emac->base_address +
1072				BIG_SUR_GE_DMA_SEND_OFFSET) == -1) {
1073		printk(KERN_ERR "Could not initialize the DMA unit  \n");
1074		return -1;
1075	}
1076
1077	return 0;
1078}
1079
1080/******************************************************************************
1081 * Configure the FIFO for simple DMA
1082 ******************************************************************************/
1083static int big_sur_ge_config_fifo(big_sur_ge * emac)
1084{
1085	int err = 0;
1086
1087	err = packet_fifo_init(&emac->recv_fifo, emac->base_address +
1088			       BIG_SUR_GE_PFIFO_RXREG_OFFSET,
1089			       emac->base_address +
1090			       BIG_SUR_GE_PFIFO_RXDATA_OFFSET);
1091
1092	if (err == -1) {
1093		printk(KERN_ERR
1094		       "Could not initialize Rx packet FIFO for Simple DMA \n");
1095		return err;
1096	}
1097
1098	err = packet_fifo_init(&emac->send_fifo, emac->base_address +
1099			       BIG_SUR_GE_PFIFO_TXREG_OFFSET,
1100			       emac->base_address +
1101			       BIG_SUR_GE_PFIFO_TXDATA_OFFSET);
1102
1103	if (err == -1) {
1104		printk(KERN_ERR
1105		       "Could not initialize Tx packet FIFO for Simple DMA \n");
1106	}
1107
1108	return err;
1109}
1110
1111#define BIG_SUR_GE_NUM_INSTANCES	2
1112
1113
1114/**********************************************************************************
1115 * Look up the config of the MAC
1116 **********************************************************************************/
1117static big_sur_ge_config *big_sur_ge_lookup_config(unsigned int device_id)
1118{
1119	big_sur_ge_config *config = NULL;
1120	int i = 0;
1121
1122	for (i = 0; i < BIG_SUR_GE_NUM_INSTANCES; i++) {
1123		/* Manish : Init the config here */
1124		break;
1125	}
1126
1127	return config;
1128}
1129
1130typedef struct {
1131	unsigned long option;
1132	unsigned long mask;
1133} option_map;
1134
1135static option_map option_table[] = {
1136	{BIG_SUR_GE_UNICAST_OPTION, BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK},
1137	{BIG_SUR_GE_BROADCAST_OPTION, BIG_SUR_GE_ECR_BROAD_ENABLE_MASK},
1138	{BIG_SUR_GE_PROMISC_OPTION, BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK},
1139	{BIG_SUR_GE_FDUPLEX_OPTION, BIG_SUR_GE_ECR_FULL_DUPLEX_MASK},
1140	{BIG_SUR_GE_LOOPBACK_OPTION, BIG_SUR_GE_ECR_LOOPBACK_MASK},
1141	{BIG_SUR_GE_MULTICAST_OPTION, BIG_SUR_GE_ECR_MULTI_ENABLE_MASK},
1142	{BIG_SUR_GE_FLOW_CONTROL_OPTION, BIG_SUR_GE_ECR_PAUSE_FRAME_MASK},
1143	{BIG_SUR_GE_INSERT_PAD_OPTION,
1144	 BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK},
1145	{BIG_SUR_GE_INSERT_FCS_OPTION,
1146	 BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK},
1147	{BIG_SUR_GE_INSERT_ADDR_OPTION,
1148	 BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK},
1149	{BIG_SUR_GE_OVWRT_ADDR_OPTION,
1150	 BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK},
1151	{BIG_SUR_GE_STRIP_PAD_OPTION, BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK},
1152	{BIG_SUR_GE_STRIP_FCS_OPTION, BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK},
1153	{BIG_SUR_GE_STRIP_PAD_FCS_OPTION,
1154	 BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK}
1155};
1156
1157#define BIG_SUR_GE_NUM_OPTIONS		(sizeof(option_table) / sizeof(option_map))
1158
1159/**********************************************************************
1160 * Set the options for the GE
1161 **********************************************************************/
1162static int big_sur_ge_set_options(big_sur_ge * emac, unsigned long option_flag)
1163{
1164	unsigned long reg_data;
1165	unsigned int index;
1166
1167	/* Assume that the device is stopped before calling this function */
1168
1169	reg_data =
1170	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
1171	for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) {
1172		if (option_flag & option_table[index].option)
1173			reg_data |= option_table[index].mask;
1174		else
1175			reg_data &= ~(option_table[index].mask);
1176
1177	}
1178
1179	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
1180			 reg_data);
1181
1182	/* No polled option */
1183	emac->polled = 0;
1184
1185	return 0;
1186}
1187
1188/*******************************************************
1189 * Get the options from the GE
1190 *******************************************************/
1191static unsigned long big_sur_ge_get_options(big_sur_ge * emac)
1192{
1193	unsigned long option_flag = 0, reg_data;
1194	unsigned int index;
1195
1196	reg_data =
1197	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
1198
1199	for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) {
1200		if (option_flag & option_table[index].option)
1201			reg_data |= option_table[index].mask;
1202	}
1203
1204	/* No polled mode */
1205
1206	return option_flag;
1207}
1208
1209/********************************************************
1210 * Set the Inter frame gap
1211 ********************************************************/
1212static int big_sur_ge_set_frame_gap(big_sur_ge * emac, int part1, int part2)
1213{
1214	unsigned long config;
1215
1216	/* Assume that the device is stopped before calling this */
1217
1218	config = ((part1 << BIG_SUR_GE_IFGP_PART1_SHIFT) |
1219		  (part2 << BIG_SUR_GE_IFGP_PART2_SHIFT));
1220
1221	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_IFGP_OFFSET,
1222			 config);
1223
1224	return 0;
1225}
1226
1227/********************************************************
1228 * Get the Inter frame gap
1229 ********************************************************/
1230static void big_sur_ge_get_frame_gap(big_sur_ge * emac, int *part1, int *part2)
1231{
1232	unsigned long config;
1233
1234	config =
1235	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_IFGP_OFFSET);
1236	*part1 =
1237	    ((config & BIG_SUR_GE_IFGP_PART1_SHIFT) >>
1238	     BIG_SUR_GE_IFGP_PART1_SHIFT);
1239	*part2 =
1240	    ((config & BIG_SUR_GE_IFGP_PART2_SHIFT) >>
1241	     BIG_SUR_GE_IFGP_PART2_SHIFT);
1242}
1243
1244/*******************************************************************
1245 * PHY specific functions for the MAC
1246 *******************************************************************/
1247#define BIG_SUR_GE_MAX_PHY_ADDR		32
1248#define BIG_SUR_GE_MAX_PHY_REG		32
1249
1250/*******************************************************************
1251 * Read the PHY reg
1252 *******************************************************************/
1253static int big_sur_ge_phy_read(big_sur_ge * emac, unsigned long addr,
1254			unsigned long reg_num, unsigned int *data)
1255{
1256	unsigned long mii_control, mii_data;
1257
1258	if (!emac->has_mii)
1259		return -1;
1260
1261	mii_control =
1262	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET);
1263	if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) {
1264		printk(KERN_ERR "PHY busy \n");
1265		return -1;
1266	}
1267
1268	mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT);
1269	mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT);
1270	mii_control |=
1271	    (BIG_SUR_GE_MGTCR_RW_NOT_MASK | BIG_SUR_GE_MGTCR_START_MASK |
1272	     BIG_SUR_GE_MGTCR_MII_ENABLE_MASK);
1273
1274	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET,
1275			 mii_control);
1276
1277	while (mii_control & BIG_SUR_GE_MGTCR_START_MASK)
1278		if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK))
1279			break;
1280
1281	mii_data =
1282	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET);
1283	*data = (unsigned int) mii_data;
1284
1285	return 0;
1286}
1287
1288/**********************************************************************
1289 * Write to the PHY register
1290 **********************************************************************/
1291static int big_sur_ge_phy_write(big_sur_ge * emac, unsigned long addr,
1292			 unsigned long reg_num, unsigned int data)
1293{
1294	unsigned long mii_control;
1295
1296	if (!emac->has_mii)
1297		return -1;
1298
1299	mii_control =
1300	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET);
1301	if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) {
1302		printk(KERN_ERR "PHY busy \n");
1303		return -1;
1304	}
1305
1306	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET,
1307			 (unsigned long) data);
1308
1309	mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT);
1310	mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT);
1311	mii_control |=
1312	    (BIG_SUR_GE_MGTCR_START_MASK |
1313	     BIG_SUR_GE_MGTCR_MII_ENABLE_MASK);
1314
1315	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET,
1316			 mii_control);
1317
1318	while (mii_control & BIG_SUR_GE_MGTCR_START_MASK)
1319		if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK))
1320			break;
1321
1322	return 0;
1323}
1324
1325
1326
1327
1328
1329
1330/********************************************************************
1331 * The hardware dependent part of the driver begins here
1332 ********************************************************************/
1333
1334
1335/*******************************************************************
1336 * Reset the GE system
1337 *******************************************************************/
1338static void big_sur_ge_reset(struct net_device *netdev, DUPLEX duplex)
1339{
1340	struct big_sur_ge_enet *lp = netdev->priv;
1341	struct sk_buff *skb;
1342	unsigned long options;
1343	int ifcfg1, ifcfg2;
1344
1345	/* Stop the queue */
1346	netif_stop_queue(netdev);
1347
1348	big_sur_ge_get_frame_gap(&lp->emac, &ifcfg1, &ifcfg2);
1349	options = big_sur_ge_get_options(&lp->emac);
1350	switch (duplex) {
1351	case HALF_DUPLEX:
1352		options &= ~(BIG_SUR_GE_FDUPLEX_OPTION);
1353		break;
1354
1355	case FULL_DUPLEX:
1356		options |= BIG_SUR_GE_FDUPLEX_OPTION;
1357		break;
1358
1359	case UNKNOWN:
1360		break;
1361	}
1362
1363	/* There is no support for SG DMA in a 100 Mpbs NIC */
1364
1365	big_sur_ge_enet_reset(&lp->emac);
1366
1367	/* Set the necessary options for the MAC unit */
1368	big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr);
1369	big_sur_ge_set_frame_gap(&lp->emac, ifcfg1, ifcfg2);
1370	big_sur_ge_set_options(&lp->emac, options);
1371
1372	(void) big_sur_ge_start(&lp->emac);
1373
1374	spin_lock_irq(&lp->lock);
1375	skb = lp->saved_skb;
1376	lp->saved_skb = NULL;
1377	spin_unlock_irq(&lp->lock);
1378
1379	if (skb)
1380		dev_kfree_skb(skb);
1381
1382	/* Wake the queue */
1383	netif_wake_queue(netdev);
1384}
1385
1386/********************************************************************
1387 * Get the PHY status
1388 *******************************************************************/
1389static int big_sur_ge_get_phy_status(struct net_device *netdev,
1390				     DUPLEX * duplex, int *linkup)
1391{
1392	struct big_sur_ge_enet *lp = netdev->priv;
1393	unsigned int reg_data;
1394	int err = 0;
1395
1396	err =
1397	    big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_BMCR,
1398				&reg_data);
1399	if (err == -1) {
1400		printk(KERN_ERR "%s: Could not read PHY control register",
1401		       netdev->name);
1402		return err;
1403	}
1404
1405	if (!(reg_data & BMCR_ANENABLE)) {
1406		if (reg_data & BMCR_FULLDPLX)
1407			*duplex = FULL_DUPLEX;
1408		else
1409			*duplex = HALF_DUPLEX;
1410	} else {
1411		unsigned int advertise, partner, neg;
1412
1413		err =
1414		    big_sur_ge_phy_read(&lp->emac, lp->mii_addr,
1415					MII_ADVERTISE, &advertise);
1416		if (err == -1) {
1417			printk(KERN_ERR
1418			       "%s: Could not read PHY control register",
1419			       netdev->name);
1420			return err;
1421		}
1422
1423		err =
1424		    big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_LPA,
1425					&partner);
1426		if (err == -1) {
1427			printk(KERN_ERR
1428			       "%s: Could not read PHY control register",
1429			       netdev->name);
1430			return err;
1431		}
1432
1433		neg = advertise & partner & ADVERTISE_ALL;
1434		if (neg & ADVERTISE_100FULL)
1435			*duplex = FULL_DUPLEX;
1436		else if (neg & ADVERTISE_100HALF)
1437			*duplex = HALF_DUPLEX;
1438		else if (neg & ADVERTISE_10FULL)
1439			*duplex = FULL_DUPLEX;
1440		else
1441			*duplex = HALF_DUPLEX;
1442
1443		err =
1444		    big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_BMSR,
1445					&reg_data);
1446		if (err == -1) {
1447			printk(KERN_ERR
1448			       "%s: Could not read PHY control register",
1449			       netdev->name);
1450			return err;
1451		}
1452
1453		*linkup = (reg_data & BMSR_LSTATUS) != 0;
1454
1455	}
1456	return 0;
1457}
1458
1459/************************************************************
1460 * Poll the MII for duplex and link status
1461 ***********************************************************/
1462static void big_sur_ge_poll_mii(unsigned long data)
1463{
1464	struct net_device *netdev = (struct net_device *) data;
1465	struct big_sur_ge_enet *lp = netdev->priv;
1466	unsigned long options;
1467	DUPLEX mac_duplex, phy_duplex;
1468	int phy_carrier, netif_carrier;
1469
1470	if (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier) ==
1471	    -1) {
1472		printk(KERN_ERR "%s: Terminating link monitoring.\n",
1473		       netdev->name);
1474		return;
1475	}
1476
1477	options = big_sur_ge_get_options(&lp->emac);
1478	if (options & BIG_SUR_GE_FDUPLEX_OPTION)
1479		mac_duplex = FULL_DUPLEX;
1480	else
1481		mac_duplex = HALF_DUPLEX;
1482
1483	if (mac_duplex != phy_duplex) {
1484		disable_irq(netdev->irq);
1485		big_sur_ge_reset(netdev, phy_duplex);
1486		enable_irq(netdev->irq);
1487	}
1488
1489	netif_carrier = netif_carrier_ok(netdev) != 0;
1490
1491	if (phy_carrier != netif_carrier) {
1492		if (phy_carrier) {
1493			printk(KERN_INFO "%s: Link carrier restored.\n",
1494			       netdev->name);
1495			netif_carrier_on(netdev);
1496		} else {
1497			printk(KERN_INFO "%s: Link carrier lost.\n",
1498			       netdev->name);
1499			netif_carrier_off(netdev);
1500		}
1501	}
1502
1503	/* Set up the timer so we'll get called again in 2 seconds. */
1504	lp->phy_timer.expires = jiffies + 2 * HZ;
1505	add_timer(&lp->phy_timer);
1506}
1507
1508/**************************************************************
1509 * Open the network interface
1510 *************************************************************/
1511static int big_sur_ge_open(struct net_device *netdev)
1512{
1513	struct big_sur_ge_enet *lp = netdev->priv;
1514	unsigned long options;
1515	DUPLEX phy_duplex, mac_duplex;
1516	int phy_carrier, retval;
1517
1518	(void) big_sur_ge_stop(&lp->emac);
1519
1520	if (big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr) == -1) {
1521		printk(KERN_ERR "%s: Could not set MAC address.\n",
1522		       netdev->name);
1523		return -EIO;
1524	}
1525
1526	options = big_sur_ge_get_options(&lp->emac);
1527
1528	retval =
1529	    request_irq(netdev->irq, &big_sur_ge_int_handler, 0,
1530			netdev->name, netdev);
1531	if (retval) {
1532		printk(KERN_ERR
1533		       "%s: Could not allocate interrupt %d.\n",
1534		       netdev->name, netdev->irq);
1535
1536		return retval;
1537	}
1538
1539	if (!
1540	    (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier)))
1541	{
1542		if (options & BIG_SUR_GE_FDUPLEX_OPTION)
1543			mac_duplex = FULL_DUPLEX;
1544		else
1545			mac_duplex = HALF_DUPLEX;
1546
1547		if (mac_duplex != phy_duplex) {
1548			switch (phy_duplex) {
1549			case HALF_DUPLEX:
1550				options &= ~(BIG_SUR_GE_FDUPLEX_OPTION);
1551				break;
1552			case FULL_DUPLEX:
1553				options |= BIG_SUR_GE_FDUPLEX_OPTION;
1554				break;
1555			case UNKNOWN:
1556				break;
1557			}
1558
1559			big_sur_ge_set_options(&lp->emac, options);
1560		}
1561	}
1562
1563	if (big_sur_ge_start(&lp->emac) == -1) {
1564		printk(KERN_ERR "%s: Could not start device.\n",
1565		       netdev->name);
1566		free_irq(netdev->irq, netdev);
1567		return -EBUSY;
1568	}
1569
1570	netif_start_queue(netdev);
1571
1572	lp->phy_timer.expires = jiffies + 2 * HZ;
1573	lp->phy_timer.data = (unsigned long) netdev;
1574	lp->phy_timer.function = &big_sur_ge_poll_mii;
1575	add_timer(&lp->phy_timer);
1576
1577	return 0;
1578}
1579
1580/*********************************************************************
1581 * Close the network device interface
1582 *********************************************************************/
1583static int big_sur_ge_close(struct net_device *netdev)
1584{
1585	struct big_sur_ge_enet *lp = netdev->priv;
1586
1587	del_timer_sync(&lp->phy_timer);
1588	netif_stop_queue(netdev);
1589
1590	free_irq(netdev->irq, netdev);
1591
1592	if (big_sur_ge_stop(&lp->emac) == -1) {
1593		printk(KERN_ERR "%s: Could not stop device.\n",
1594		       netdev->name);
1595		return -EBUSY;
1596	}
1597
1598	return 0;
1599}
1600
1601/*********************************************************************
1602 * Get the network device stats. For now, do nothing
1603 *********************************************************************/
1604static struct net_device_stats *big_sur_ge_get_stats(struct net_device
1605						     *netdev)
1606{
1607	/* Do nothing */
1608	return (struct net_device_stats *) 0;
1609}
1610
1611/********************************************************************
1612 * FIFO send for a packet that needs to be transmitted
1613 ********************************************************************/
1614static int big_sur_ge_fifo_send(struct sk_buff *orig_skb,
1615				struct net_device *netdev)
1616{
1617	struct big_sur_ge_enet *lp = netdev->priv;
1618	struct sk_buff *new_skb;
1619	unsigned int len, align;
1620
1621	netif_stop_queue(netdev);
1622	len = orig_skb->len;
1623
1624	if (!(new_skb = dev_alloc_skb(len + 4))) {
1625		dev_kfree_skb(orig_skb);
1626		printk(KERN_ERR
1627		       "%s: Could not allocate transmit buffer.\n",
1628		       netdev->name);
1629		netif_wake_queue(netdev);
1630		return -EBUSY;
1631	}
1632
1633	align = 4 - ((unsigned long) new_skb->data & 3);
1634	if (align != 4)
1635		skb_reserve(new_skb, align);
1636
1637	skb_put(new_skb, len);
1638	memcpy(new_skb->data, orig_skb->data, len);
1639
1640	dev_kfree_skb(orig_skb);
1641
1642	lp->saved_skb = new_skb;
1643	if (big_sur_ge_enet_fifo_send(&lp->emac, (u8 *) new_skb->data, len)
1644	    == -1) {
1645		spin_lock_irq(&lp->lock);
1646		new_skb = lp->saved_skb;
1647		lp->saved_skb = NULL;
1648		spin_unlock_irq(&lp->lock);
1649
1650		dev_kfree_skb(new_skb);
1651		printk(KERN_ERR "%s: Could not transmit buffer.\n",
1652		       netdev->name);
1653		netif_wake_queue(netdev);
1654		return -EIO;
1655	}
1656	return 0;
1657}
1658
1659/**********************************************************************
1660 * Call the fifo send handler
1661 **********************************************************************/
1662static void big_sur_ge_fifo_send_handler(void *callback)
1663{
1664	struct net_device *netdev = (struct net_device *) callback;
1665	struct big_sur_ge_enet *lp = netdev->priv;
1666	struct sk_buff *skb;
1667
1668	spin_lock_irq(&lp->lock);
1669	skb = lp->saved_skb;
1670	lp->saved_skb = NULL;
1671	spin_unlock_irq(&lp->lock);
1672
1673	if (skb)
1674		dev_kfree_skb(skb);
1675
1676	netif_wake_queue(netdev);
1677}
1678
1679/**********************************************************************
1680 * Handle the timeout of the ethernet device
1681 **********************************************************************/
1682static void big_sur_ge_tx_timeout(struct net_device *netdev)
1683{
1684	printk
1685	    ("%s: Exceeded transmit timeout of %lu ms.	Resetting mac.\n",
1686	     netdev->name, TX_TIMEOUT * 1000UL / HZ);
1687
1688	disable_irq(netdev->irq);
1689	big_sur_ge_reset(netdev, UNKNOWN);
1690	enable_irq(netdev->irq);
1691}
1692
1693/*********************************************************************
1694 * When in FIFO mode, the callback function for packets received
1695 *********************************************************************/
1696static void big_sur_ge_fifo_recv_handler(void *callback)
1697{
1698	struct net_device *netdev = (struct net_device *) callback;
1699	struct big_sur_ge_enet *lp = netdev->priv;
1700	struct sk_buff *skb;
1701	unsigned long len = BIG_SUR_GE_MAX_FRAME_SIZE;
1702	unsigned int align;
1703
1704	if (!(skb = dev_alloc_skb(len + 4))) {
1705		printk(KERN_ERR "%s: Could not allocate receive buffer.\n",
1706		       netdev->name);
1707		return;
1708	}
1709
1710	align = 4 - ((unsigned long) skb->data & 3);
1711	if (align != 4)
1712		skb_reserve(skb, align);
1713
1714	if (big_sur_ge_enet_fifo_recv(&lp->emac, (u8 *) skb->data, &len) ==
1715	    -1) {
1716		dev_kfree_skb(skb);
1717
1718		printk(KERN_ERR "%s: Could not receive buffer \n",
1719		       netdev->name);
1720		netdev->tx_timeout = NULL;
1721		big_sur_ge_reset(netdev, UNKNOWN);
1722		netdev->tx_timeout = big_sur_ge_tx_timeout;
1723	}
1724
1725	skb_put(skb, len);	/* Tell the skb how much data we got. */
1726	skb->dev = netdev;	/* Fill out required meta-data. */
1727	skb->protocol = eth_type_trans(skb, netdev);
1728
1729	netif_rx(skb);		/* Send the packet upstream. */
1730}
1731
1732/*********************************************************************
1733 * Set the Multicast Hash list
1734 *********************************************************************/
1735static void big_sur_ge_set_multicast_hash_list(struct net_device *netdev)
1736{
1737	struct big_sur_ge_enet *lp = netdev->priv;
1738	unsigned long options;
1739
1740	disable_irq(netdev->irq);
1741	local_bh_disable();
1742
1743	(void) big_sur_ge_stop(&lp->emac);
1744	options = big_sur_ge_get_options(&lp->emac);
1745	options &=
1746	    ~(BIG_SUR_GE_PROMISC_OPTION | BIG_SUR_GE_MULTICAST_OPTION);
1747
1748	/* Do nothing for now */
1749
1750	(void) big_sur_ge_start(&lp->emac);
1751	local_bh_enable();
1752	enable_irq(netdev->irq);
1753}
1754
1755/***********************************************************************
1756 * IOCTL support
1757 ***********************************************************************/
1758static int big_sur_ge_ioctl(struct net_device *netdev, struct ifreq *rq,
1759			    int cmd)
1760{
1761	struct big_sur_ge_enet *lp = netdev->priv;
1762	struct mii_ioctl_data *data =
1763	    (struct mii_ioctl_data *) &rq->ifr_data;
1764
1765	switch (cmd) {
1766	case SIOCGMIIPHY:	/* Get address of MII PHY in use. */
1767	case SIOCDEVPRIVATE:	/* for binary compat, remove in 2.5 */
1768		data->phy_id = lp->mii_addr;
1769
1770	case SIOCGMIIREG:	/* Read MII PHY register. */
1771	case SIOCDEVPRIVATE + 1:	/* for binary compat, remove in 2.5 */
1772		if (data->phy_id > 31 || data->reg_num > 31)
1773			return -ENXIO;
1774
1775		del_timer_sync(&lp->phy_timer);
1776
1777		if (big_sur_ge_phy_read(&lp->emac, data->phy_id,
1778					data->reg_num,
1779					&data->val_out) == -1) {
1780			printk(KERN_ERR "%s: Could not read from PHY",
1781			       netdev->name);
1782			return -EBUSY;
1783		}
1784
1785		lp->phy_timer.expires = jiffies + 2 * HZ;
1786		add_timer(&lp->phy_timer);
1787
1788		return 0;
1789
1790	case SIOCSMIIREG:	/* Write MII PHY register. */
1791	case SIOCDEVPRIVATE + 2:	/* for binary compat, remove in 2.5 */
1792		if (data->phy_id > 31 || data->reg_num > 31)
1793			return -ENXIO;
1794
1795		del_timer_sync(&lp->phy_timer);
1796
1797		if (big_sur_ge_phy_write
1798		    (&lp->emac, data->phy_id, data->reg_num,
1799		     data->val_in) == -1) {
1800			printk(KERN_ERR "%s: Could not write to PHY",
1801			       netdev->name);
1802			return -EBUSY;
1803		}
1804
1805		lp->phy_timer.expires = jiffies + 2 * HZ;
1806		add_timer(&lp->phy_timer);
1807
1808		return 0;
1809
1810	default:
1811		return -EOPNOTSUPP;
1812	}
1813}
1814
1815/*****************************************************************
1816 * Get the config from the config table
1817 *****************************************************************/
1818static big_sur_ge_config *big_sur_ge_get_config(int index)
1819{
1820	/* Manish */
1821	return (big_sur_ge_config *) 0;
1822}
1823
1824/*****************************************************************
1825 * Release the network device structure
1826 *****************************************************************/
1827static void big_sur_ge_remove_head(void)
1828{
1829	struct net_device *netdev;
1830	struct big_sur_ge_enet *lp;
1831	big_sur_ge_config *config;
1832
1833	spin_lock(&dev_lock);
1834	netdev = dev_list;
1835	lp = netdev->priv;
1836
1837	spin_unlock(&dev_lock);
1838
1839	config = big_sur_ge_get_config(lp->index);
1840	iounmap((void *) config->base_address);
1841	config->base_address = lp->save_base_address;
1842
1843	if (lp->saved_skb)
1844		dev_kfree_skb(lp->saved_skb);
1845	kfree(lp);
1846
1847	unregister_netdev(netdev);
1848	kfree(netdev);
1849}
1850
1851/*****************************************************************
1852 * Initial Function to probe the network interface
1853 *****************************************************************/
1854static int __init big_sur_ge_probe(int index)
1855{
1856	static const unsigned long remap_size =
1857	    BIG_SUR_GE_EMAC_0_HIGHADDR - BIG_SUR_GE_EMAC_0_BASEADDR + 1;
1858	struct net_device *netdev;
1859	struct big_sur_ge_enet *lp;
1860	big_sur_ge_config *config;
1861	unsigned int irq;
1862	unsigned long maddr;
1863	goto err;
1864
1865	switch (index) {
1866	case 0:
1867		irq = (31 - BIG_SUR_GE_INTC_0_EMAC_0_VEC_ID);
1868		break;
1869	case 1:
1870		irq = (31 - BIG_SUR_GE_INTC_1_EMAC_1_VEC_ID);
1871		break;
1872	case 2:
1873		irq = (31 - BIG_SUR_GE_INTC_2_EMAC_2_VEC_ID);
1874		break;
1875	default:
1876		err = -ENODEV;
1877		goto out;
1878	}
1879
1880	config = big_sur_ge_get_config(index);
1881	if (!config) {
1882		err = -ENODEV;
1883		goto out;
1884	}
1885
1886	netdev = alloc_etherdev(sizeof(big_sur_ge_config));
1887
1888	if (!netdev) {
1889		err = -ENOMEM;
1890		goto out;
1891	}
1892
1893	SET_MODULE_OWNER(netdev);
1894
1895	netdev->irq = irq;
1896
1897	lp = (struct big_sur_ge_enet *) netdev->priv;
1898	memset(lp, 0, sizeof(struct big_sur_ge_enet));
1899	spin_lock_init(&lp->lock);
1900	spin_lock(&dev_lock);
1901	lp->next_dev = dev_list;
1902	dev_list = netdev;
1903	spin_unlock(&dev_lock);
1904
1905	lp->save_base_address = config->base_address;
1906	config->base_address =
1907	    (unsigned long) ioremap(lp->save_base_address, remap_size);
1908	if (!config->base_address) {
1909		err = -ENOMEM;
1910		goto out_unlock;
1911	}
1912
1913	if (big_sur_ge_enet_init(&lp->emac, config->device_id) == -1) {
1914		printk(KERN_ERR "%s: Could not initialize device.\n",
1915		       netdev->name);
1916		err = -ENODEV;
1917		goto out_unmap;
1918	}
1919
1920	/* Manish: dev_addr value */
1921	memcpy(netdev->dev_addr, big_sur_mac_addr_base, 6);
1922	if (big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr) == -1) {
1923		printk(KERN_ERR "%s: Could not set MAC address.\n",
1924		       netdev->name);
1925		err = -EIO;
1926		goto out_unmap;
1927	}
1928
1929	/*
1930	 * There is no Scatter Gather support but there is a Simple DMA support
1931	 */
1932	big_sur_ge_set_fifo_recv_handler(&lp->emac, netdev,
1933					 big_sur_ge_fifo_recv_handler);
1934	big_sur_ge_set_fifo_send_handler(&lp->emac, netdev,
1935					 big_sur_ge_fifo_send_handler);
1936	netdev->hard_start_xmit = big_sur_ge_fifo_send;
1937
1938	lp->mii_addr = 0xFF;
1939
1940	for (maddr = 0; maddr < 31; maddr++) {
1941		unsigned int reg_data;
1942
1943		if (big_sur_ge_phy_read
1944		    (&lp->emac, maddr, MII_BMCR, &reg_data) == 0) {
1945			lp->mii_addr = maddr;
1946			break;
1947		}
1948	}
1949
1950	if (lp->mii_addr == 0xFF) {
1951		lp->mii_addr = 0;
1952		printk(KERN_WARNING
1953		       "%s: No PHY detected.  Assuming a PHY at address %d.\n",
1954		       netdev->name, lp->mii_addr);
1955	}
1956
1957	netdev->open = big_sur_ge_open;
1958	netdev->stop = big_sur_ge_close;
1959	netdev->get_stats = big_sur_ge_get_stats;	/* Does nothing */
1960	netdev->do_ioctl = big_sur_ge_ioctl;
1961	netdev->tx_timeout = big_sur_ge_tx_timeout;
1962	netdev->watchdog_timeo = TX_TIMEOUT;
1963
1964	err = register_netdev(netdev))
1965	if (!err)
1966		goto out_unmap;
1967
1968	printk(KERN_INFO "%s: PMC-Sierra Big Sur Ethernet Device %d  at 0x%08X "
1969	       "mapped to 0x%08X, irq=%d\n", netdev->name, index,
1970	       lp->save_base_address, config->base_address, netdev->irq);
1971
1972	return ret;
1973
1974out_unmap:
1975	iounmap(config->base_address);
1976
1977out_unlock:
1978	big_sur_ge_remove_head();
1979
1980out:
1981	return ret;
1982}
1983
1984static int __init big_sur_ge_init(void)
1985{
1986	int index = 0;
1987
1988	while (big_sur_ge_probe(index++) == 0);
1989
1990	return (index > 1) ? 0 : -ENODEV;
1991}
1992
1993static void __exit big_sur_ge_cleanup(void)
1994{
1995	while (dev_list)
1996		big_sur_ge_remove_head();
1997}
1998
1999module_init(big_sur_ge_init);
2000module_exit(big_sur_ge_cleanup);
2001
2002MODULE_AUTHOR("Manish Lachwani <lachwani@pmc-sierra.com>");
2003MODULE_DESCRIPTION("PMC-Sierra Big Sur Ethernet MAC Driver");
2004MODULE_LICENSE("GPL");
2005