1/* 2 * drivers/mtd/nand.c 3 * 4 * Overview: 5 * This is the generic MTD driver for NAND flash devices. It should be 6 * capable of working with almost all NAND chips currently available. 7 * Basic support for AG-AND chips is provided. 8 * 9 * Additional technical information is available on 10 * http://www.linux-mtd.infradead.org/tech/nand.html 11 * 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de) 14 * 15 * Credits: 16 * David Woodhouse for adding multichip support 17 * 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the 19 * rework for 2K page size chips 20 * 21 * TODO: 22 * Enable cached programming for 2k page size chips 23 * Check, if mtd->ecctype should be set to MTD_ECC_HW 24 * if we have HW ecc support. 25 * The AG-AND chips have nice features for speed improvement, 26 * which are not supported yet. Read / program 4 pages in one go. 27 * 28 * This program is free software; you can redistribute it and/or modify 29 * it under the terms of the GNU General Public License version 2 as 30 * published by the Free Software Foundation. 31 * 32 */ 33 34#include <linux/module.h> 35#include <linux/delay.h> 36#include <linux/errno.h> 37#include <linux/err.h> 38#include <linux/sched.h> 39#include <linux/slab.h> 40#include <linux/types.h> 41#include <linux/mtd/mtd.h> 42#include <linux/mtd/nand.h> 43#include <linux/mtd/nand_ecc.h> 44#include <linux/mtd/compatmac.h> 45#include <linux/interrupt.h> 46#include <linux/bitops.h> 47#include <linux/leds.h> 48#include <asm/io.h> 49 50#ifdef CONFIG_MTD_PARTITIONS 51#include <linux/mtd/partitions.h> 52#endif 53 54/* Define default oob placement schemes for large and small page devices */ 55static struct nand_ecclayout nand_oob_8 = { 56 .eccbytes = 3, 57 .eccpos = {0, 1, 2}, 58 .oobfree = { 59 {.offset = 3, 60 .length = 2}, 61 {.offset = 6, 62 .length = 2}} 63}; 64 65static struct nand_ecclayout nand_oob_16 = { 66 .eccbytes = 6, 67 .eccpos = {0, 1, 2, 3, 6, 7}, 68 .oobfree = { 69 {.offset = 8, 70 . length = 8}} 71}; 72 73static struct nand_ecclayout nand_oob_64 = { 74 .eccbytes = 24, 75 .eccpos = { 76 40, 41, 42, 43, 44, 45, 46, 47, 77 48, 49, 50, 51, 52, 53, 54, 55, 78 56, 57, 58, 59, 60, 61, 62, 63}, 79 .oobfree = { 80 {.offset = 2, 81 .length = 38}} 82}; 83 84static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, 85 int new_state); 86 87static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, 88 struct mtd_oob_ops *ops); 89 90/* 91 * For devices which display every fart in the system on a seperate LED. Is 92 * compiled away when LED support is disabled. 93 */ 94DEFINE_LED_TRIGGER(nand_led_trigger); 95 96/** 97 * nand_release_device - [GENERIC] release chip 98 * @mtd: MTD device structure 99 * 100 * Deselect, release chip lock and wake up anyone waiting on the device 101 */ 102static void nand_release_device(struct mtd_info *mtd) 103{ 104 struct nand_chip *chip = mtd->priv; 105 106#ifdef CONFIG_MTD_BRCMNAND 107 if (chip->release_device) { 108 chip->release_device(mtd); 109 return; 110 } 111#endif /* CONFIG_MTD_BRCMNAND */ 112 113 /* De-select the NAND device */ 114 chip->select_chip(mtd, -1); 115 116 /* Release the controller and the chip */ 117 spin_lock(&chip->controller->lock); 118 chip->controller->active = NULL; 119 chip->state = FL_READY; 120 wake_up(&chip->controller->wq); 121 spin_unlock(&chip->controller->lock); 122} 123 124/** 125 * nand_read_byte - [DEFAULT] read one byte from the chip 126 * @mtd: MTD device structure 127 * 128 * Default read function for 8bit buswith 129 */ 130static uint8_t nand_read_byte(struct mtd_info *mtd) 131{ 132 struct nand_chip *chip = mtd->priv; 133 return readb(chip->IO_ADDR_R); 134} 135 136/** 137 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip 138 * @mtd: MTD device structure 139 * 140 * Default read function for 16bit buswith with 141 * endianess conversion 142 */ 143static uint8_t nand_read_byte16(struct mtd_info *mtd) 144{ 145 struct nand_chip *chip = mtd->priv; 146 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); 147} 148 149/** 150 * nand_read_word - [DEFAULT] read one word from the chip 151 * @mtd: MTD device structure 152 * 153 * Default read function for 16bit buswith without 154 * endianess conversion 155 */ 156static u16 nand_read_word(struct mtd_info *mtd) 157{ 158 struct nand_chip *chip = mtd->priv; 159 return readw(chip->IO_ADDR_R); 160} 161 162/** 163 * nand_select_chip - [DEFAULT] control CE line 164 * @mtd: MTD device structure 165 * @chipnr: chipnumber to select, -1 for deselect 166 * 167 * Default select function for 1 chip devices. 168 */ 169static void nand_select_chip(struct mtd_info *mtd, int chipnr) 170{ 171 struct nand_chip *chip = mtd->priv; 172 173 switch (chipnr) { 174 case -1: 175 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); 176 break; 177 case 0: 178 break; 179 180 default: 181 BUG(); 182 } 183} 184 185/** 186 * nand_write_buf - [DEFAULT] write buffer to chip 187 * @mtd: MTD device structure 188 * @buf: data buffer 189 * @len: number of bytes to write 190 * 191 * Default write function for 8bit buswith 192 */ 193static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 194{ 195 int i; 196 struct nand_chip *chip = mtd->priv; 197 198 for (i = 0; i < len; i++) 199 writeb(buf[i], chip->IO_ADDR_W); 200} 201 202/** 203 * nand_read_buf - [DEFAULT] read chip data into buffer 204 * @mtd: MTD device structure 205 * @buf: buffer to store date 206 * @len: number of bytes to read 207 * 208 * Default read function for 8bit buswith 209 */ 210static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 211{ 212 int i; 213 struct nand_chip *chip = mtd->priv; 214 215 for (i = 0; i < len; i++) 216 buf[i] = readb(chip->IO_ADDR_R); 217} 218 219/** 220 * nand_verify_buf - [DEFAULT] Verify chip data against buffer 221 * @mtd: MTD device structure 222 * @buf: buffer containing the data to compare 223 * @len: number of bytes to compare 224 * 225 * Default verify function for 8bit buswith 226 */ 227static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 228{ 229 int i; 230 struct nand_chip *chip = mtd->priv; 231 232 for (i = 0; i < len; i++) 233 if (buf[i] != readb(chip->IO_ADDR_R)) 234 return -EFAULT; 235 return 0; 236} 237 238/** 239 * nand_write_buf16 - [DEFAULT] write buffer to chip 240 * @mtd: MTD device structure 241 * @buf: data buffer 242 * @len: number of bytes to write 243 * 244 * Default write function for 16bit buswith 245 */ 246static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) 247{ 248 int i; 249 struct nand_chip *chip = mtd->priv; 250 u16 *p = (u16 *) buf; 251 len >>= 1; 252 253 for (i = 0; i < len; i++) 254 writew(p[i], chip->IO_ADDR_W); 255 256} 257 258/** 259 * nand_read_buf16 - [DEFAULT] read chip data into buffer 260 * @mtd: MTD device structure 261 * @buf: buffer to store date 262 * @len: number of bytes to read 263 * 264 * Default read function for 16bit buswith 265 */ 266static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) 267{ 268 int i; 269 struct nand_chip *chip = mtd->priv; 270 u16 *p = (u16 *) buf; 271 len >>= 1; 272 273 for (i = 0; i < len; i++) 274 p[i] = readw(chip->IO_ADDR_R); 275} 276 277/** 278 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer 279 * @mtd: MTD device structure 280 * @buf: buffer containing the data to compare 281 * @len: number of bytes to compare 282 * 283 * Default verify function for 16bit buswith 284 */ 285static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) 286{ 287 int i; 288 struct nand_chip *chip = mtd->priv; 289 u16 *p = (u16 *) buf; 290 len >>= 1; 291 292 for (i = 0; i < len; i++) 293 if (p[i] != readw(chip->IO_ADDR_R)) 294 return -EFAULT; 295 296 return 0; 297} 298 299/** 300 * nand_block_bad - [DEFAULT] Read bad block marker from the chip 301 * @mtd: MTD device structure 302 * @ofs: offset from device start 303 * @getchip: 0, if the chip is already selected 304 * 305 * Check, if the block is bad. 306 */ 307static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) 308{ 309 int page, chipnr, res = 0; 310 struct nand_chip *chip = mtd->priv; 311 u16 bad; 312 313 page = (int)(ofs >> chip->page_shift) & chip->pagemask; 314 315 if (getchip) { 316 chipnr = (int)(ofs >> chip->chip_shift); 317 318 nand_get_device(chip, mtd, FL_READING); 319 320 /* Select the NAND device */ 321 chip->select_chip(mtd, chipnr); 322 } 323 324 if (chip->options & NAND_BUSWIDTH_16) { 325 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, 326 page); 327 bad = cpu_to_le16(chip->read_word(mtd)); 328 if (chip->badblockpos & 0x1) 329 bad >>= 8; 330 if ((bad & 0xFF) != 0xff) 331 res = 1; 332 } else { 333 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); 334 if (chip->read_byte(mtd) != 0xff) 335 res = 1; 336 } 337 338 if (getchip) 339 nand_release_device(mtd); 340 341 return res; 342} 343 344/** 345 * nand_default_block_markbad - [DEFAULT] mark a block bad 346 * @mtd: MTD device structure 347 * @ofs: offset from device start 348 * 349 * This is the default implementation, which can be overridden by 350 * a hardware specific driver. 351*/ 352static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) 353{ 354 struct nand_chip *chip = mtd->priv; 355 uint8_t buf[2] = { 0, 0 }; 356 int block, ret; 357 358 /* Get block number */ 359 block = (int)(ofs >> chip->bbt_erase_shift); 360 if (chip->bbt) 361 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); 362 363 /* Do we have a flash based bad block table ? */ 364 if (chip->options & NAND_USE_FLASH_BBT) 365 ret = nand_update_bbt(mtd, ofs); 366 else { 367 /* We write two bytes, so we dont have to mess with 16 bit 368 * access 369 */ 370 /* Patched from Linux 2.6.27.57 */ 371 nand_get_device(chip, mtd, FL_WRITING); 372 373 ofs += mtd->oobsize; 374 chip->ops.len = chip->ops.ooblen = 2; 375 chip->ops.datbuf = NULL; 376 chip->ops.oobbuf = buf; 377 chip->ops.ooboffs = chip->badblockpos & ~0x01; 378 379 ret = nand_do_write_oob(mtd, ofs, &chip->ops); 380 381 /* Patched from Linux 2.6.27.57 */ 382 nand_release_device(mtd); 383 } 384 if (!ret) 385 mtd->ecc_stats.badblocks++; 386 return ret; 387} 388 389/** 390 * nand_check_wp - [GENERIC] check if the chip is write protected 391 * @mtd: MTD device structure 392 * Check, if the device is write protected 393 * 394 * The function expects, that the device is already selected 395 */ 396static int nand_check_wp(struct mtd_info *mtd) 397{ 398 struct nand_chip *chip = mtd->priv; 399 /* Check the WP bit */ 400 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); 401 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; 402} 403 404/** 405 * nand_block_checkbad - [GENERIC] Check if a block is marked bad 406 * @mtd: MTD device structure 407 * @ofs: offset from device start 408 * @getchip: 0, if the chip is already selected 409 * @allowbbt: 1, if its allowed to access the bbt area 410 * 411 * Check, if the block is bad. Either by reading the bad block table or 412 * calling of the scan function. 413 */ 414static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, 415 int allowbbt) 416{ 417 struct nand_chip *chip = mtd->priv; 418 419 if (!chip->bbt) 420 return chip->block_bad(mtd, ofs, getchip); 421 422 /* Return info from the table */ 423 return nand_isbad_bbt(mtd, ofs, allowbbt); 424} 425 426/* 427 * Wait for the ready pin, after a command 428 * The timeout is catched later. 429 */ 430void nand_wait_ready(struct mtd_info *mtd) 431{ 432 struct nand_chip *chip = mtd->priv; 433 unsigned long timeo = jiffies + 2; 434 435 led_trigger_event(nand_led_trigger, LED_FULL); 436 /* wait until command is processed or timeout occures */ 437 do { 438 if (chip->dev_ready(mtd)) 439 break; 440 touch_softlockup_watchdog(); 441 } while (time_before(jiffies, timeo)); 442 led_trigger_event(nand_led_trigger, LED_OFF); 443} 444EXPORT_SYMBOL_GPL(nand_wait_ready); 445 446/** 447 * nand_command - [DEFAULT] Send command to NAND device 448 * @mtd: MTD device structure 449 * @command: the command to be sent 450 * @column: the column address for this command, -1 if none 451 * @page_addr: the page address for this command, -1 if none 452 * 453 * Send command to NAND device. This function is used for small page 454 * devices (256/512 Bytes per page) 455 */ 456static void nand_command(struct mtd_info *mtd, unsigned int command, 457 int column, int page_addr) 458{ 459 register struct nand_chip *chip = mtd->priv; 460 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; 461 462 /* 463 * Write out the command to the device. 464 */ 465 if (command == NAND_CMD_SEQIN) { 466 int readcmd; 467 468 if (column >= mtd->writesize) { 469 /* OOB area */ 470 column -= mtd->writesize; 471 readcmd = NAND_CMD_READOOB; 472 } else if (column < 256) { 473 /* First 256 bytes --> READ0 */ 474 readcmd = NAND_CMD_READ0; 475 } else { 476 column -= 256; 477 readcmd = NAND_CMD_READ1; 478 } 479 chip->cmd_ctrl(mtd, readcmd, ctrl); 480 ctrl &= ~NAND_CTRL_CHANGE; 481 } 482 chip->cmd_ctrl(mtd, command, ctrl); 483 484 /* 485 * Address cycle, when necessary 486 */ 487 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; 488 /* Serially input address */ 489 if (column != -1) { 490 /* Adjust columns for 16 bit buswidth */ 491 if (chip->options & NAND_BUSWIDTH_16) 492 column >>= 1; 493 chip->cmd_ctrl(mtd, column, ctrl); 494 ctrl &= ~NAND_CTRL_CHANGE; 495 } 496 if (page_addr != -1) { 497 chip->cmd_ctrl(mtd, page_addr, ctrl); 498 ctrl &= ~NAND_CTRL_CHANGE; 499 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); 500 /* One more address cycle for devices > 32MiB */ 501 if (chip->chipsize > (32 << 20)) 502 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); 503 } 504 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 505 506 /* 507 * program and erase have their own busy handlers 508 * status and sequential in needs no delay 509 */ 510 switch (command) { 511 512 case NAND_CMD_PAGEPROG: 513 case NAND_CMD_ERASE1: 514 case NAND_CMD_ERASE2: 515 case NAND_CMD_SEQIN: 516 case NAND_CMD_STATUS: 517 return; 518 519 case NAND_CMD_RESET: 520 if (chip->dev_ready) 521 break; 522 udelay(chip->chip_delay); 523 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 524 NAND_CTRL_CLE | NAND_CTRL_CHANGE); 525 chip->cmd_ctrl(mtd, 526 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 527 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; 528 return; 529 530 /* This applies to read commands */ 531 default: 532 /* 533 * If we don't have access to the busy pin, we apply the given 534 * command delay 535 */ 536 if (!chip->dev_ready) { 537 udelay(chip->chip_delay); 538 return; 539 } 540 } 541 /* Apply this short delay always to ensure that we do wait tWB in 542 * any case on any machine. */ 543 ndelay(100); 544 545 nand_wait_ready(mtd); 546} 547 548/** 549 * nand_command_lp - [DEFAULT] Send command to NAND large page device 550 * @mtd: MTD device structure 551 * @command: the command to be sent 552 * @column: the column address for this command, -1 if none 553 * @page_addr: the page address for this command, -1 if none 554 * 555 * Send command to NAND device. This is the version for the new large page 556 * devices We dont have the separate regions as we have in the small page 557 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. 558 */ 559static void nand_command_lp(struct mtd_info *mtd, unsigned int command, 560 int column, int page_addr) 561{ 562 register struct nand_chip *chip = mtd->priv; 563 564 /* Emulate NAND_CMD_READOOB */ 565 if (command == NAND_CMD_READOOB) { 566 column += mtd->writesize; 567 command = NAND_CMD_READ0; 568 } 569 570 /* Command latch cycle */ 571 chip->cmd_ctrl(mtd, command & 0xff, 572 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 573 574 if (column != -1 || page_addr != -1) { 575 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; 576 577 /* Serially input address */ 578 if (column != -1) { 579 /* Adjust columns for 16 bit buswidth */ 580 if (chip->options & NAND_BUSWIDTH_16) 581 column >>= 1; 582 chip->cmd_ctrl(mtd, column, ctrl); 583 ctrl &= ~NAND_CTRL_CHANGE; 584 chip->cmd_ctrl(mtd, column >> 8, ctrl); 585 } 586 if (page_addr != -1) { 587 chip->cmd_ctrl(mtd, page_addr, ctrl); 588 chip->cmd_ctrl(mtd, page_addr >> 8, 589 NAND_NCE | NAND_ALE); 590 /* One more address cycle for devices > 128MiB */ 591 if (chip->chipsize > (128 << 20)) 592 chip->cmd_ctrl(mtd, page_addr >> 16, 593 NAND_NCE | NAND_ALE); 594 } 595 } 596 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 597 598 /* 599 * program and erase have their own busy handlers 600 * status, sequential in, and deplete1 need no delay 601 */ 602 switch (command) { 603 604 case NAND_CMD_CACHEDPROG: 605 case NAND_CMD_PAGEPROG: 606 case NAND_CMD_ERASE1: 607 case NAND_CMD_ERASE2: 608 case NAND_CMD_SEQIN: 609 case NAND_CMD_RNDIN: 610 case NAND_CMD_STATUS: 611 case NAND_CMD_DEPLETE1: 612 return; 613 614 /* 615 * read error status commands require only a short delay 616 */ 617 case NAND_CMD_STATUS_ERROR: 618 case NAND_CMD_STATUS_ERROR0: 619 case NAND_CMD_STATUS_ERROR1: 620 case NAND_CMD_STATUS_ERROR2: 621 case NAND_CMD_STATUS_ERROR3: 622 udelay(chip->chip_delay); 623 return; 624 625 case NAND_CMD_RESET: 626 if (chip->dev_ready) 627 break; 628 udelay(chip->chip_delay); 629 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 630 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 631 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 632 NAND_NCE | NAND_CTRL_CHANGE); 633 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; 634 return; 635 636 case NAND_CMD_RNDOUT: 637 /* No ready / busy check necessary */ 638 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, 639 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 640 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 641 NAND_NCE | NAND_CTRL_CHANGE); 642 return; 643 644 case NAND_CMD_READ0: 645 chip->cmd_ctrl(mtd, NAND_CMD_READSTART, 646 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 647 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 648 NAND_NCE | NAND_CTRL_CHANGE); 649 650 /* This applies to read commands */ 651 default: 652 /* 653 * If we don't have access to the busy pin, we apply the given 654 * command delay 655 */ 656 if (!chip->dev_ready) { 657 udelay(chip->chip_delay); 658 return; 659 } 660 } 661 662 /* Apply this short delay always to ensure that we do wait tWB in 663 * any case on any machine. */ 664 ndelay(100); 665 666 nand_wait_ready(mtd); 667} 668 669/** 670 * nand_get_device - [GENERIC] Get chip for selected access 671 * @chip: the nand chip descriptor 672 * @mtd: MTD device structure 673 * @new_state: the state which is requested 674 * 675 * Get the device and lock it for exclusive access 676 */ 677static int 678nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) 679{ 680 spinlock_t *lock = &chip->controller->lock; 681 wait_queue_head_t *wq = &chip->controller->wq; 682 DECLARE_WAITQUEUE(wait, current); 683 684#ifdef CONFIG_MTD_BRCMNAND 685 if (chip->get_device) { 686 return (chip->get_device(chip, mtd, new_state)); 687 } 688#endif /* CONFIG_MTD_BRCMNAND */ 689 690 retry: 691 spin_lock(lock); 692 693 /* Hardware controller shared among independend devices */ 694 /* Hardware controller shared among independend devices */ 695 if (!chip->controller->active) 696 chip->controller->active = chip; 697 698 if (chip->controller->active == chip && chip->state == FL_READY) { 699 chip->state = new_state; 700 spin_unlock(lock); 701 return 0; 702 } 703 if (new_state == FL_PM_SUSPENDED) { 704 spin_unlock(lock); 705 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; 706 } 707 set_current_state(TASK_UNINTERRUPTIBLE); 708 add_wait_queue(wq, &wait); 709 spin_unlock(lock); 710 schedule(); 711 remove_wait_queue(wq, &wait); 712 goto retry; 713} 714 715/** 716 * nand_wait - [DEFAULT] wait until the command is done 717 * @mtd: MTD device structure 718 * @chip: NAND chip structure 719 * 720 * Wait for command done. This applies to erase and program only 721 * Erase can take up to 400ms and program up to 20ms according to 722 * general NAND and SmartMedia specs 723 */ 724static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) 725{ 726 727 unsigned long timeo = jiffies; 728 int status, state = chip->state; 729 730 if (state == FL_ERASING) 731 timeo += (HZ * 400) / 1000; 732 else 733 timeo += (HZ * 20) / 1000; 734 735 led_trigger_event(nand_led_trigger, LED_FULL); 736 737 /* Apply this short delay always to ensure that we do wait tWB in 738 * any case on any machine. */ 739 ndelay(100); 740 741 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) 742 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); 743 else 744 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); 745 746 while (time_before(jiffies, timeo)) { 747 if (chip->dev_ready) { 748 if (chip->dev_ready(mtd)) 749 break; 750 } else { 751 if (chip->read_byte(mtd) & NAND_STATUS_READY) 752 break; 753 } 754 cond_resched(); 755 } 756 led_trigger_event(nand_led_trigger, LED_OFF); 757 758 status = (int)chip->read_byte(mtd); 759 return status; 760} 761 762/** 763 * nand_read_page_raw - [Intern] read raw page data without ecc 764 * @mtd: mtd info structure 765 * @chip: nand chip info structure 766 * @buf: buffer to store read data 767 */ 768static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 769 uint8_t *buf) 770{ 771 chip->read_buf(mtd, buf, mtd->writesize); 772 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 773 return 0; 774} 775 776/** 777 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function 778 * @mtd: mtd info structure 779 * @chip: nand chip info structure 780 * @buf: buffer to store read data 781 */ 782static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, 783 uint8_t *buf) 784{ 785 int i, eccsize = chip->ecc.size; 786 int eccbytes = chip->ecc.bytes; 787 int eccsteps = chip->ecc.steps; 788 uint8_t *p = buf; 789 uint8_t *ecc_calc = chip->buffers->ecccalc; 790 uint8_t *ecc_code = chip->buffers->ecccode; 791 int *eccpos = chip->ecc.layout->eccpos; 792 793 chip->ecc.read_page_raw(mtd, chip, buf); 794 795 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 796 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 797 798 for (i = 0; i < chip->ecc.total; i++) 799 ecc_code[i] = chip->oob_poi[eccpos[i]]; 800 801 eccsteps = chip->ecc.steps; 802 p = buf; 803 804 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 805 int stat; 806 807 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 808 if (stat == -1) 809 mtd->ecc_stats.failed++; 810 else 811 mtd->ecc_stats.corrected += stat; 812 } 813 return 0; 814} 815 816/** 817 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function 818 * @mtd: mtd info structure 819 * @chip: nand chip info structure 820 * @dataofs offset of requested data within the page 821 * @readlen data length 822 * @buf: buffer to store read data 823 * Note: This function is patched from Linux 2.6.27.57 824 */ 825static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) 826{ 827 int start_step, end_step, num_steps; 828 uint32_t *eccpos = chip->ecc.layout->eccpos; 829 uint8_t *p; 830 int data_col_addr, i, gaps = 0; 831 int datafrag_len, eccfrag_len, aligned_len, aligned_pos; 832 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; 833 834 /* Column address wihin the page aligned to ECC size (256bytes). */ 835 start_step = data_offs / chip->ecc.size; 836 end_step = (data_offs + readlen - 1) / chip->ecc.size; 837 num_steps = end_step - start_step + 1; 838 839 /* Data size aligned to ECC ecc.size*/ 840 datafrag_len = num_steps * chip->ecc.size; 841 eccfrag_len = num_steps * chip->ecc.bytes; 842 843 data_col_addr = start_step * chip->ecc.size; 844 /* If we read not a page aligned data */ 845 if (data_col_addr != 0) 846 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); 847 848 p = bufpoi + data_col_addr; 849 chip->read_buf(mtd, p, datafrag_len); 850 851 /* Calculate ECC */ 852 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) 853 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); 854 855 /* The performance is faster if to position offsets 856 according to ecc.pos. Let make sure here that 857 there are no gaps in ecc positions */ 858 for (i = 0; i < eccfrag_len - 1; i++) { 859 if (eccpos[i + start_step * chip->ecc.bytes] + 1 != 860 eccpos[i + start_step * chip->ecc.bytes + 1]) { 861 gaps = 1; 862 break; 863 } 864 } 865 if (gaps) { 866 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); 867 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 868 } else { 869 /* send the command to read the particular ecc bytes */ 870 /* take care about buswidth alignment in read_buf */ 871 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1); 872 aligned_len = eccfrag_len; 873 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1)) 874 aligned_len++; 875 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1)) 876 aligned_len++; 877 878 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1); 879 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); 880 } 881 882 for (i = 0; i < eccfrag_len; i++) 883 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]]; 884 885 p = bufpoi + data_col_addr; 886 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { 887 int stat; 888 889 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); 890 if (stat == -1) 891 mtd->ecc_stats.failed++; 892 else 893 mtd->ecc_stats.corrected += stat; 894 } 895 return 0; 896} 897 898/** 899 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function 900 * @mtd: mtd info structure 901 * @chip: nand chip info structure 902 * @buf: buffer to store read data 903 * 904 * Not for syndrome calculating ecc controllers which need a special oob layout 905 */ 906static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 907 uint8_t *buf) 908{ 909 int i, eccsize = chip->ecc.size; 910 int eccbytes = chip->ecc.bytes; 911 int eccsteps = chip->ecc.steps; 912 uint8_t *p = buf; 913 uint8_t *ecc_calc = chip->buffers->ecccalc; 914 uint8_t *ecc_code = chip->buffers->ecccode; 915 int *eccpos = chip->ecc.layout->eccpos; 916 917 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 918 chip->ecc.hwctl(mtd, NAND_ECC_READ); 919 chip->read_buf(mtd, p, eccsize); 920 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 921 } 922 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 923 924 for (i = 0; i < chip->ecc.total; i++) 925 ecc_code[i] = chip->oob_poi[eccpos[i]]; 926 927 eccsteps = chip->ecc.steps; 928 p = buf; 929 930 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 931 int stat; 932 933 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 934 if (stat == -1) 935 mtd->ecc_stats.failed++; 936 else 937 mtd->ecc_stats.corrected += stat; 938 } 939 return 0; 940} 941 942/** 943 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read 944 * @mtd: mtd info structure 945 * @chip: nand chip info structure 946 * @buf: buffer to store read data 947 * 948 * The hw generator calculates the error syndrome automatically. Therefor 949 * we need a special oob layout and handling. 950 */ 951static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 952 uint8_t *buf) 953{ 954 int i, eccsize = chip->ecc.size; 955 int eccbytes = chip->ecc.bytes; 956 int eccsteps = chip->ecc.steps; 957 uint8_t *p = buf; 958 uint8_t *oob = chip->oob_poi; 959 960 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 961 int stat; 962 963 chip->ecc.hwctl(mtd, NAND_ECC_READ); 964 chip->read_buf(mtd, p, eccsize); 965 966 if (chip->ecc.prepad) { 967 chip->read_buf(mtd, oob, chip->ecc.prepad); 968 oob += chip->ecc.prepad; 969 } 970 971 chip->ecc.hwctl(mtd, NAND_ECC_READSYN); 972 chip->read_buf(mtd, oob, eccbytes); 973 stat = chip->ecc.correct(mtd, p, oob, NULL); 974 975 if (stat == -1) 976 mtd->ecc_stats.failed++; 977 else 978 mtd->ecc_stats.corrected += stat; 979 980 oob += eccbytes; 981 982 if (chip->ecc.postpad) { 983 chip->read_buf(mtd, oob, chip->ecc.postpad); 984 oob += chip->ecc.postpad; 985 } 986 } 987 988 /* Calculate remaining oob bytes */ 989 i = mtd->oobsize - (oob - chip->oob_poi); 990 if (i) 991 chip->read_buf(mtd, oob, i); 992 993 return 0; 994} 995 996/** 997 * nand_transfer_oob - [Internal] Transfer oob to client buffer 998 * @chip: nand chip structure 999 * @oob: oob destination address 1000 * @ops: oob ops structure 1001 * @len: size of oob to transfer 1002 */ 1003static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, 1004 struct mtd_oob_ops *ops, size_t len) 1005{ 1006 switch(ops->mode) { 1007 1008 case MTD_OOB_PLACE: 1009 case MTD_OOB_RAW: 1010 memcpy(oob, chip->oob_poi + ops->ooboffs, len); 1011 return oob + len; 1012 1013 case MTD_OOB_AUTO: { 1014 struct nand_oobfree *free = chip->ecc.layout->oobfree; 1015 uint32_t boffs = 0, roffs = ops->ooboffs; 1016 size_t bytes = 0; 1017 1018 for(; free->length && len; free++, len -= bytes) { 1019 /* Read request not from offset 0 ? */ 1020 if (unlikely(roffs)) { 1021 if (roffs >= free->length) { 1022 roffs -= free->length; 1023 continue; 1024 } 1025 boffs = free->offset + roffs; 1026 bytes = min_t(size_t, len, 1027 (free->length - roffs)); 1028 roffs = 0; 1029 } else { 1030 bytes = min_t(size_t, len, free->length); 1031 boffs = free->offset; 1032 } 1033 memcpy(oob, chip->oob_poi + boffs, bytes); 1034 oob += bytes; 1035 } 1036 return oob; 1037 } 1038 default: 1039 BUG(); 1040 } 1041 return NULL; 1042} 1043 1044/** 1045 * nand_do_read_ops - [Internal] Read data with ECC 1046 * 1047 * @mtd: MTD device structure 1048 * @from: offset to read from 1049 * @ops: oob ops structure 1050 * 1051 * Internal function. Called with chip held. 1052 */ 1053static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, 1054 struct mtd_oob_ops *ops) 1055{ 1056 int chipnr, page, realpage, col, bytes, aligned; 1057 struct nand_chip *chip = mtd->priv; 1058 struct mtd_ecc_stats stats; 1059 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; 1060 int sndcmd = 1; 1061 int ret = 0; 1062 uint32_t readlen = ops->len; 1063 uint32_t oobreadlen = ops->ooblen; 1064 uint8_t *bufpoi, *oob, *buf; 1065 1066 stats = mtd->ecc_stats; 1067 1068 chipnr = (int)(from >> chip->chip_shift); 1069 chip->select_chip(mtd, chipnr); 1070 1071 realpage = (int)(from >> chip->page_shift); 1072 page = realpage & chip->pagemask; 1073 1074 col = (int)(from & (mtd->writesize - 1)); 1075 1076 buf = ops->datbuf; 1077 oob = ops->oobbuf; 1078 1079 while(1) { 1080 bytes = min(mtd->writesize - col, readlen); 1081 aligned = (bytes == mtd->writesize); 1082 1083 /* Is the current page in the buffer ? */ 1084 if (realpage != chip->pagebuf || oob) { 1085 bufpoi = aligned ? buf : chip->buffers->databuf; 1086 1087 if (likely(sndcmd)) { 1088 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); 1089 sndcmd = 0; 1090 } 1091 1092 /* Now read the page into the buffer */ 1093 if (unlikely(ops->mode == MTD_OOB_RAW)) 1094 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi); 1095 /* Patched from Linux 2.6.27.57 */ 1096 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) 1097 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi); 1098 else 1099 ret = chip->ecc.read_page(mtd, chip, bufpoi); 1100 if (ret < 0) 1101 break; 1102 1103 /* Transfer not aligned data */ 1104 if (!aligned) { 1105 /* Patched from Linux 2.6.27.57 */ 1106 if (!NAND_SUBPAGE_READ(chip) && !oob) 1107 chip->pagebuf = realpage; 1108 memcpy(buf, chip->buffers->databuf + col, bytes); 1109 } 1110 1111 buf += bytes; 1112 1113 if (unlikely(oob)) { 1114 /* Raw mode does data:oob:data:oob */ 1115 if (ops->mode != MTD_OOB_RAW) { 1116 int toread = min(oobreadlen, 1117 chip->ecc.layout->oobavail); 1118 if (toread) { 1119 oob = nand_transfer_oob(chip, 1120 oob, ops, toread); 1121 oobreadlen -= toread; 1122 } 1123 } else 1124 buf = nand_transfer_oob(chip, 1125 buf, ops, mtd->oobsize); 1126 } 1127 1128 if (!(chip->options & NAND_NO_READRDY)) { 1129 /* 1130 * Apply delay or wait for ready/busy pin. Do 1131 * this before the AUTOINCR check, so no 1132 * problems arise if a chip which does auto 1133 * increment is marked as NOAUTOINCR by the 1134 * board driver. 1135 */ 1136 if (!chip->dev_ready) 1137 udelay(chip->chip_delay); 1138 else 1139 nand_wait_ready(mtd); 1140 } 1141 } else { 1142 memcpy(buf, chip->buffers->databuf + col, bytes); 1143 buf += bytes; 1144 } 1145 1146 readlen -= bytes; 1147 1148 if (!readlen) 1149 break; 1150 1151 /* For subsequent reads align to page boundary. */ 1152 col = 0; 1153 /* Increment page address */ 1154 realpage++; 1155 1156 page = realpage & chip->pagemask; 1157 /* Check, if we cross a chip boundary */ 1158 if (!page) { 1159 chipnr++; 1160 chip->select_chip(mtd, -1); 1161 chip->select_chip(mtd, chipnr); 1162 } 1163 1164 /* Check, if the chip supports auto page increment 1165 * or if we have hit a block boundary. 1166 */ 1167 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) 1168 sndcmd = 1; 1169 } 1170 1171 ops->retlen = ops->len - (size_t) readlen; 1172 if (oob) 1173 ops->oobretlen = ops->ooblen - oobreadlen; 1174 1175 if (ret) 1176 return ret; 1177 1178 if (mtd->ecc_stats.failed - stats.failed) 1179 return -EBADMSG; 1180 1181 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; 1182} 1183 1184/** 1185 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc 1186 * @mtd: MTD device structure 1187 * @from: offset to read from 1188 * @len: number of bytes to read 1189 * @retlen: pointer to variable to store the number of read bytes 1190 * @buf: the databuffer to put data 1191 * 1192 * Get hold of the chip and call nand_do_read 1193 */ 1194static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, 1195 size_t *retlen, uint8_t *buf) 1196{ 1197 struct nand_chip *chip = mtd->priv; 1198 int ret; 1199 1200 /* Do not allow reads past end of device */ 1201 if ((from + len) > mtd->size) 1202 return -EINVAL; 1203 if (!len) 1204 return 0; 1205 1206 nand_get_device(chip, mtd, FL_READING); 1207 1208 chip->ops.len = len; 1209 chip->ops.datbuf = buf; 1210 chip->ops.oobbuf = NULL; 1211 1212 ret = nand_do_read_ops(mtd, from, &chip->ops); 1213 1214 *retlen = chip->ops.retlen; 1215 1216 nand_release_device(mtd); 1217 1218 return ret; 1219} 1220 1221/** 1222 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function 1223 * @mtd: mtd info structure 1224 * @chip: nand chip info structure 1225 * @page: page number to read 1226 * @sndcmd: flag whether to issue read command or not 1227 */ 1228static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, 1229 int page, int sndcmd) 1230{ 1231 if (sndcmd) { 1232 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 1233 sndcmd = 0; 1234 } 1235 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1236 return sndcmd; 1237} 1238 1239/** 1240 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC 1241 * with syndromes 1242 * @mtd: mtd info structure 1243 * @chip: nand chip info structure 1244 * @page: page number to read 1245 * @sndcmd: flag whether to issue read command or not 1246 */ 1247static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1248 int page, int sndcmd) 1249{ 1250 uint8_t *buf = chip->oob_poi; 1251 int length = mtd->oobsize; 1252 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 1253 int eccsize = chip->ecc.size; 1254 uint8_t *bufpoi = buf; 1255 int i, toread, sndrnd = 0, pos; 1256 1257 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); 1258 for (i = 0; i < chip->ecc.steps; i++) { 1259 if (sndrnd) { 1260 pos = eccsize + i * (eccsize + chunk); 1261 if (mtd->writesize > 512) 1262 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); 1263 else 1264 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); 1265 } else 1266 sndrnd = 1; 1267 toread = min_t(int, length, chunk); 1268 chip->read_buf(mtd, bufpoi, toread); 1269 bufpoi += toread; 1270 length -= toread; 1271 } 1272 if (length > 0) 1273 chip->read_buf(mtd, bufpoi, length); 1274 1275 return 1; 1276} 1277 1278/** 1279 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function 1280 * @mtd: mtd info structure 1281 * @chip: nand chip info structure 1282 * @page: page number to write 1283 */ 1284static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, 1285 int page) 1286{ 1287 int status = 0; 1288 const uint8_t *buf = chip->oob_poi; 1289 int length = mtd->oobsize; 1290 1291 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 1292 chip->write_buf(mtd, buf, length); 1293 /* Send command to program the OOB data */ 1294 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 1295 1296 status = chip->waitfunc(mtd, chip); 1297 1298 return status & NAND_STATUS_FAIL ? -EIO : 0; 1299} 1300 1301/** 1302 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC 1303 * with syndrome - only for large page flash ! 1304 * @mtd: mtd info structure 1305 * @chip: nand chip info structure 1306 * @page: page number to write 1307 */ 1308static int nand_write_oob_syndrome(struct mtd_info *mtd, 1309 struct nand_chip *chip, int page) 1310{ 1311 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 1312 int eccsize = chip->ecc.size, length = mtd->oobsize; 1313 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; 1314 const uint8_t *bufpoi = chip->oob_poi; 1315 1316 /* 1317 * data-ecc-data-ecc ... ecc-oob 1318 * or 1319 * data-pad-ecc-pad-data-pad .... ecc-pad-oob 1320 */ 1321 if (!chip->ecc.prepad && !chip->ecc.postpad) { 1322 pos = steps * (eccsize + chunk); 1323 steps = 0; 1324 } else 1325 pos = eccsize; 1326 1327 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); 1328 for (i = 0; i < steps; i++) { 1329 if (sndcmd) { 1330 if (mtd->writesize <= 512) { 1331 uint32_t fill = 0xFFFFFFFF; 1332 1333 len = eccsize; 1334 while (len > 0) { 1335 int num = min_t(int, len, 4); 1336 chip->write_buf(mtd, (uint8_t *)&fill, 1337 num); 1338 len -= num; 1339 } 1340 } else { 1341 pos = eccsize + i * (eccsize + chunk); 1342 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); 1343 } 1344 } else 1345 sndcmd = 1; 1346 len = min_t(int, length, chunk); 1347 chip->write_buf(mtd, bufpoi, len); 1348 bufpoi += len; 1349 length -= len; 1350 } 1351 if (length > 0) 1352 chip->write_buf(mtd, bufpoi, length); 1353 1354 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 1355 status = chip->waitfunc(mtd, chip); 1356 1357 return status & NAND_STATUS_FAIL ? -EIO : 0; 1358} 1359 1360/** 1361 * nand_do_read_oob - [Intern] NAND read out-of-band 1362 * @mtd: MTD device structure 1363 * @from: offset to read from 1364 * @ops: oob operations description structure 1365 * 1366 * NAND read out-of-band data from the spare area 1367 */ 1368static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, 1369 struct mtd_oob_ops *ops) 1370{ 1371 int page, realpage, chipnr, sndcmd = 1; 1372 struct nand_chip *chip = mtd->priv; 1373 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; 1374 int readlen = ops->ooblen; 1375 int len; 1376 uint8_t *buf = ops->oobbuf; 1377 1378 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n", 1379 (unsigned long long)from, readlen); 1380 1381 if (ops->mode == MTD_OOB_AUTO) 1382 len = chip->ecc.layout->oobavail; 1383 else 1384 len = mtd->oobsize; 1385 1386 if (unlikely(ops->ooboffs >= len)) { 1387 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " 1388 "Attempt to start read outside oob\n"); 1389 return -EINVAL; 1390 } 1391 1392 /* Do not allow reads past end of device */ 1393 if (unlikely(from >= mtd->size || 1394 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - 1395 (from >> chip->page_shift)) * len)) { 1396 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " 1397 "Attempt read beyond end of device\n"); 1398 return -EINVAL; 1399 } 1400 1401 chipnr = (int)(from >> chip->chip_shift); 1402 chip->select_chip(mtd, chipnr); 1403 1404 /* Shift to get page */ 1405 realpage = (int)(from >> chip->page_shift); 1406 page = realpage & chip->pagemask; 1407 1408 while(1) { 1409 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd); 1410 1411 len = min(len, readlen); 1412 buf = nand_transfer_oob(chip, buf, ops, len); 1413 1414 if (!(chip->options & NAND_NO_READRDY)) { 1415 /* 1416 * Apply delay or wait for ready/busy pin. Do this 1417 * before the AUTOINCR check, so no problems arise if a 1418 * chip which does auto increment is marked as 1419 * NOAUTOINCR by the board driver. 1420 */ 1421 if (!chip->dev_ready) 1422 udelay(chip->chip_delay); 1423 else 1424 nand_wait_ready(mtd); 1425 } 1426 1427 readlen -= len; 1428 if (!readlen) 1429 break; 1430 1431 /* Increment page address */ 1432 realpage++; 1433 1434 page = realpage & chip->pagemask; 1435 /* Check, if we cross a chip boundary */ 1436 if (!page) { 1437 chipnr++; 1438 chip->select_chip(mtd, -1); 1439 chip->select_chip(mtd, chipnr); 1440 } 1441 1442 /* Check, if the chip supports auto page increment 1443 * or if we have hit a block boundary. 1444 */ 1445 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) 1446 sndcmd = 1; 1447 } 1448 1449 ops->oobretlen = ops->ooblen; 1450 return 0; 1451} 1452 1453/** 1454 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band 1455 * @mtd: MTD device structure 1456 * @from: offset to read from 1457 * @ops: oob operation description structure 1458 * 1459 * NAND read data and/or out-of-band data 1460 */ 1461static int nand_read_oob(struct mtd_info *mtd, loff_t from, 1462 struct mtd_oob_ops *ops) 1463{ 1464 struct nand_chip *chip = mtd->priv; 1465 int ret = -ENOTSUPP; 1466 1467 ops->retlen = 0; 1468 1469 /* Do not allow reads past end of device */ 1470 if (ops->datbuf && (from + ops->len) > mtd->size) { 1471 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " 1472 "Attempt read beyond end of device\n"); 1473 return -EINVAL; 1474 } 1475 1476 nand_get_device(chip, mtd, FL_READING); 1477 1478 switch(ops->mode) { 1479 case MTD_OOB_PLACE: 1480 case MTD_OOB_AUTO: 1481 case MTD_OOB_RAW: 1482 break; 1483 1484 default: 1485 goto out; 1486 } 1487 1488 if (!ops->datbuf) 1489 ret = nand_do_read_oob(mtd, from, ops); 1490 else 1491 ret = nand_do_read_ops(mtd, from, ops); 1492 1493 out: 1494 nand_release_device(mtd); 1495 return ret; 1496} 1497 1498 1499/** 1500 * nand_write_page_raw - [Intern] raw page write function 1501 * @mtd: mtd info structure 1502 * @chip: nand chip info structure 1503 * @buf: data buffer 1504 */ 1505static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1506 const uint8_t *buf) 1507{ 1508 chip->write_buf(mtd, buf, mtd->writesize); 1509 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 1510} 1511 1512/** 1513 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function 1514 * @mtd: mtd info structure 1515 * @chip: nand chip info structure 1516 * @buf: data buffer 1517 */ 1518static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, 1519 const uint8_t *buf) 1520{ 1521 int i, eccsize = chip->ecc.size; 1522 int eccbytes = chip->ecc.bytes; 1523 int eccsteps = chip->ecc.steps; 1524 uint8_t *ecc_calc = chip->buffers->ecccalc; 1525 const uint8_t *p = buf; 1526 int *eccpos = chip->ecc.layout->eccpos; 1527 1528 /* Software ecc calculation */ 1529 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 1530 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1531 1532 for (i = 0; i < chip->ecc.total; i++) 1533 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 1534 1535 chip->ecc.write_page_raw(mtd, chip, buf); 1536} 1537 1538/** 1539 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function 1540 * @mtd: mtd info structure 1541 * @chip: nand chip info structure 1542 * @buf: data buffer 1543 */ 1544static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 1545 const uint8_t *buf) 1546{ 1547 int i, eccsize = chip->ecc.size; 1548 int eccbytes = chip->ecc.bytes; 1549 int eccsteps = chip->ecc.steps; 1550 uint8_t *ecc_calc = chip->buffers->ecccalc; 1551 const uint8_t *p = buf; 1552 int *eccpos = chip->ecc.layout->eccpos; 1553 1554 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1555 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 1556 chip->write_buf(mtd, p, eccsize); 1557 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1558 } 1559 1560 for (i = 0; i < chip->ecc.total; i++) 1561 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 1562 1563 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 1564} 1565 1566/** 1567 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write 1568 * @mtd: mtd info structure 1569 * @chip: nand chip info structure 1570 * @buf: data buffer 1571 * 1572 * The hw generator calculates the error syndrome automatically. Therefor 1573 * we need a special oob layout and handling. 1574 */ 1575static void nand_write_page_syndrome(struct mtd_info *mtd, 1576 struct nand_chip *chip, const uint8_t *buf) 1577{ 1578 int i, eccsize = chip->ecc.size; 1579 int eccbytes = chip->ecc.bytes; 1580 int eccsteps = chip->ecc.steps; 1581 const uint8_t *p = buf; 1582 uint8_t *oob = chip->oob_poi; 1583 1584 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1585 1586 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 1587 chip->write_buf(mtd, p, eccsize); 1588 1589 if (chip->ecc.prepad) { 1590 chip->write_buf(mtd, oob, chip->ecc.prepad); 1591 oob += chip->ecc.prepad; 1592 } 1593 1594 chip->ecc.calculate(mtd, p, oob); 1595 chip->write_buf(mtd, oob, eccbytes); 1596 oob += eccbytes; 1597 1598 if (chip->ecc.postpad) { 1599 chip->write_buf(mtd, oob, chip->ecc.postpad); 1600 oob += chip->ecc.postpad; 1601 } 1602 } 1603 1604 /* Calculate remaining oob bytes */ 1605 i = mtd->oobsize - (oob - chip->oob_poi); 1606 if (i) 1607 chip->write_buf(mtd, oob, i); 1608} 1609 1610/** 1611 * nand_write_page - [REPLACEABLE] write one page 1612 * @mtd: MTD device structure 1613 * @chip: NAND chip descriptor 1614 * @buf: the data to write 1615 * @page: page number to write 1616 * @cached: cached programming 1617 * @raw: use _raw version of write_page 1618 */ 1619static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, 1620 const uint8_t *buf, int page, int cached, int raw) 1621{ 1622 int status; 1623 1624 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); 1625 1626 if (unlikely(raw)) 1627 chip->ecc.write_page_raw(mtd, chip, buf); 1628 else 1629 chip->ecc.write_page(mtd, chip, buf); 1630 1631 /* 1632 * Cached progamming disabled for now, Not sure if its worth the 1633 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) 1634 */ 1635 cached = 0; 1636 1637 if (!cached || !(chip->options & NAND_CACHEPRG)) { 1638 1639 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 1640 status = chip->waitfunc(mtd, chip); 1641 /* 1642 * See if operation failed and additional status checks are 1643 * available 1644 */ 1645 if ((status & NAND_STATUS_FAIL) && (chip->errstat)) 1646 status = chip->errstat(mtd, chip, FL_WRITING, status, 1647 page); 1648 1649 if (status & NAND_STATUS_FAIL) 1650 return -EIO; 1651 } else { 1652 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); 1653 status = chip->waitfunc(mtd, chip); 1654 } 1655 1656#ifdef CONFIG_MTD_NAND_VERIFY_WRITE 1657 /* Send command to read back the data */ 1658 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); 1659 1660 if (chip->verify_buf(mtd, buf, mtd->writesize)) 1661 return -EIO; 1662#endif 1663 return 0; 1664} 1665 1666/** 1667 * nand_fill_oob - [Internal] Transfer client buffer to oob 1668 * @chip: nand chip structure 1669 * @oob: oob data buffer 1670 * @ops: oob ops structure 1671 */ 1672static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, 1673 struct mtd_oob_ops *ops) 1674{ 1675 size_t len = ops->ooblen; 1676 1677 switch(ops->mode) { 1678 1679 case MTD_OOB_PLACE: 1680 case MTD_OOB_RAW: 1681 memcpy(chip->oob_poi + ops->ooboffs, oob, len); 1682 return oob + len; 1683 1684 case MTD_OOB_AUTO: { 1685 struct nand_oobfree *free = chip->ecc.layout->oobfree; 1686 uint32_t boffs = 0, woffs = ops->ooboffs; 1687 size_t bytes = 0; 1688 1689 for(; free->length && len; free++, len -= bytes) { 1690 /* Write request not from offset 0 ? */ 1691 if (unlikely(woffs)) { 1692 if (woffs >= free->length) { 1693 woffs -= free->length; 1694 continue; 1695 } 1696 boffs = free->offset + woffs; 1697 bytes = min_t(size_t, len, 1698 (free->length - woffs)); 1699 woffs = 0; 1700 } else { 1701 bytes = min_t(size_t, len, free->length); 1702 boffs = free->offset; 1703 } 1704 memcpy(chip->oob_poi + boffs, oob, bytes); 1705 oob += bytes; 1706 } 1707 return oob; 1708 } 1709 default: 1710 BUG(); 1711 } 1712 return NULL; 1713} 1714 1715#define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0 1716 1717/** 1718 * nand_do_write_ops - [Internal] NAND write with ECC 1719 * @mtd: MTD device structure 1720 * @to: offset to write to 1721 * @ops: oob operations description structure 1722 * 1723 * NAND write with ECC 1724 */ 1725static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, 1726 struct mtd_oob_ops *ops) 1727{ 1728 int chipnr, realpage, page, blockmask, column; 1729 struct nand_chip *chip = mtd->priv; 1730 uint32_t writelen = ops->len; 1731 uint8_t *oob = ops->oobbuf; 1732 uint8_t *buf = ops->datbuf; 1733 int ret, subpage; 1734 1735 ops->retlen = 0; 1736 if (!writelen) 1737 return 0; 1738 1739 /* reject writes, which are not page aligned */ 1740 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { 1741 printk(KERN_NOTICE "nand_write: " 1742 "Attempt to write not page aligned data\n"); 1743 return -EINVAL; 1744 } 1745 1746 column = to & (mtd->writesize - 1); 1747 subpage = column || (writelen & (mtd->writesize - 1)); 1748 1749 if (subpage && oob) 1750 return -EINVAL; 1751 1752 chipnr = (int)(to >> chip->chip_shift); 1753 chip->select_chip(mtd, chipnr); 1754 1755 /* Check, if it is write protected */ 1756 if (nand_check_wp(mtd)) 1757 return -EIO; 1758 1759 realpage = (int)(to >> chip->page_shift); 1760 page = realpage & chip->pagemask; 1761 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; 1762 1763 /* Invalidate the page cache, when we write to the cached page */ 1764 if (to <= (chip->pagebuf << chip->page_shift) && 1765 (chip->pagebuf << chip->page_shift) < (to + ops->len)) 1766 chip->pagebuf = -1; 1767 1768 /* If we're not given explicit OOB data, let it be 0xFF */ 1769 if (likely(!oob)) 1770 memset(chip->oob_poi, 0xff, mtd->oobsize); 1771 1772 while(1) { 1773 int bytes = mtd->writesize; 1774 int cached = writelen > bytes && page != blockmask; 1775 uint8_t *wbuf = buf; 1776 1777 /* Partial page write ? */ 1778 if (unlikely(column || writelen < (mtd->writesize - 1))) { 1779 cached = 0; 1780 bytes = min_t(int, bytes - column, (int) writelen); 1781 chip->pagebuf = -1; 1782 memset(chip->buffers->databuf, 0xff, mtd->writesize); 1783 memcpy(&chip->buffers->databuf[column], buf, bytes); 1784 wbuf = chip->buffers->databuf; 1785 } 1786 1787 if (unlikely(oob)) 1788 oob = nand_fill_oob(chip, oob, ops); 1789 1790 ret = chip->write_page(mtd, chip, wbuf, page, cached, 1791 (ops->mode == MTD_OOB_RAW)); 1792 if (ret) 1793 break; 1794 1795 writelen -= bytes; 1796 if (!writelen) 1797 break; 1798 1799 column = 0; 1800 buf += bytes; 1801 realpage++; 1802 1803 page = realpage & chip->pagemask; 1804 /* Check, if we cross a chip boundary */ 1805 if (!page) { 1806 chipnr++; 1807 chip->select_chip(mtd, -1); 1808 chip->select_chip(mtd, chipnr); 1809 } 1810 } 1811 1812 ops->retlen = ops->len - writelen; 1813 if (unlikely(oob)) 1814 ops->oobretlen = ops->ooblen; 1815 return ret; 1816} 1817 1818/** 1819 * nand_write - [MTD Interface] NAND write with ECC 1820 * @mtd: MTD device structure 1821 * @to: offset to write to 1822 * @len: number of bytes to write 1823 * @retlen: pointer to variable to store the number of written bytes 1824 * @buf: the data to write 1825 * 1826 * NAND write with ECC 1827 */ 1828static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, 1829 size_t *retlen, const uint8_t *buf) 1830{ 1831 struct nand_chip *chip = mtd->priv; 1832 int ret; 1833 1834 /* Do not allow reads past end of device */ 1835 if ((to + len) > mtd->size) 1836 return -EINVAL; 1837 if (!len) 1838 return 0; 1839 1840 nand_get_device(chip, mtd, FL_WRITING); 1841 1842 chip->ops.len = len; 1843 chip->ops.datbuf = (uint8_t *)buf; 1844 chip->ops.oobbuf = NULL; 1845 1846 ret = nand_do_write_ops(mtd, to, &chip->ops); 1847 1848 *retlen = chip->ops.retlen; 1849 1850 nand_release_device(mtd); 1851 1852 return ret; 1853} 1854 1855/** 1856 * nand_do_write_oob - [MTD Interface] NAND write out-of-band 1857 * @mtd: MTD device structure 1858 * @to: offset to write to 1859 * @ops: oob operation description structure 1860 * 1861 * NAND write out-of-band 1862 */ 1863static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, 1864 struct mtd_oob_ops *ops) 1865{ 1866 int chipnr, page, status, len; 1867 struct nand_chip *chip = mtd->priv; 1868 1869 DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", 1870 (unsigned int)to, (int)ops->ooblen); 1871 1872 if (ops->mode == MTD_OOB_AUTO) 1873 len = chip->ecc.layout->oobavail; 1874 else 1875 len = mtd->oobsize; 1876 1877 /* Do not allow write past end of page */ 1878 if ((ops->ooboffs + ops->ooblen) > len) { 1879 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " 1880 "Attempt to write past end of page\n"); 1881 return -EINVAL; 1882 } 1883 1884 if (unlikely(ops->ooboffs >= len)) { 1885 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " 1886 "Attempt to start write outside oob\n"); 1887 return -EINVAL; 1888 } 1889 1890 /* Do not allow reads past end of device */ 1891 if (unlikely(to >= mtd->size || 1892 ops->ooboffs + ops->ooblen > 1893 ((mtd->size >> chip->page_shift) - 1894 (to >> chip->page_shift)) * len)) { 1895 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " 1896 "Attempt write beyond end of device\n"); 1897 return -EINVAL; 1898 } 1899 1900 chipnr = (int)(to >> chip->chip_shift); 1901 chip->select_chip(mtd, chipnr); 1902 1903 /* Shift to get page */ 1904 page = (int)(to >> chip->page_shift); 1905 1906 /* 1907 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one 1908 * of my DiskOnChip 2000 test units) will clear the whole data page too 1909 * if we don't do this. I have no clue why, but I seem to have 'fixed' 1910 * it in the doc2000 driver in August 1999. dwmw2. 1911 */ 1912 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 1913 1914 /* Check, if it is write protected */ 1915 if (nand_check_wp(mtd)) 1916 return -EROFS; 1917 1918 /* Invalidate the page cache, if we write to the cached page */ 1919 if (page == chip->pagebuf) 1920 chip->pagebuf = -1; 1921 1922 memset(chip->oob_poi, 0xff, mtd->oobsize); 1923 nand_fill_oob(chip, ops->oobbuf, ops); 1924 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); 1925 memset(chip->oob_poi, 0xff, mtd->oobsize); 1926 1927 if (status) 1928 return status; 1929 1930 ops->oobretlen = ops->ooblen; 1931 1932 return 0; 1933} 1934 1935/** 1936 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band 1937 * @mtd: MTD device structure 1938 * @to: offset to write to 1939 * @ops: oob operation description structure 1940 */ 1941static int nand_write_oob(struct mtd_info *mtd, loff_t to, 1942 struct mtd_oob_ops *ops) 1943{ 1944 struct nand_chip *chip = mtd->priv; 1945 int ret = -ENOTSUPP; 1946 1947 ops->retlen = 0; 1948 1949 /* Do not allow writes past end of device */ 1950 if (ops->datbuf && (to + ops->len) > mtd->size) { 1951 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " 1952 "Attempt read beyond end of device\n"); 1953 return -EINVAL; 1954 } 1955 1956 nand_get_device(chip, mtd, FL_WRITING); 1957 1958 switch(ops->mode) { 1959 case MTD_OOB_PLACE: 1960 case MTD_OOB_AUTO: 1961 case MTD_OOB_RAW: 1962 break; 1963 1964 default: 1965 goto out; 1966 } 1967 1968 if (!ops->datbuf) 1969 ret = nand_do_write_oob(mtd, to, ops); 1970 else 1971 ret = nand_do_write_ops(mtd, to, ops); 1972 1973 out: 1974 nand_release_device(mtd); 1975 return ret; 1976} 1977 1978/** 1979 * single_erease_cmd - [GENERIC] NAND standard block erase command function 1980 * @mtd: MTD device structure 1981 * @page: the page address of the block which will be erased 1982 * 1983 * Standard erase command for NAND chips 1984 */ 1985static void single_erase_cmd(struct mtd_info *mtd, int page) 1986{ 1987 struct nand_chip *chip = mtd->priv; 1988 /* Send commands to erase a block */ 1989 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); 1990 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); 1991} 1992 1993/** 1994 * multi_erease_cmd - [GENERIC] AND specific block erase command function 1995 * @mtd: MTD device structure 1996 * @page: the page address of the block which will be erased 1997 * 1998 * AND multi block erase command function 1999 * Erase 4 consecutive blocks 2000 */ 2001static void multi_erase_cmd(struct mtd_info *mtd, int page) 2002{ 2003 struct nand_chip *chip = mtd->priv; 2004 /* Send commands to erase a block */ 2005 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); 2006 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); 2007 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); 2008 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); 2009 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); 2010} 2011 2012/** 2013 * nand_erase - [MTD Interface] erase block(s) 2014 * @mtd: MTD device structure 2015 * @instr: erase instruction 2016 * 2017 * Erase one ore more blocks 2018 */ 2019static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) 2020{ 2021 return nand_erase_nand(mtd, instr, 0); 2022} 2023 2024#define BBT_PAGE_MASK 0xffffff3f 2025/** 2026 * nand_erase_nand - [Internal] erase block(s) 2027 * @mtd: MTD device structure 2028 * @instr: erase instruction 2029 * @allowbbt: allow erasing the bbt area 2030 * 2031 * Erase one ore more blocks 2032 */ 2033int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 2034 int allowbbt) 2035{ 2036 int page, len, status, pages_per_block, ret, chipnr; 2037 struct nand_chip *chip = mtd->priv; 2038 int rewrite_bbt[NAND_MAX_CHIPS]={0}; 2039 unsigned int bbt_masked_page = 0xffffffff; 2040 2041 DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", 2042 (unsigned int)instr->addr, (unsigned int)instr->len); 2043 2044 /* Start address must align on block boundary */ 2045 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) { 2046 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); 2047 return -EINVAL; 2048 } 2049 2050 /* Length must align on block boundary */ 2051 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) { 2052 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " 2053 "Length not block aligned\n"); 2054 return -EINVAL; 2055 } 2056 2057 /* Do not allow erase past end of device */ 2058 if ((instr->len + instr->addr) > mtd->size) { 2059 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " 2060 "Erase past end of device\n"); 2061 return -EINVAL; 2062 } 2063 2064 instr->fail_addr = 0xffffffff; 2065 2066 /* Grab the lock and see if the device is available */ 2067 nand_get_device(chip, mtd, FL_ERASING); 2068 2069 /* Shift to get first page */ 2070 page = (int)(instr->addr >> chip->page_shift); 2071 chipnr = (int)(instr->addr >> chip->chip_shift); 2072 2073 /* Calculate pages in each block */ 2074 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); 2075 2076 /* Select the NAND device */ 2077 chip->select_chip(mtd, chipnr); 2078 2079 /* Check, if it is write protected */ 2080 if (nand_check_wp(mtd)) { 2081 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " 2082 "Device is write protected!!!\n"); 2083 instr->state = MTD_ERASE_FAILED; 2084 goto erase_exit; 2085 } 2086 2087 /* 2088 * If BBT requires refresh, set the BBT page mask to see if the BBT 2089 * should be rewritten. Otherwise the mask is set to 0xffffffff which 2090 * can not be matched. This is also done when the bbt is actually 2091 * erased to avoid recusrsive updates 2092 */ 2093 if (chip->options & BBT_AUTO_REFRESH && !allowbbt) 2094 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; 2095 2096 /* Loop through the pages */ 2097 len = instr->len; 2098 2099 instr->state = MTD_ERASING; 2100 2101 while (len) { 2102 /* 2103 * heck if we have a bad block, we do not erase bad blocks ! 2104 */ 2105 if (nand_block_checkbad(mtd, ((loff_t) page) << 2106 chip->page_shift, 0, allowbbt)) { 2107 printk(KERN_WARNING "nand_erase: attempt to erase a " 2108 "bad block at page 0x%08x\n", page); 2109 instr->state = MTD_ERASE_FAILED; 2110 goto erase_exit; 2111 } 2112 2113 /* 2114 * Invalidate the page cache, if we erase the block which 2115 * contains the current cached page 2116 */ 2117 if (page <= chip->pagebuf && chip->pagebuf < 2118 (page + pages_per_block)) 2119 chip->pagebuf = -1; 2120 2121 chip->erase_cmd(mtd, page & chip->pagemask); 2122 2123 status = chip->waitfunc(mtd, chip); 2124 2125 /* 2126 * See if operation failed and additional status checks are 2127 * available 2128 */ 2129 if ((status & NAND_STATUS_FAIL) && (chip->errstat)) 2130 status = chip->errstat(mtd, chip, FL_ERASING, 2131 status, page); 2132 2133 /* See if block erase succeeded */ 2134 if (status & NAND_STATUS_FAIL) { 2135 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " 2136 "Failed erase, page 0x%08x\n", page); 2137 instr->state = MTD_ERASE_FAILED; 2138 instr->fail_addr = (page << chip->page_shift); 2139 goto erase_exit; 2140 } 2141 2142 /* 2143 * If BBT requires refresh, set the BBT rewrite flag to the 2144 * page being erased 2145 */ 2146 if (bbt_masked_page != 0xffffffff && 2147 (page & BBT_PAGE_MASK) == bbt_masked_page) 2148 rewrite_bbt[chipnr] = (page << chip->page_shift); 2149 2150 /* Increment page address and decrement length */ 2151 len -= (1 << chip->phys_erase_shift); 2152 page += pages_per_block; 2153 2154 /* Check, if we cross a chip boundary */ 2155 if (len && !(page & chip->pagemask)) { 2156 chipnr++; 2157 chip->select_chip(mtd, -1); 2158 chip->select_chip(mtd, chipnr); 2159 2160 /* 2161 * If BBT requires refresh and BBT-PERCHIP, set the BBT 2162 * page mask to see if this BBT should be rewritten 2163 */ 2164 if (bbt_masked_page != 0xffffffff && 2165 (chip->bbt_td->options & NAND_BBT_PERCHIP)) 2166 bbt_masked_page = chip->bbt_td->pages[chipnr] & 2167 BBT_PAGE_MASK; 2168 } 2169 } 2170 instr->state = MTD_ERASE_DONE; 2171 2172 erase_exit: 2173 2174 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; 2175 /* Do call back function */ 2176 if (!ret) 2177 mtd_erase_callback(instr); 2178 2179 /* Deselect and wake up anyone waiting on the device */ 2180 nand_release_device(mtd); 2181 2182 /* 2183 * If BBT requires refresh and erase was successful, rewrite any 2184 * selected bad block tables 2185 */ 2186 if (bbt_masked_page == 0xffffffff || ret) 2187 return ret; 2188 2189 for (chipnr = 0; chipnr < chip->numchips; chipnr++) { 2190 if (!rewrite_bbt[chipnr]) 2191 continue; 2192 /* update the BBT for chip */ 2193 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt " 2194 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr], 2195 chip->bbt_td->pages[chipnr]); 2196 nand_update_bbt(mtd, rewrite_bbt[chipnr]); 2197 } 2198 2199 /* Return more or less happy */ 2200 return ret; 2201} 2202 2203/** 2204 * nand_sync - [MTD Interface] sync 2205 * @mtd: MTD device structure 2206 * 2207 * Sync is actually a wait for chip ready function 2208 */ 2209static void nand_sync(struct mtd_info *mtd) 2210{ 2211 struct nand_chip *chip = mtd->priv; 2212 2213 DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n"); 2214 2215 /* Grab the lock and see if the device is available */ 2216 nand_get_device(chip, mtd, FL_SYNCING); 2217 /* Release it and go back */ 2218 nand_release_device(mtd); 2219} 2220 2221/** 2222 * nand_block_isbad - [MTD Interface] Check if block at offset is bad 2223 * @mtd: MTD device structure 2224 * @offs: offset relative to mtd start 2225 */ 2226static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) 2227{ 2228 /* Check for invalid offset */ 2229 if (offs > mtd->size) 2230 return -EINVAL; 2231 2232 return nand_block_checkbad(mtd, offs, 1, 0); 2233} 2234 2235/** 2236 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad 2237 * @mtd: MTD device structure 2238 * @ofs: offset relative to mtd start 2239 */ 2240static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) 2241{ 2242 struct nand_chip *chip = mtd->priv; 2243 int ret; 2244 2245 if ((ret = nand_block_isbad(mtd, ofs))) { 2246 /* If it was bad already, return success and do nothing. */ 2247 if (ret > 0) 2248 return 0; 2249 return ret; 2250 } 2251 2252 return chip->block_markbad(mtd, ofs); 2253} 2254 2255/** 2256 * nand_suspend - [MTD Interface] Suspend the NAND flash 2257 * @mtd: MTD device structure 2258 */ 2259static int nand_suspend(struct mtd_info *mtd) 2260{ 2261 struct nand_chip *chip = mtd->priv; 2262 2263 return nand_get_device(chip, mtd, FL_PM_SUSPENDED); 2264} 2265 2266/** 2267 * nand_resume - [MTD Interface] Resume the NAND flash 2268 * @mtd: MTD device structure 2269 */ 2270static void nand_resume(struct mtd_info *mtd) 2271{ 2272 struct nand_chip *chip = mtd->priv; 2273 2274 if (chip->state == FL_PM_SUSPENDED) 2275 nand_release_device(mtd); 2276 else 2277 printk(KERN_ERR "nand_resume() called for a chip which is not " 2278 "in suspended state\n"); 2279} 2280 2281/* 2282 * Set default functions 2283 */ 2284static void nand_set_defaults(struct nand_chip *chip, int busw) 2285{ 2286 /* check for proper chip_delay setup, set 20us if not */ 2287 if (!chip->chip_delay) 2288 chip->chip_delay = 20; 2289 2290 /* check, if a user supplied command function given */ 2291 if (chip->cmdfunc == NULL) 2292 chip->cmdfunc = nand_command; 2293 2294 /* check, if a user supplied wait function given */ 2295 if (chip->waitfunc == NULL) 2296 chip->waitfunc = nand_wait; 2297 2298 if (!chip->select_chip) 2299 chip->select_chip = nand_select_chip; 2300 if (!chip->read_byte) 2301 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; 2302 if (!chip->read_word) 2303 chip->read_word = nand_read_word; 2304 if (!chip->block_bad) 2305 chip->block_bad = nand_block_bad; 2306 if (!chip->block_markbad) 2307 chip->block_markbad = nand_default_block_markbad; 2308 if (!chip->write_buf) 2309 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; 2310 if (!chip->read_buf) 2311 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; 2312 if (!chip->verify_buf) 2313 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; 2314 if (!chip->scan_bbt) 2315 chip->scan_bbt = nand_default_bbt; 2316 2317 if (!chip->controller) { 2318 chip->controller = &chip->hwcontrol; 2319 spin_lock_init(&chip->controller->lock); 2320 init_waitqueue_head(&chip->controller->wq); 2321 } 2322 2323} 2324 2325/* 2326 * Get the flash and manufacturer id and lookup if the type is supported 2327 */ 2328static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, 2329 struct nand_chip *chip, 2330 int busw, int *maf_id) 2331{ 2332 struct nand_flash_dev *type = NULL; 2333 int i, dev_id, maf_idx; 2334 int tmp_id, tmp_manf; 2335 2336 /* Select the device */ 2337 chip->select_chip(mtd, 0); 2338 2339 /* Send the command for reading device ID */ 2340 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 2341 2342 /* Read manufacturer and device IDs */ 2343 *maf_id = chip->read_byte(mtd); 2344 dev_id = chip->read_byte(mtd); 2345 2346 /* Try again to make sure, as some systems the bus-hold or other 2347 * interface concerns can cause random data which looks like a 2348 * possibly credible NAND flash to appear. If the two results do 2349 * not match, ignore the device completely. 2350 * Patched from Linux 2.6.27.57. 2351 */ 2352 2353 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 2354 2355 /* Read manufacturer and device IDs */ 2356 2357 tmp_manf = chip->read_byte(mtd); 2358 tmp_id = chip->read_byte(mtd); 2359 2360 if (tmp_manf != *maf_id || tmp_id != dev_id) { 2361 printk(KERN_INFO "%s: second ID read did not match " 2362 "%02x,%02x against %02x,%02x\n", __func__, 2363 *maf_id, dev_id, tmp_manf, tmp_id); 2364 return ERR_PTR(-ENODEV); 2365 } 2366 2367 /* Lookup the flash id */ 2368 for (i = 0; nand_flash_ids[i].name != NULL; i++) { 2369 if (dev_id == nand_flash_ids[i].id) { 2370 type = &nand_flash_ids[i]; 2371 break; 2372 } 2373 } 2374 2375 if (!type) 2376 return ERR_PTR(-ENODEV); 2377 2378 if (!mtd->name) 2379 mtd->name = type->name; 2380 2381 chip->chipsize = type->chipsize << 20; 2382 2383 /* Newer devices have all the information in additional id bytes */ 2384 if (!type->pagesize) { 2385 int extid; 2386 /* The 3rd id byte holds MLC / multichip data */ 2387 chip->cellinfo = chip->read_byte(mtd); 2388 /* The 4th id byte is the important one */ 2389 extid = chip->read_byte(mtd); 2390 /* Calc pagesize */ 2391 mtd->writesize = 1024 << (extid & 0x3); 2392 extid >>= 2; 2393 /* Calc oobsize */ 2394 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); 2395 extid >>= 2; 2396 /* Calc blocksize. Blocksize is multiples of 64KiB */ 2397 mtd->erasesize = (64 * 1024) << (extid & 0x03); 2398 extid >>= 2; 2399 /* Get buswidth information */ 2400 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; 2401 2402 } else { 2403 /* 2404 * Old devices have chip data hardcoded in the device id table 2405 */ 2406 mtd->erasesize = type->erasesize; 2407 mtd->writesize = type->pagesize; 2408 mtd->oobsize = mtd->writesize / 32; 2409 busw = type->options & NAND_BUSWIDTH_16; 2410 } 2411 2412 /* Try to identify manufacturer */ 2413 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { 2414 if (nand_manuf_ids[maf_idx].id == *maf_id) 2415 break; 2416 } 2417 2418 /* 2419 * Check, if buswidth is correct. Hardware drivers should set 2420 * chip correct ! 2421 */ 2422 if (busw != (chip->options & NAND_BUSWIDTH_16)) { 2423 printk(KERN_INFO "NAND device: Manufacturer ID:" 2424 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, 2425 dev_id, nand_manuf_ids[maf_idx].name, mtd->name); 2426 printk(KERN_WARNING "NAND bus width %d instead %d bit\n", 2427 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, 2428 busw ? 16 : 8); 2429 return ERR_PTR(-EINVAL); 2430 } 2431 2432 /* Calculate the address shift from the page size */ 2433 chip->page_shift = ffs(mtd->writesize) - 1; 2434 /* Convert chipsize to number of pages per chip -1. */ 2435 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; 2436 2437 chip->bbt_erase_shift = chip->phys_erase_shift = 2438 ffs(mtd->erasesize) - 1; 2439 chip->chip_shift = ffs(chip->chipsize) - 1; 2440 2441 /* Set the bad block position */ 2442 chip->badblockpos = mtd->writesize > 512 ? 2443 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; 2444 2445 /* Get chip options, preserve non chip based options */ 2446 chip->options &= ~NAND_CHIPOPTIONS_MSK; 2447 chip->options |= type->options & NAND_CHIPOPTIONS_MSK; 2448 2449 /* 2450 * Set chip as a default. Board drivers can override it, if necessary 2451 */ 2452 chip->options |= NAND_NO_AUTOINCR; 2453 2454 /* Check if chip is a not a samsung device. Do not clear the 2455 * options for chips which are not having an extended id. 2456 */ 2457 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) 2458 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; 2459 2460 /* Check for AND chips with 4 page planes */ 2461 if (chip->options & NAND_4PAGE_ARRAY) 2462 chip->erase_cmd = multi_erase_cmd; 2463 else 2464 chip->erase_cmd = single_erase_cmd; 2465 2466 /* Do not replace user supplied command function ! */ 2467 if (mtd->writesize > 512 && chip->cmdfunc == nand_command) 2468 chip->cmdfunc = nand_command_lp; 2469 2470 printk(KERN_INFO "NAND device: Manufacturer ID:" 2471 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id, 2472 nand_manuf_ids[maf_idx].name, type->name); 2473 2474#ifdef CONFIG_MTD_BRCMNAND 2475 DEBUG(MTD_DEBUG_LEVEL3, "NAND device: mtd->writesize=%d mtd->oobsize=%d " 2476 "mtd->erasesize=%d busw=%d\n", 2477 mtd->writesize, mtd->oobsize, mtd->erasesize, busw); 2478 2479 DEBUG(MTD_DEBUG_LEVEL3, "NAND device: page_shift=%d pagemask=%d bbt_erase_shift=%d " 2480 "chip_shift=%d badblockpos=%d options=%02x\n", 2481 chip->page_shift, chip->pagemask, chip->bbt_erase_shift, 2482 chip->chip_shift, chip->badblockpos, chip->options); 2483#endif /* CONFIG_MTD_BRCMNAND */ 2484 2485 return type; 2486} 2487 2488/** 2489 * nand_scan_ident - [NAND Interface] Scan for the NAND device 2490 * @mtd: MTD device structure 2491 * @maxchips: Number of chips to scan for 2492 * 2493 * This is the first phase of the normal nand_scan() function. It 2494 * reads the flash ID and sets up MTD fields accordingly. 2495 * 2496 * The mtd->owner field must be set to the module of the caller. 2497 */ 2498int nand_scan_ident(struct mtd_info *mtd, int maxchips) 2499{ 2500 int i, busw, nand_maf_id; 2501 struct nand_chip *chip = mtd->priv; 2502 struct nand_flash_dev *type; 2503 2504 /* Get buswidth to select the correct functions */ 2505 busw = chip->options & NAND_BUSWIDTH_16; 2506 /* Set the default functions */ 2507 nand_set_defaults(chip, busw); 2508 2509 /* Read the flash type */ 2510 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id); 2511 2512 if (IS_ERR(type)) { 2513 printk(KERN_WARNING "No NAND device found!!!\n"); 2514 chip->select_chip(mtd, -1); 2515 return PTR_ERR(type); 2516 } 2517 2518 /* Check for a chip array */ 2519 for (i = 1; i < maxchips; i++) { 2520 chip->select_chip(mtd, i); 2521 /* Send the command for reading device ID */ 2522 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 2523 /* Read manufacturer and device IDs */ 2524 if (nand_maf_id != chip->read_byte(mtd) || 2525 type->id != chip->read_byte(mtd)) 2526 break; 2527 } 2528 if (i > 1) 2529 printk(KERN_INFO "%d NAND chips detected\n", i); 2530 2531 /* Store the number of chips and calc total size for mtd */ 2532 chip->numchips = i; 2533 mtd->size = i * chip->chipsize; 2534 2535 return 0; 2536} 2537 2538 2539/** 2540 * nand_scan_tail - [NAND Interface] Scan for the NAND device 2541 * @mtd: MTD device structure 2542 * @maxchips: Number of chips to scan for 2543 * 2544 * This is the second phase of the normal nand_scan() function. It 2545 * fills out all the uninitialized function pointers with the defaults 2546 * and scans for a bad block table if appropriate. 2547 */ 2548int nand_scan_tail(struct mtd_info *mtd) 2549{ 2550 int i; 2551 struct nand_chip *chip = mtd->priv; 2552 2553 if (!(chip->options & NAND_OWN_BUFFERS)) 2554 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); 2555 if (!chip->buffers) 2556 return -ENOMEM; 2557 2558 /* Set the internal oob buffer location, just after the page data */ 2559 chip->oob_poi = chip->buffers->databuf + mtd->writesize; 2560 2561 /* 2562 * If no default placement scheme is given, select an appropriate one 2563 */ 2564 if (!chip->ecc.layout) { 2565 switch (mtd->oobsize) { 2566 case 8: 2567 chip->ecc.layout = &nand_oob_8; 2568 break; 2569 case 16: 2570 chip->ecc.layout = &nand_oob_16; 2571 break; 2572 case 64: 2573 chip->ecc.layout = &nand_oob_64; 2574 break; 2575 default: 2576 printk(KERN_WARNING "No oob scheme defined for " 2577 "oobsize %d\n", mtd->oobsize); 2578 BUG(); 2579 } 2580 } 2581 2582 if (!chip->write_page) 2583 chip->write_page = nand_write_page; 2584 2585 /* 2586 * check ECC mode, default to software if 3byte/512byte hardware ECC is 2587 * selected and we have 256 byte pagesize fallback to software ECC 2588 */ 2589 if (!chip->ecc.read_page_raw) 2590 chip->ecc.read_page_raw = nand_read_page_raw; 2591 if (!chip->ecc.write_page_raw) 2592 chip->ecc.write_page_raw = nand_write_page_raw; 2593 2594 switch (chip->ecc.mode) { 2595 case NAND_ECC_HW: 2596 /* Use standard hwecc read page function ? */ 2597 if (!chip->ecc.read_page) 2598 chip->ecc.read_page = nand_read_page_hwecc; 2599 if (!chip->ecc.write_page) 2600 chip->ecc.write_page = nand_write_page_hwecc; 2601 if (!chip->ecc.read_oob) 2602 chip->ecc.read_oob = nand_read_oob_std; 2603 if (!chip->ecc.write_oob) 2604 chip->ecc.write_oob = nand_write_oob_std; 2605 2606 case NAND_ECC_HW_SYNDROME: 2607 if (!chip->ecc.calculate || !chip->ecc.correct || 2608 !chip->ecc.hwctl) { 2609 printk(KERN_WARNING "No ECC functions supplied, " 2610 "Hardware ECC not possible\n"); 2611 BUG(); 2612 } 2613 /* Use standard syndrome read/write page function ? */ 2614 if (!chip->ecc.read_page) 2615 chip->ecc.read_page = nand_read_page_syndrome; 2616 if (!chip->ecc.write_page) 2617 chip->ecc.write_page = nand_write_page_syndrome; 2618 if (!chip->ecc.read_oob) 2619 chip->ecc.read_oob = nand_read_oob_syndrome; 2620 if (!chip->ecc.write_oob) 2621 chip->ecc.write_oob = nand_write_oob_syndrome; 2622 2623 if (mtd->writesize >= chip->ecc.size) 2624 break; 2625 printk(KERN_WARNING "%d byte HW ECC not possible on " 2626 "%d byte page size, fallback to SW ECC\n", 2627 chip->ecc.size, mtd->writesize); 2628 chip->ecc.mode = NAND_ECC_SOFT; 2629 2630 case NAND_ECC_SOFT: 2631 chip->ecc.calculate = nand_calculate_ecc; 2632 chip->ecc.correct = nand_correct_data; 2633 chip->ecc.read_page = nand_read_page_swecc; 2634 /* Patched from Linux 2.6.27.57 */ 2635 chip->ecc.read_subpage = nand_read_subpage; 2636 chip->ecc.write_page = nand_write_page_swecc; 2637 chip->ecc.read_oob = nand_read_oob_std; 2638 chip->ecc.write_oob = nand_write_oob_std; 2639 chip->ecc.size = 256; 2640 chip->ecc.bytes = 3; 2641 break; 2642 2643 case NAND_ECC_NONE: 2644 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " 2645 "This is not recommended !!\n"); 2646 chip->ecc.read_page = nand_read_page_raw; 2647 chip->ecc.write_page = nand_write_page_raw; 2648 chip->ecc.read_oob = nand_read_oob_std; 2649 chip->ecc.write_oob = nand_write_oob_std; 2650 chip->ecc.size = mtd->writesize; 2651 chip->ecc.bytes = 0; 2652 break; 2653 2654 default: 2655 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", 2656 chip->ecc.mode); 2657 BUG(); 2658 } 2659 2660 /* 2661 * The number of bytes available for a client to place data into 2662 * the out of band area 2663 */ 2664 chip->ecc.layout->oobavail = 0; 2665 for (i = 0; chip->ecc.layout->oobfree[i].length; i++) 2666 chip->ecc.layout->oobavail += 2667 chip->ecc.layout->oobfree[i].length; 2668 mtd->oobavail = chip->ecc.layout->oobavail; 2669 2670 /* 2671 * Set the number of read / write steps for one page depending on ECC 2672 * mode 2673 */ 2674 chip->ecc.steps = mtd->writesize / chip->ecc.size; 2675 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) { 2676 printk(KERN_WARNING "Invalid ecc parameters\n"); 2677 BUG(); 2678 } 2679 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; 2680 2681 /* 2682 * Allow subpage writes up to ecc.steps. Not possible for MLC 2683 * FLASH. 2684 */ 2685 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && 2686 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { 2687 switch(chip->ecc.steps) { 2688 case 2: 2689 mtd->subpage_sft = 1; 2690 break; 2691 case 4: 2692 case 8: 2693 mtd->subpage_sft = 2; 2694 break; 2695 } 2696 } 2697 chip->subpagesize = mtd->writesize >> mtd->subpage_sft; 2698 2699 /* Initialize state */ 2700 chip->state = FL_READY; 2701 2702 /* De-select the device */ 2703 chip->select_chip(mtd, -1); 2704 2705 /* Invalidate the pagebuffer reference */ 2706 chip->pagebuf = -1; 2707 2708 /* Fill in remaining MTD driver data */ 2709 mtd->type = MTD_NANDFLASH; 2710 mtd->flags = MTD_CAP_NANDFLASH; 2711 mtd->erase = nand_erase; 2712 mtd->point = NULL; 2713 mtd->unpoint = NULL; 2714 mtd->read = nand_read; 2715 mtd->write = nand_write; 2716 mtd->read_oob = nand_read_oob; 2717 mtd->write_oob = nand_write_oob; 2718 mtd->sync = nand_sync; 2719 mtd->lock = NULL; 2720 mtd->unlock = NULL; 2721 mtd->suspend = nand_suspend; 2722 mtd->resume = nand_resume; 2723 mtd->block_isbad = nand_block_isbad; 2724 mtd->block_markbad = nand_block_markbad; 2725 2726 /* propagate ecc.layout to mtd_info */ 2727 mtd->ecclayout = chip->ecc.layout; 2728 2729 /* Check, if we should skip the bad block table scan */ 2730 if (chip->options & NAND_SKIP_BBTSCAN) 2731 return 0; 2732 2733 /* Build bad block table */ 2734 return chip->scan_bbt(mtd); 2735} 2736 2737/* module_text_address() isn't exported, and it's mostly a pointless 2738 test if this is a module _anyway_ -- they'd have to try _really_ hard 2739 to call us from in-kernel code if the core NAND support is modular. */ 2740#ifdef MODULE 2741#define caller_is_module() (1) 2742#else 2743#define caller_is_module() \ 2744 module_text_address((unsigned long)__builtin_return_address(0)) 2745#endif 2746 2747/** 2748 * nand_scan - [NAND Interface] Scan for the NAND device 2749 * @mtd: MTD device structure 2750 * @maxchips: Number of chips to scan for 2751 * 2752 * This fills out all the uninitialized function pointers 2753 * with the defaults. 2754 * The flash ID is read and the mtd/chip structures are 2755 * filled with the appropriate values. 2756 * The mtd->owner field must be set to the module of the caller 2757 * 2758 */ 2759int nand_scan(struct mtd_info *mtd, int maxchips) 2760{ 2761 int ret; 2762 2763 /* Many callers got this wrong, so check for it for a while... */ 2764 if (!mtd->owner && caller_is_module()) { 2765 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n"); 2766 BUG(); 2767 } 2768 2769 ret = nand_scan_ident(mtd, maxchips); 2770 if (!ret) 2771 ret = nand_scan_tail(mtd); 2772 return ret; 2773} 2774 2775/** 2776 * nand_release - [NAND Interface] Free resources held by the NAND device 2777 * @mtd: MTD device structure 2778*/ 2779void nand_release(struct mtd_info *mtd) 2780{ 2781 struct nand_chip *chip = mtd->priv; 2782 2783#ifdef CONFIG_MTD_PARTITIONS 2784 /* Deregister partitions */ 2785 del_mtd_partitions(mtd); 2786#endif 2787 /* Deregister the device */ 2788 del_mtd_device(mtd); 2789 2790 /* Free bad block table memory */ 2791 kfree(chip->bbt); 2792 if (!(chip->options & NAND_OWN_BUFFERS)) 2793 kfree(chip->buffers); 2794} 2795 2796EXPORT_SYMBOL_GPL(nand_scan); 2797EXPORT_SYMBOL_GPL(nand_scan_ident); 2798EXPORT_SYMBOL_GPL(nand_scan_tail); 2799EXPORT_SYMBOL_GPL(nand_release); 2800 2801static int __init nand_base_init(void) 2802{ 2803 led_trigger_register_simple("nand-disk", &nand_led_trigger); 2804 return 0; 2805} 2806 2807static void __exit nand_base_exit(void) 2808{ 2809 led_trigger_unregister_simple(nand_led_trigger); 2810} 2811 2812module_init(nand_base_init); 2813module_exit(nand_base_exit); 2814 2815MODULE_LICENSE("GPL"); 2816MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>"); 2817MODULE_DESCRIPTION("Generic NAND flash driver code"); 2818