1/* 2 * linux/drivers/media/mmc/omap.c 3 * 4 * Copyright (C) 2004 Nokia Corporation 5 * Written by Tuukka Tikkanen and Juha Yrj�l�<juha.yrjola@nokia.com> 6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com> 7 * Other hacks (DMA, SD, etc) by David Brownell 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14#include <linux/module.h> 15#include <linux/moduleparam.h> 16#include <linux/init.h> 17#include <linux/ioport.h> 18#include <linux/platform_device.h> 19#include <linux/interrupt.h> 20#include <linux/dma-mapping.h> 21#include <linux/delay.h> 22#include <linux/spinlock.h> 23#include <linux/timer.h> 24#include <linux/mmc/host.h> 25#include <linux/mmc/card.h> 26#include <linux/clk.h> 27 28#include <asm/io.h> 29#include <asm/irq.h> 30#include <asm/scatterlist.h> 31#include <asm/mach-types.h> 32 33#include <asm/arch/board.h> 34#include <asm/arch/gpio.h> 35#include <asm/arch/dma.h> 36#include <asm/arch/mux.h> 37#include <asm/arch/fpga.h> 38#include <asm/arch/tps65010.h> 39 40#define OMAP_MMC_REG_CMD 0x00 41#define OMAP_MMC_REG_ARGL 0x04 42#define OMAP_MMC_REG_ARGH 0x08 43#define OMAP_MMC_REG_CON 0x0c 44#define OMAP_MMC_REG_STAT 0x10 45#define OMAP_MMC_REG_IE 0x14 46#define OMAP_MMC_REG_CTO 0x18 47#define OMAP_MMC_REG_DTO 0x1c 48#define OMAP_MMC_REG_DATA 0x20 49#define OMAP_MMC_REG_BLEN 0x24 50#define OMAP_MMC_REG_NBLK 0x28 51#define OMAP_MMC_REG_BUF 0x2c 52#define OMAP_MMC_REG_SDIO 0x34 53#define OMAP_MMC_REG_REV 0x3c 54#define OMAP_MMC_REG_RSP0 0x40 55#define OMAP_MMC_REG_RSP1 0x44 56#define OMAP_MMC_REG_RSP2 0x48 57#define OMAP_MMC_REG_RSP3 0x4c 58#define OMAP_MMC_REG_RSP4 0x50 59#define OMAP_MMC_REG_RSP5 0x54 60#define OMAP_MMC_REG_RSP6 0x58 61#define OMAP_MMC_REG_RSP7 0x5c 62#define OMAP_MMC_REG_IOSR 0x60 63#define OMAP_MMC_REG_SYSC 0x64 64#define OMAP_MMC_REG_SYSS 0x68 65 66#define OMAP_MMC_STAT_CARD_ERR (1 << 14) 67#define OMAP_MMC_STAT_CARD_IRQ (1 << 13) 68#define OMAP_MMC_STAT_OCR_BUSY (1 << 12) 69#define OMAP_MMC_STAT_A_EMPTY (1 << 11) 70#define OMAP_MMC_STAT_A_FULL (1 << 10) 71#define OMAP_MMC_STAT_CMD_CRC (1 << 8) 72#define OMAP_MMC_STAT_CMD_TOUT (1 << 7) 73#define OMAP_MMC_STAT_DATA_CRC (1 << 6) 74#define OMAP_MMC_STAT_DATA_TOUT (1 << 5) 75#define OMAP_MMC_STAT_END_BUSY (1 << 4) 76#define OMAP_MMC_STAT_END_OF_DATA (1 << 3) 77#define OMAP_MMC_STAT_CARD_BUSY (1 << 2) 78#define OMAP_MMC_STAT_END_OF_CMD (1 << 0) 79 80#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg) 81#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg) 82 83/* 84 * Command types 85 */ 86#define OMAP_MMC_CMDTYPE_BC 0 87#define OMAP_MMC_CMDTYPE_BCR 1 88#define OMAP_MMC_CMDTYPE_AC 2 89#define OMAP_MMC_CMDTYPE_ADTC 3 90 91 92#define DRIVER_NAME "mmci-omap" 93 94/* Specifies how often in millisecs to poll for card status changes 95 * when the cover switch is open */ 96#define OMAP_MMC_SWITCH_POLL_DELAY 500 97 98static int mmc_omap_enable_poll = 1; 99 100struct mmc_omap_host { 101 int initialized; 102 int suspended; 103 struct mmc_request * mrq; 104 struct mmc_command * cmd; 105 struct mmc_data * data; 106 struct mmc_host * mmc; 107 struct device * dev; 108 unsigned char id; /* 16xx chips have 2 MMC blocks */ 109 struct clk * iclk; 110 struct clk * fclk; 111 struct resource *mem_res; 112 void __iomem *virt_base; 113 unsigned int phys_base; 114 int irq; 115 unsigned char bus_mode; 116 unsigned char hw_bus_mode; 117 118 unsigned int sg_len; 119 int sg_idx; 120 u16 * buffer; 121 u32 buffer_bytes_left; 122 u32 total_bytes_left; 123 124 unsigned use_dma:1; 125 unsigned brs_received:1, dma_done:1; 126 unsigned dma_is_read:1; 127 unsigned dma_in_use:1; 128 int dma_ch; 129 spinlock_t dma_lock; 130 struct timer_list dma_timer; 131 unsigned dma_len; 132 133 short power_pin; 134 short wp_pin; 135 136 int switch_pin; 137 struct work_struct switch_work; 138 struct timer_list switch_timer; 139 int switch_last_state; 140}; 141 142static inline int 143mmc_omap_cover_is_open(struct mmc_omap_host *host) 144{ 145 if (host->switch_pin < 0) 146 return 0; 147 return omap_get_gpio_datain(host->switch_pin); 148} 149 150static ssize_t 151mmc_omap_show_cover_switch(struct device *dev, 152 struct device_attribute *attr, char *buf) 153{ 154 struct mmc_omap_host *host = dev_get_drvdata(dev); 155 156 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" : 157 "closed"); 158} 159 160static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL); 161 162static ssize_t 163mmc_omap_show_enable_poll(struct device *dev, 164 struct device_attribute *attr, char *buf) 165{ 166 return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll); 167} 168 169static ssize_t 170mmc_omap_store_enable_poll(struct device *dev, 171 struct device_attribute *attr, const char *buf, 172 size_t size) 173{ 174 int enable_poll; 175 176 if (sscanf(buf, "%10d", &enable_poll) != 1) 177 return -EINVAL; 178 179 if (enable_poll != mmc_omap_enable_poll) { 180 struct mmc_omap_host *host = dev_get_drvdata(dev); 181 182 mmc_omap_enable_poll = enable_poll; 183 if (enable_poll && host->switch_pin >= 0) 184 schedule_work(&host->switch_work); 185 } 186 return size; 187} 188 189static DEVICE_ATTR(enable_poll, 0664, 190 mmc_omap_show_enable_poll, mmc_omap_store_enable_poll); 191 192static void 193mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd) 194{ 195 u32 cmdreg; 196 u32 resptype; 197 u32 cmdtype; 198 199 host->cmd = cmd; 200 201 resptype = 0; 202 cmdtype = 0; 203 204 /* Our hardware needs to know exact type */ 205 switch (mmc_resp_type(cmd)) { 206 case MMC_RSP_NONE: 207 break; 208 case MMC_RSP_R1: 209 case MMC_RSP_R1B: 210 /* resp 1, 1b, 6, 7 */ 211 resptype = 1; 212 break; 213 case MMC_RSP_R2: 214 resptype = 2; 215 break; 216 case MMC_RSP_R3: 217 resptype = 3; 218 break; 219 default: 220 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd)); 221 break; 222 } 223 224 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) { 225 cmdtype = OMAP_MMC_CMDTYPE_ADTC; 226 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) { 227 cmdtype = OMAP_MMC_CMDTYPE_BC; 228 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) { 229 cmdtype = OMAP_MMC_CMDTYPE_BCR; 230 } else { 231 cmdtype = OMAP_MMC_CMDTYPE_AC; 232 } 233 234 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12); 235 236 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) 237 cmdreg |= 1 << 6; 238 239 if (cmd->flags & MMC_RSP_BUSY) 240 cmdreg |= 1 << 11; 241 242 if (host->data && !(host->data->flags & MMC_DATA_WRITE)) 243 cmdreg |= 1 << 15; 244 245 clk_enable(host->fclk); 246 247 OMAP_MMC_WRITE(host, CTO, 200); 248 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff); 249 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16); 250 OMAP_MMC_WRITE(host, IE, 251 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL | 252 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT | 253 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT | 254 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR | 255 OMAP_MMC_STAT_END_OF_DATA); 256 OMAP_MMC_WRITE(host, CMD, cmdreg); 257} 258 259static void 260mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data) 261{ 262 if (host->dma_in_use) { 263 enum dma_data_direction dma_data_dir; 264 265 BUG_ON(host->dma_ch < 0); 266 if (data->error != MMC_ERR_NONE) 267 omap_stop_dma(host->dma_ch); 268 /* Release DMA channel lazily */ 269 mod_timer(&host->dma_timer, jiffies + HZ); 270 if (data->flags & MMC_DATA_WRITE) 271 dma_data_dir = DMA_TO_DEVICE; 272 else 273 dma_data_dir = DMA_FROM_DEVICE; 274 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len, 275 dma_data_dir); 276 } 277 host->data = NULL; 278 host->sg_len = 0; 279 clk_disable(host->fclk); 280 281 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing 282 * dozens of requests until the card finishes writing data. 283 * It'd be cheaper to just wait till an EOFB interrupt arrives... 284 */ 285 286 if (!data->stop) { 287 host->mrq = NULL; 288 mmc_request_done(host->mmc, data->mrq); 289 return; 290 } 291 292 mmc_omap_start_command(host, data->stop); 293} 294 295static void 296mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data) 297{ 298 unsigned long flags; 299 int done; 300 301 if (!host->dma_in_use) { 302 mmc_omap_xfer_done(host, data); 303 return; 304 } 305 done = 0; 306 spin_lock_irqsave(&host->dma_lock, flags); 307 if (host->dma_done) 308 done = 1; 309 else 310 host->brs_received = 1; 311 spin_unlock_irqrestore(&host->dma_lock, flags); 312 if (done) 313 mmc_omap_xfer_done(host, data); 314} 315 316static void 317mmc_omap_dma_timer(unsigned long data) 318{ 319 struct mmc_omap_host *host = (struct mmc_omap_host *) data; 320 321 BUG_ON(host->dma_ch < 0); 322 omap_free_dma(host->dma_ch); 323 host->dma_ch = -1; 324} 325 326static void 327mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data) 328{ 329 unsigned long flags; 330 int done; 331 332 done = 0; 333 spin_lock_irqsave(&host->dma_lock, flags); 334 if (host->brs_received) 335 done = 1; 336 else 337 host->dma_done = 1; 338 spin_unlock_irqrestore(&host->dma_lock, flags); 339 if (done) 340 mmc_omap_xfer_done(host, data); 341} 342 343static void 344mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) 345{ 346 host->cmd = NULL; 347 348 if (cmd->flags & MMC_RSP_PRESENT) { 349 if (cmd->flags & MMC_RSP_136) { 350 /* response type 2 */ 351 cmd->resp[3] = 352 OMAP_MMC_READ(host, RSP0) | 353 (OMAP_MMC_READ(host, RSP1) << 16); 354 cmd->resp[2] = 355 OMAP_MMC_READ(host, RSP2) | 356 (OMAP_MMC_READ(host, RSP3) << 16); 357 cmd->resp[1] = 358 OMAP_MMC_READ(host, RSP4) | 359 (OMAP_MMC_READ(host, RSP5) << 16); 360 cmd->resp[0] = 361 OMAP_MMC_READ(host, RSP6) | 362 (OMAP_MMC_READ(host, RSP7) << 16); 363 } else { 364 /* response types 1, 1b, 3, 4, 5, 6 */ 365 cmd->resp[0] = 366 OMAP_MMC_READ(host, RSP6) | 367 (OMAP_MMC_READ(host, RSP7) << 16); 368 } 369 } 370 371 if (host->data == NULL || cmd->error != MMC_ERR_NONE) { 372 host->mrq = NULL; 373 clk_disable(host->fclk); 374 mmc_request_done(host->mmc, cmd->mrq); 375 } 376} 377 378/* PIO only */ 379static void 380mmc_omap_sg_to_buf(struct mmc_omap_host *host) 381{ 382 struct scatterlist *sg; 383 384 sg = host->data->sg + host->sg_idx; 385 host->buffer_bytes_left = sg->length; 386 host->buffer = page_address(sg->page) + sg->offset; 387 if (host->buffer_bytes_left > host->total_bytes_left) 388 host->buffer_bytes_left = host->total_bytes_left; 389} 390 391/* PIO only */ 392static void 393mmc_omap_xfer_data(struct mmc_omap_host *host, int write) 394{ 395 int n; 396 397 if (host->buffer_bytes_left == 0) { 398 host->sg_idx++; 399 BUG_ON(host->sg_idx == host->sg_len); 400 mmc_omap_sg_to_buf(host); 401 } 402 n = 64; 403 if (n > host->buffer_bytes_left) 404 n = host->buffer_bytes_left; 405 host->buffer_bytes_left -= n; 406 host->total_bytes_left -= n; 407 host->data->bytes_xfered += n; 408 409 if (write) { 410 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n); 411 } else { 412 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n); 413 } 414} 415 416static inline void mmc_omap_report_irq(u16 status) 417{ 418 static const char *mmc_omap_status_bits[] = { 419 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO", 420 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR" 421 }; 422 int i, c = 0; 423 424 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++) 425 if (status & (1 << i)) { 426 if (c) 427 printk(" "); 428 printk("%s", mmc_omap_status_bits[i]); 429 c++; 430 } 431} 432 433static irqreturn_t mmc_omap_irq(int irq, void *dev_id) 434{ 435 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id; 436 u16 status; 437 int end_command; 438 int end_transfer; 439 int transfer_error; 440 441 if (host->cmd == NULL && host->data == NULL) { 442 status = OMAP_MMC_READ(host, STAT); 443 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status); 444 if (status != 0) { 445 OMAP_MMC_WRITE(host, STAT, status); 446 OMAP_MMC_WRITE(host, IE, 0); 447 } 448 return IRQ_HANDLED; 449 } 450 451 end_command = 0; 452 end_transfer = 0; 453 transfer_error = 0; 454 455 while ((status = OMAP_MMC_READ(host, STAT)) != 0) { 456 OMAP_MMC_WRITE(host, STAT, status); 457#ifdef CONFIG_MMC_DEBUG 458 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ", 459 status, host->cmd != NULL ? host->cmd->opcode : -1); 460 mmc_omap_report_irq(status); 461 printk("\n"); 462#endif 463 if (host->total_bytes_left) { 464 if ((status & OMAP_MMC_STAT_A_FULL) || 465 (status & OMAP_MMC_STAT_END_OF_DATA)) 466 mmc_omap_xfer_data(host, 0); 467 if (status & OMAP_MMC_STAT_A_EMPTY) 468 mmc_omap_xfer_data(host, 1); 469 } 470 471 if (status & OMAP_MMC_STAT_END_OF_DATA) { 472 end_transfer = 1; 473 } 474 475 if (status & OMAP_MMC_STAT_DATA_TOUT) { 476 dev_dbg(mmc_dev(host->mmc), "data timeout\n"); 477 if (host->data) { 478 host->data->error |= MMC_ERR_TIMEOUT; 479 transfer_error = 1; 480 } 481 } 482 483 if (status & OMAP_MMC_STAT_DATA_CRC) { 484 if (host->data) { 485 host->data->error |= MMC_ERR_BADCRC; 486 dev_dbg(mmc_dev(host->mmc), 487 "data CRC error, bytes left %d\n", 488 host->total_bytes_left); 489 transfer_error = 1; 490 } else { 491 dev_dbg(mmc_dev(host->mmc), "data CRC error\n"); 492 } 493 } 494 495 if (status & OMAP_MMC_STAT_CMD_TOUT) { 496 /* Timeouts are routine with some commands */ 497 if (host->cmd) { 498 if (host->cmd->opcode != MMC_ALL_SEND_CID && 499 host->cmd->opcode != 500 MMC_SEND_OP_COND && 501 host->cmd->opcode != 502 MMC_APP_CMD && 503 !mmc_omap_cover_is_open(host)) 504 dev_err(mmc_dev(host->mmc), 505 "command timeout, CMD %d\n", 506 host->cmd->opcode); 507 host->cmd->error = MMC_ERR_TIMEOUT; 508 end_command = 1; 509 } 510 } 511 512 if (status & OMAP_MMC_STAT_CMD_CRC) { 513 if (host->cmd) { 514 dev_err(mmc_dev(host->mmc), 515 "command CRC error (CMD%d, arg 0x%08x)\n", 516 host->cmd->opcode, host->cmd->arg); 517 host->cmd->error = MMC_ERR_BADCRC; 518 end_command = 1; 519 } else 520 dev_err(mmc_dev(host->mmc), 521 "command CRC error without cmd?\n"); 522 } 523 524 if (status & OMAP_MMC_STAT_CARD_ERR) { 525 dev_dbg(mmc_dev(host->mmc), 526 "ignoring card status error (CMD%d)\n", 527 host->cmd->opcode); 528 end_command = 1; 529 } 530 531 /* 532 * NOTE: On 1610 the END_OF_CMD may come too early when 533 * starting a write 534 */ 535 if ((status & OMAP_MMC_STAT_END_OF_CMD) && 536 (!(status & OMAP_MMC_STAT_A_EMPTY))) { 537 end_command = 1; 538 } 539 } 540 541 if (end_command) { 542 mmc_omap_cmd_done(host, host->cmd); 543 } 544 if (transfer_error) 545 mmc_omap_xfer_done(host, host->data); 546 else if (end_transfer) 547 mmc_omap_end_of_data(host, host->data); 548 549 return IRQ_HANDLED; 550} 551 552static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id) 553{ 554 struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id; 555 556 schedule_work(&host->switch_work); 557 558 return IRQ_HANDLED; 559} 560 561static void mmc_omap_switch_timer(unsigned long arg) 562{ 563 struct mmc_omap_host *host = (struct mmc_omap_host *) arg; 564 565 schedule_work(&host->switch_work); 566} 567 568static void mmc_omap_switch_handler(struct work_struct *work) 569{ 570 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, switch_work); 571 struct mmc_card *card; 572 static int complained = 0; 573 int cards = 0, cover_open; 574 575 if (host->switch_pin == -1) 576 return; 577 cover_open = mmc_omap_cover_is_open(host); 578 if (cover_open != host->switch_last_state) { 579 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE); 580 host->switch_last_state = cover_open; 581 } 582 mmc_detect_change(host->mmc, 0); 583 list_for_each_entry(card, &host->mmc->cards, node) { 584 if (mmc_card_present(card)) 585 cards++; 586 } 587 if (mmc_omap_cover_is_open(host)) { 588 if (!complained) { 589 dev_info(mmc_dev(host->mmc), "cover is open\n"); 590 complained = 1; 591 } 592 if (mmc_omap_enable_poll) 593 mod_timer(&host->switch_timer, jiffies + 594 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY)); 595 } else { 596 complained = 0; 597 } 598} 599 600/* Prepare to transfer the next segment of a scatterlist */ 601static void 602mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data) 603{ 604 int dma_ch = host->dma_ch; 605 unsigned long data_addr; 606 u16 buf, frame; 607 u32 count; 608 struct scatterlist *sg = &data->sg[host->sg_idx]; 609 int src_port = 0; 610 int dst_port = 0; 611 int sync_dev = 0; 612 613 data_addr = host->phys_base + OMAP_MMC_REG_DATA; 614 frame = data->blksz; 615 count = sg_dma_len(sg); 616 617 if ((data->blocks == 1) && (count > data->blksz)) 618 count = frame; 619 620 host->dma_len = count; 621 622 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx. 623 * Use 16 or 32 word frames when the blocksize is at least that large. 624 * Blocksize is usually 512 bytes; but not for some SD reads. 625 */ 626 if (cpu_is_omap15xx() && frame > 32) 627 frame = 32; 628 else if (frame > 64) 629 frame = 64; 630 count /= frame; 631 frame >>= 1; 632 633 if (!(data->flags & MMC_DATA_WRITE)) { 634 buf = 0x800f | ((frame - 1) << 8); 635 636 if (cpu_class_is_omap1()) { 637 src_port = OMAP_DMA_PORT_TIPB; 638 dst_port = OMAP_DMA_PORT_EMIFF; 639 } 640 if (cpu_is_omap24xx()) 641 sync_dev = OMAP24XX_DMA_MMC1_RX; 642 643 omap_set_dma_src_params(dma_ch, src_port, 644 OMAP_DMA_AMODE_CONSTANT, 645 data_addr, 0, 0); 646 omap_set_dma_dest_params(dma_ch, dst_port, 647 OMAP_DMA_AMODE_POST_INC, 648 sg_dma_address(sg), 0, 0); 649 omap_set_dma_dest_data_pack(dma_ch, 1); 650 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4); 651 } else { 652 buf = 0x0f80 | ((frame - 1) << 0); 653 654 if (cpu_class_is_omap1()) { 655 src_port = OMAP_DMA_PORT_EMIFF; 656 dst_port = OMAP_DMA_PORT_TIPB; 657 } 658 if (cpu_is_omap24xx()) 659 sync_dev = OMAP24XX_DMA_MMC1_TX; 660 661 omap_set_dma_dest_params(dma_ch, dst_port, 662 OMAP_DMA_AMODE_CONSTANT, 663 data_addr, 0, 0); 664 omap_set_dma_src_params(dma_ch, src_port, 665 OMAP_DMA_AMODE_POST_INC, 666 sg_dma_address(sg), 0, 0); 667 omap_set_dma_src_data_pack(dma_ch, 1); 668 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4); 669 } 670 671 /* Max limit for DMA frame count is 0xffff */ 672 BUG_ON(count > 0xffff); 673 674 OMAP_MMC_WRITE(host, BUF, buf); 675 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16, 676 frame, count, OMAP_DMA_SYNC_FRAME, 677 sync_dev, 0); 678} 679 680/* A scatterlist segment completed */ 681static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data) 682{ 683 struct mmc_omap_host *host = (struct mmc_omap_host *) data; 684 struct mmc_data *mmcdat = host->data; 685 686 if (unlikely(host->dma_ch < 0)) { 687 dev_err(mmc_dev(host->mmc), 688 "DMA callback while DMA not enabled\n"); 689 return; 690 } 691 if (ch_status & OMAP1_DMA_TOUT_IRQ) { 692 dev_err(mmc_dev(host->mmc),"DMA timeout\n"); 693 return; 694 } 695 if (ch_status & OMAP_DMA_DROP_IRQ) { 696 dev_err(mmc_dev(host->mmc), "DMA sync error\n"); 697 return; 698 } 699 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) { 700 return; 701 } 702 mmcdat->bytes_xfered += host->dma_len; 703 host->sg_idx++; 704 if (host->sg_idx < host->sg_len) { 705 mmc_omap_prepare_dma(host, host->data); 706 omap_start_dma(host->dma_ch); 707 } else 708 mmc_omap_dma_done(host, host->data); 709} 710 711static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data) 712{ 713 const char *dev_name; 714 int sync_dev, dma_ch, is_read, r; 715 716 is_read = !(data->flags & MMC_DATA_WRITE); 717 del_timer_sync(&host->dma_timer); 718 if (host->dma_ch >= 0) { 719 if (is_read == host->dma_is_read) 720 return 0; 721 omap_free_dma(host->dma_ch); 722 host->dma_ch = -1; 723 } 724 725 if (is_read) { 726 if (host->id == 1) { 727 sync_dev = OMAP_DMA_MMC_RX; 728 dev_name = "MMC1 read"; 729 } else { 730 sync_dev = OMAP_DMA_MMC2_RX; 731 dev_name = "MMC2 read"; 732 } 733 } else { 734 if (host->id == 1) { 735 sync_dev = OMAP_DMA_MMC_TX; 736 dev_name = "MMC1 write"; 737 } else { 738 sync_dev = OMAP_DMA_MMC2_TX; 739 dev_name = "MMC2 write"; 740 } 741 } 742 r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb, 743 host, &dma_ch); 744 if (r != 0) { 745 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r); 746 return r; 747 } 748 host->dma_ch = dma_ch; 749 host->dma_is_read = is_read; 750 751 return 0; 752} 753 754static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req) 755{ 756 u16 reg; 757 758 reg = OMAP_MMC_READ(host, SDIO); 759 reg &= ~(1 << 5); 760 OMAP_MMC_WRITE(host, SDIO, reg); 761 /* Set maximum timeout */ 762 OMAP_MMC_WRITE(host, CTO, 0xff); 763} 764 765static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req) 766{ 767 int timeout; 768 u16 reg; 769 770 /* Convert ns to clock cycles by assuming 20MHz frequency 771 * 1 cycle at 20MHz = 500 ns 772 */ 773 timeout = req->data->timeout_clks + req->data->timeout_ns / 500; 774 775 /* Check if we need to use timeout multiplier register */ 776 reg = OMAP_MMC_READ(host, SDIO); 777 if (timeout > 0xffff) { 778 reg |= (1 << 5); 779 timeout /= 1024; 780 } else 781 reg &= ~(1 << 5); 782 OMAP_MMC_WRITE(host, SDIO, reg); 783 OMAP_MMC_WRITE(host, DTO, timeout); 784} 785 786static void 787mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) 788{ 789 struct mmc_data *data = req->data; 790 int i, use_dma, block_size; 791 unsigned sg_len; 792 793 host->data = data; 794 if (data == NULL) { 795 OMAP_MMC_WRITE(host, BLEN, 0); 796 OMAP_MMC_WRITE(host, NBLK, 0); 797 OMAP_MMC_WRITE(host, BUF, 0); 798 host->dma_in_use = 0; 799 set_cmd_timeout(host, req); 800 return; 801 } 802 803 block_size = data->blksz; 804 805 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1); 806 OMAP_MMC_WRITE(host, BLEN, block_size - 1); 807 set_data_timeout(host, req); 808 809 /* cope with calling layer confusion; it issues "single 810 * block" writes using multi-block scatterlists. 811 */ 812 sg_len = (data->blocks == 1) ? 1 : data->sg_len; 813 814 /* Only do DMA for entire blocks */ 815 use_dma = host->use_dma; 816 if (use_dma) { 817 for (i = 0; i < sg_len; i++) { 818 if ((data->sg[i].length % block_size) != 0) { 819 use_dma = 0; 820 break; 821 } 822 } 823 } 824 825 host->sg_idx = 0; 826 if (use_dma) { 827 if (mmc_omap_get_dma_channel(host, data) == 0) { 828 enum dma_data_direction dma_data_dir; 829 830 if (data->flags & MMC_DATA_WRITE) 831 dma_data_dir = DMA_TO_DEVICE; 832 else 833 dma_data_dir = DMA_FROM_DEVICE; 834 835 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 836 sg_len, dma_data_dir); 837 host->total_bytes_left = 0; 838 mmc_omap_prepare_dma(host, req->data); 839 host->brs_received = 0; 840 host->dma_done = 0; 841 host->dma_in_use = 1; 842 } else 843 use_dma = 0; 844 } 845 846 /* Revert to PIO? */ 847 if (!use_dma) { 848 OMAP_MMC_WRITE(host, BUF, 0x1f1f); 849 host->total_bytes_left = data->blocks * block_size; 850 host->sg_len = sg_len; 851 mmc_omap_sg_to_buf(host); 852 host->dma_in_use = 0; 853 } 854} 855 856static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req) 857{ 858 struct mmc_omap_host *host = mmc_priv(mmc); 859 860 WARN_ON(host->mrq != NULL); 861 862 host->mrq = req; 863 864 /* only touch fifo AFTER the controller readies it */ 865 mmc_omap_prepare_data(host, req); 866 mmc_omap_start_command(host, req->cmd); 867 if (host->dma_in_use) 868 omap_start_dma(host->dma_ch); 869} 870 871static void innovator_fpga_socket_power(int on) 872{ 873#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX) 874 if (on) { 875 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3), 876 OMAP1510_FPGA_POWER); 877 } else { 878 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3), 879 OMAP1510_FPGA_POWER); 880 } 881#endif 882} 883 884/* 885 * Turn the socket power on/off. Innovator uses FPGA, most boards 886 * probably use GPIO. 887 */ 888static void mmc_omap_power(struct mmc_omap_host *host, int on) 889{ 890 if (on) { 891 if (machine_is_omap_innovator()) 892 innovator_fpga_socket_power(1); 893 else if (machine_is_omap_h2()) 894 tps65010_set_gpio_out_value(GPIO3, HIGH); 895 else if (machine_is_omap_h3()) 896 /* GPIO 4 of TPS65010 sends SD_EN signal */ 897 tps65010_set_gpio_out_value(GPIO4, HIGH); 898 else if (cpu_is_omap24xx()) { 899 u16 reg = OMAP_MMC_READ(host, CON); 900 OMAP_MMC_WRITE(host, CON, reg | (1 << 11)); 901 } else 902 if (host->power_pin >= 0) 903 omap_set_gpio_dataout(host->power_pin, 1); 904 } else { 905 if (machine_is_omap_innovator()) 906 innovator_fpga_socket_power(0); 907 else if (machine_is_omap_h2()) 908 tps65010_set_gpio_out_value(GPIO3, LOW); 909 else if (machine_is_omap_h3()) 910 tps65010_set_gpio_out_value(GPIO4, LOW); 911 else if (cpu_is_omap24xx()) { 912 u16 reg = OMAP_MMC_READ(host, CON); 913 OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11)); 914 } else 915 if (host->power_pin >= 0) 916 omap_set_gpio_dataout(host->power_pin, 0); 917 } 918} 919 920static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios) 921{ 922 struct mmc_omap_host *host = mmc_priv(mmc); 923 int func_clk_rate = clk_get_rate(host->fclk); 924 int dsor; 925 926 if (ios->clock == 0) 927 return 0; 928 929 dsor = func_clk_rate / ios->clock; 930 if (dsor < 1) 931 dsor = 1; 932 933 if (func_clk_rate / dsor > ios->clock) 934 dsor++; 935 936 if (dsor > 250) 937 dsor = 250; 938 dsor++; 939 940 if (ios->bus_width == MMC_BUS_WIDTH_4) 941 dsor |= 1 << 15; 942 943 return dsor; 944} 945 946static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 947{ 948 struct mmc_omap_host *host = mmc_priv(mmc); 949 int dsor; 950 int i; 951 952 dsor = mmc_omap_calc_divisor(mmc, ios); 953 host->bus_mode = ios->bus_mode; 954 host->hw_bus_mode = host->bus_mode; 955 956 switch (ios->power_mode) { 957 case MMC_POWER_OFF: 958 mmc_omap_power(host, 0); 959 break; 960 case MMC_POWER_UP: 961 /* Cannot touch dsor yet, just power up MMC */ 962 mmc_omap_power(host, 1); 963 return; 964 case MMC_POWER_ON: 965 dsor |= 1 << 11; 966 break; 967 } 968 969 clk_enable(host->fclk); 970 971 /* On insanely high arm_per frequencies something sometimes 972 * goes somehow out of sync, and the POW bit is not being set, 973 * which results in the while loop below getting stuck. 974 * Writing to the CON register twice seems to do the trick. */ 975 for (i = 0; i < 2; i++) 976 OMAP_MMC_WRITE(host, CON, dsor); 977 if (ios->power_mode == MMC_POWER_ON) { 978 /* Send clock cycles, poll completion */ 979 OMAP_MMC_WRITE(host, IE, 0); 980 OMAP_MMC_WRITE(host, STAT, 0xffff); 981 OMAP_MMC_WRITE(host, CMD, 1 << 7); 982 while ((OMAP_MMC_READ(host, STAT) & 1) == 0); 983 OMAP_MMC_WRITE(host, STAT, 1); 984 } 985 clk_disable(host->fclk); 986} 987 988static int mmc_omap_get_ro(struct mmc_host *mmc) 989{ 990 struct mmc_omap_host *host = mmc_priv(mmc); 991 992 return host->wp_pin && omap_get_gpio_datain(host->wp_pin); 993} 994 995static const struct mmc_host_ops mmc_omap_ops = { 996 .request = mmc_omap_request, 997 .set_ios = mmc_omap_set_ios, 998 .get_ro = mmc_omap_get_ro, 999}; 1000 1001static int __init mmc_omap_probe(struct platform_device *pdev) 1002{ 1003 struct omap_mmc_conf *minfo = pdev->dev.platform_data; 1004 struct mmc_host *mmc; 1005 struct mmc_omap_host *host = NULL; 1006 struct resource *res; 1007 int ret = 0; 1008 int irq; 1009 1010 if (minfo == NULL) { 1011 dev_err(&pdev->dev, "platform data missing\n"); 1012 return -ENXIO; 1013 } 1014 1015 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1016 irq = platform_get_irq(pdev, 0); 1017 if (res == NULL || irq < 0) 1018 return -ENXIO; 1019 1020 res = request_mem_region(res->start, res->end - res->start + 1, 1021 pdev->name); 1022 if (res == NULL) 1023 return -EBUSY; 1024 1025 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev); 1026 if (mmc == NULL) { 1027 ret = -ENOMEM; 1028 goto err_free_mem_region; 1029 } 1030 1031 host = mmc_priv(mmc); 1032 host->mmc = mmc; 1033 1034 spin_lock_init(&host->dma_lock); 1035 init_timer(&host->dma_timer); 1036 host->dma_timer.function = mmc_omap_dma_timer; 1037 host->dma_timer.data = (unsigned long) host; 1038 1039 host->id = pdev->id; 1040 host->mem_res = res; 1041 host->irq = irq; 1042 1043 if (cpu_is_omap24xx()) { 1044 host->iclk = clk_get(&pdev->dev, "mmc_ick"); 1045 if (IS_ERR(host->iclk)) 1046 goto err_free_mmc_host; 1047 clk_enable(host->iclk); 1048 } 1049 1050 if (!cpu_is_omap24xx()) 1051 host->fclk = clk_get(&pdev->dev, "mmc_ck"); 1052 else 1053 host->fclk = clk_get(&pdev->dev, "mmc_fck"); 1054 1055 if (IS_ERR(host->fclk)) { 1056 ret = PTR_ERR(host->fclk); 1057 goto err_free_iclk; 1058 } 1059 1060 /* REVISIT: 1061 * Also, use minfo->cover to decide how to manage 1062 * the card detect sensing. 1063 */ 1064 host->power_pin = minfo->power_pin; 1065 host->switch_pin = minfo->switch_pin; 1066 host->wp_pin = minfo->wp_pin; 1067 host->use_dma = 1; 1068 host->dma_ch = -1; 1069 1070 host->irq = irq; 1071 host->phys_base = host->mem_res->start; 1072 host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base); 1073 1074 mmc->ops = &mmc_omap_ops; 1075 mmc->f_min = 400000; 1076 mmc->f_max = 24000000; 1077 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1078 mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK; 1079 1080 if (minfo->wire4) 1081 mmc->caps |= MMC_CAP_4_BIT_DATA; 1082 1083 /* Use scatterlist DMA to reduce per-transfer costs. 1084 * NOTE max_seg_size assumption that small blocks aren't 1085 * normally used (except e.g. for reading SD registers). 1086 */ 1087 mmc->max_phys_segs = 32; 1088 mmc->max_hw_segs = 32; 1089 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */ 1090 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */ 1091 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1092 mmc->max_seg_size = mmc->max_req_size; 1093 1094 if (host->power_pin >= 0) { 1095 if ((ret = omap_request_gpio(host->power_pin)) != 0) { 1096 dev_err(mmc_dev(host->mmc), 1097 "Unable to get GPIO pin for MMC power\n"); 1098 goto err_free_fclk; 1099 } 1100 omap_set_gpio_direction(host->power_pin, 0); 1101 } 1102 1103 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); 1104 if (ret) 1105 goto err_free_power_gpio; 1106 1107 host->dev = &pdev->dev; 1108 platform_set_drvdata(pdev, host); 1109 1110 if (host->switch_pin >= 0) { 1111 INIT_WORK(&host->switch_work, mmc_omap_switch_handler); 1112 init_timer(&host->switch_timer); 1113 host->switch_timer.function = mmc_omap_switch_timer; 1114 host->switch_timer.data = (unsigned long) host; 1115 if (omap_request_gpio(host->switch_pin) != 0) { 1116 dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n"); 1117 host->switch_pin = -1; 1118 goto no_switch; 1119 } 1120 1121 omap_set_gpio_direction(host->switch_pin, 1); 1122 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin), 1123 mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host); 1124 if (ret) { 1125 dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n"); 1126 omap_free_gpio(host->switch_pin); 1127 host->switch_pin = -1; 1128 goto no_switch; 1129 } 1130 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch); 1131 if (ret == 0) { 1132 ret = device_create_file(&pdev->dev, &dev_attr_enable_poll); 1133 if (ret != 0) 1134 device_remove_file(&pdev->dev, &dev_attr_cover_switch); 1135 } 1136 if (ret) { 1137 dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n"); 1138 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host); 1139 omap_free_gpio(host->switch_pin); 1140 host->switch_pin = -1; 1141 goto no_switch; 1142 } 1143 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host)) 1144 schedule_work(&host->switch_work); 1145 } 1146 1147 mmc_add_host(mmc); 1148 1149 return 0; 1150 1151no_switch: 1152 if (host) { 1153 if (host->iclk && !IS_ERR(host->iclk)) 1154 clk_put(host->iclk); 1155 if (host->fclk && !IS_ERR(host->fclk)) 1156 clk_put(host->fclk); 1157 mmc_free_host(host->mmc); 1158 } 1159err_free_power_gpio: 1160 if (host->power_pin >= 0) 1161 omap_free_gpio(host->power_pin); 1162err_free_fclk: 1163 clk_put(host->fclk); 1164err_free_iclk: 1165 if (host->iclk != NULL) { 1166 clk_disable(host->iclk); 1167 clk_put(host->iclk); 1168 } 1169err_free_mmc_host: 1170 mmc_free_host(host->mmc); 1171err_free_mem_region: 1172 release_mem_region(res->start, res->end - res->start + 1); 1173 return ret; 1174} 1175 1176static int mmc_omap_remove(struct platform_device *pdev) 1177{ 1178 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1179 1180 platform_set_drvdata(pdev, NULL); 1181 1182 BUG_ON(host == NULL); 1183 1184 mmc_remove_host(host->mmc); 1185 free_irq(host->irq, host); 1186 1187 if (host->power_pin >= 0) 1188 omap_free_gpio(host->power_pin); 1189 if (host->switch_pin >= 0) { 1190 device_remove_file(&pdev->dev, &dev_attr_enable_poll); 1191 device_remove_file(&pdev->dev, &dev_attr_cover_switch); 1192 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host); 1193 omap_free_gpio(host->switch_pin); 1194 host->switch_pin = -1; 1195 del_timer_sync(&host->switch_timer); 1196 flush_scheduled_work(); 1197 } 1198 if (host->iclk && !IS_ERR(host->iclk)) 1199 clk_put(host->iclk); 1200 if (host->fclk && !IS_ERR(host->fclk)) 1201 clk_put(host->fclk); 1202 1203 release_mem_region(pdev->resource[0].start, 1204 pdev->resource[0].end - pdev->resource[0].start + 1); 1205 1206 mmc_free_host(host->mmc); 1207 1208 return 0; 1209} 1210 1211#ifdef CONFIG_PM 1212static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg) 1213{ 1214 int ret = 0; 1215 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1216 1217 if (host && host->suspended) 1218 return 0; 1219 1220 if (host) { 1221 ret = mmc_suspend_host(host->mmc, mesg); 1222 if (ret == 0) 1223 host->suspended = 1; 1224 } 1225 return ret; 1226} 1227 1228static int mmc_omap_resume(struct platform_device *pdev) 1229{ 1230 int ret = 0; 1231 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1232 1233 if (host && !host->suspended) 1234 return 0; 1235 1236 if (host) { 1237 ret = mmc_resume_host(host->mmc); 1238 if (ret == 0) 1239 host->suspended = 0; 1240 } 1241 1242 return ret; 1243} 1244#else 1245#define mmc_omap_suspend NULL 1246#define mmc_omap_resume NULL 1247#endif 1248 1249static struct platform_driver mmc_omap_driver = { 1250 .probe = mmc_omap_probe, 1251 .remove = mmc_omap_remove, 1252 .suspend = mmc_omap_suspend, 1253 .resume = mmc_omap_resume, 1254 .driver = { 1255 .name = DRIVER_NAME, 1256 }, 1257}; 1258 1259static int __init mmc_omap_init(void) 1260{ 1261 return platform_driver_register(&mmc_omap_driver); 1262} 1263 1264static void __exit mmc_omap_exit(void) 1265{ 1266 platform_driver_unregister(&mmc_omap_driver); 1267} 1268 1269module_init(mmc_omap_init); 1270module_exit(mmc_omap_exit); 1271 1272MODULE_DESCRIPTION("OMAP Multimedia Card driver"); 1273MODULE_LICENSE("GPL"); 1274MODULE_ALIAS(DRIVER_NAME); 1275MODULE_AUTHOR("Juha Yrj�l�"); 1276