1/* 2 * linux/drivers/mmc/at91_mci.c - ATMEL AT91 MCI Driver 3 * 4 * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved 5 * 6 * Copyright (C) 2006 Malcolm Noyes 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13/* 14 This is the AT91 MCI driver that has been tested with both MMC cards 15 and SD-cards. Boards that support write protect are now supported. 16 The CCAT91SBC001 board does not support SD cards. 17 18 The three entry points are at91_mci_request, at91_mci_set_ios 19 and at91_mci_get_ro. 20 21 SET IOS 22 This configures the device to put it into the correct mode and clock speed 23 required. 24 25 MCI REQUEST 26 MCI request processes the commands sent in the mmc_request structure. This 27 can consist of a processing command and a stop command in the case of 28 multiple block transfers. 29 30 There are three main types of request, commands, reads and writes. 31 32 Commands are straight forward. The command is submitted to the controller and 33 the request function returns. When the controller generates an interrupt to indicate 34 the command is finished, the response to the command are read and the mmc_request_done 35 function called to end the request. 36 37 Reads and writes work in a similar manner to normal commands but involve the PDC (DMA) 38 controller to manage the transfers. 39 40 A read is done from the controller directly to the scatterlist passed in from the request. 41 Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte 42 swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug. 43 44 The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY 45 46 A write is slightly different in that the bytes to write are read from the scatterlist 47 into a dma memory buffer (this is in case the source buffer should be read only). The 48 entire write buffer is then done from this single dma memory buffer. 49 50 The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY 51 52 GET RO 53 Gets the status of the write protect pin, if available. 54*/ 55 56#include <linux/module.h> 57#include <linux/moduleparam.h> 58#include <linux/init.h> 59#include <linux/ioport.h> 60#include <linux/platform_device.h> 61#include <linux/interrupt.h> 62#include <linux/blkdev.h> 63#include <linux/delay.h> 64#include <linux/err.h> 65#include <linux/dma-mapping.h> 66#include <linux/clk.h> 67#include <linux/atmel_pdc.h> 68 69#include <linux/mmc/host.h> 70 71#include <asm/io.h> 72#include <asm/irq.h> 73#include <asm/mach/mmc.h> 74#include <asm/arch/board.h> 75#include <asm/arch/cpu.h> 76#include <asm/arch/gpio.h> 77#include <asm/arch/at91_mci.h> 78 79#define DRIVER_NAME "at91_mci" 80 81#undef SUPPORT_4WIRE 82 83#define FL_SENT_COMMAND (1 << 0) 84#define FL_SENT_STOP (1 << 1) 85 86#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ 87 | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ 88 | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) 89 90#define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg)) 91#define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg)) 92 93 94/* 95 * Low level type for this driver 96 */ 97struct at91mci_host 98{ 99 struct mmc_host *mmc; 100 struct mmc_command *cmd; 101 struct mmc_request *request; 102 103 void __iomem *baseaddr; 104 int irq; 105 106 struct at91_mmc_data *board; 107 int present; 108 109 struct clk *mci_clk; 110 111 /* 112 * Flag indicating when the command has been sent. This is used to 113 * work out whether or not to send the stop 114 */ 115 unsigned int flags; 116 /* flag for current bus settings */ 117 u32 bus_mode; 118 119 /* DMA buffer used for transmitting */ 120 unsigned int* buffer; 121 dma_addr_t physical_address; 122 unsigned int total_length; 123 124 /* Latest in the scatterlist that has been enabled for transfer, but not freed */ 125 int in_use_index; 126 127 /* Latest in the scatterlist that has been enabled for transfer */ 128 int transfer_index; 129}; 130 131/* 132 * Copy from sg to a dma block - used for transfers 133 */ 134static inline void at91mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data) 135{ 136 unsigned int len, i, size; 137 unsigned *dmabuf = host->buffer; 138 139 size = host->total_length; 140 len = data->sg_len; 141 142 /* 143 * Just loop through all entries. Size might not 144 * be the entire list though so make sure that 145 * we do not transfer too much. 146 */ 147 for (i = 0; i < len; i++) { 148 struct scatterlist *sg; 149 int amount; 150 unsigned int *sgbuffer; 151 152 sg = &data->sg[i]; 153 154 sgbuffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset; 155 amount = min(size, sg->length); 156 size -= amount; 157 158 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ 159 int index; 160 161 for (index = 0; index < (amount / 4); index++) 162 *dmabuf++ = swab32(sgbuffer[index]); 163 } 164 else 165 memcpy(dmabuf, sgbuffer, amount); 166 167 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ); 168 169 if (size == 0) 170 break; 171 } 172 173 /* 174 * Check that we didn't get a request to transfer 175 * more data than can fit into the SG list. 176 */ 177 BUG_ON(size != 0); 178} 179 180/* 181 * Prepare a dma read 182 */ 183static void at91mci_pre_dma_read(struct at91mci_host *host) 184{ 185 int i; 186 struct scatterlist *sg; 187 struct mmc_command *cmd; 188 struct mmc_data *data; 189 190 pr_debug("pre dma read\n"); 191 192 cmd = host->cmd; 193 if (!cmd) { 194 pr_debug("no command\n"); 195 return; 196 } 197 198 data = cmd->data; 199 if (!data) { 200 pr_debug("no data\n"); 201 return; 202 } 203 204 for (i = 0; i < 2; i++) { 205 /* nothing left to transfer */ 206 if (host->transfer_index >= data->sg_len) { 207 pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index); 208 break; 209 } 210 211 /* Check to see if this needs filling */ 212 if (i == 0) { 213 if (at91_mci_read(host, ATMEL_PDC_RCR) != 0) { 214 pr_debug("Transfer active in current\n"); 215 continue; 216 } 217 } 218 else { 219 if (at91_mci_read(host, ATMEL_PDC_RNCR) != 0) { 220 pr_debug("Transfer active in next\n"); 221 continue; 222 } 223 } 224 225 /* Setup the next transfer */ 226 pr_debug("Using transfer index %d\n", host->transfer_index); 227 228 sg = &data->sg[host->transfer_index++]; 229 pr_debug("sg = %p\n", sg); 230 231 sg->dma_address = dma_map_page(NULL, sg->page, sg->offset, sg->length, DMA_FROM_DEVICE); 232 233 pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length); 234 235 if (i == 0) { 236 at91_mci_write(host, ATMEL_PDC_RPR, sg->dma_address); 237 at91_mci_write(host, ATMEL_PDC_RCR, sg->length / 4); 238 } 239 else { 240 at91_mci_write(host, ATMEL_PDC_RNPR, sg->dma_address); 241 at91_mci_write(host, ATMEL_PDC_RNCR, sg->length / 4); 242 } 243 } 244 245 pr_debug("pre dma read done\n"); 246} 247 248/* 249 * Handle after a dma read 250 */ 251static void at91mci_post_dma_read(struct at91mci_host *host) 252{ 253 struct mmc_command *cmd; 254 struct mmc_data *data; 255 256 pr_debug("post dma read\n"); 257 258 cmd = host->cmd; 259 if (!cmd) { 260 pr_debug("no command\n"); 261 return; 262 } 263 264 data = cmd->data; 265 if (!data) { 266 pr_debug("no data\n"); 267 return; 268 } 269 270 while (host->in_use_index < host->transfer_index) { 271 unsigned int *buffer; 272 273 struct scatterlist *sg; 274 275 pr_debug("finishing index %d\n", host->in_use_index); 276 277 sg = &data->sg[host->in_use_index++]; 278 279 pr_debug("Unmapping page %08X\n", sg->dma_address); 280 281 dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE); 282 283 /* Swap the contents of the buffer */ 284 buffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset; 285 pr_debug("buffer = %p, length = %d\n", buffer, sg->length); 286 287 data->bytes_xfered += sg->length; 288 289 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ 290 int index; 291 292 for (index = 0; index < (sg->length / 4); index++) 293 buffer[index] = swab32(buffer[index]); 294 } 295 296 kunmap_atomic(buffer, KM_BIO_SRC_IRQ); 297 flush_dcache_page(sg->page); 298 } 299 300 /* Is there another transfer to trigger? */ 301 if (host->transfer_index < data->sg_len) 302 at91mci_pre_dma_read(host); 303 else { 304 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF); 305 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 306 } 307 308 pr_debug("post dma read done\n"); 309} 310 311/* 312 * Handle transmitted data 313 */ 314static void at91_mci_handle_transmitted(struct at91mci_host *host) 315{ 316 struct mmc_command *cmd; 317 struct mmc_data *data; 318 319 pr_debug("Handling the transmit\n"); 320 321 /* Disable the transfer */ 322 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 323 324 /* Now wait for cmd ready */ 325 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE); 326 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); 327 328 cmd = host->cmd; 329 if (!cmd) return; 330 331 data = cmd->data; 332 if (!data) return; 333 334 data->bytes_xfered = host->total_length; 335} 336 337/* 338 * Enable the controller 339 */ 340static void at91_mci_enable(struct at91mci_host *host) 341{ 342 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); 343 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); 344 at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); 345 at91_mci_write(host, AT91_MCI_MR, AT91_MCI_PDCMODE | 0x34a); 346 347 /* use Slot A or B (only one at same time) */ 348 at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b); 349} 350 351/* 352 * Disable the controller 353 */ 354static void at91_mci_disable(struct at91mci_host *host) 355{ 356 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); 357} 358 359/* 360 * Send a command 361 * return the interrupts to enable 362 */ 363static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd) 364{ 365 unsigned int cmdr, mr; 366 unsigned int block_length; 367 struct mmc_data *data = cmd->data; 368 369 unsigned int blocks; 370 unsigned int ier = 0; 371 372 host->cmd = cmd; 373 374 /* Not sure if this is needed */ 375 cmdr = cmd->opcode; 376 377 if (mmc_resp_type(cmd) == MMC_RSP_NONE) 378 cmdr |= AT91_MCI_RSPTYP_NONE; 379 else { 380 /* if a response is expected then allow maximum response latancy */ 381 cmdr |= AT91_MCI_MAXLAT; 382 /* set 136 bit response for R2, 48 bit response otherwise */ 383 if (mmc_resp_type(cmd) == MMC_RSP_R2) 384 cmdr |= AT91_MCI_RSPTYP_136; 385 else 386 cmdr |= AT91_MCI_RSPTYP_48; 387 } 388 389 if (data) { 390 block_length = data->blksz; 391 blocks = data->blocks; 392 393 /* always set data start - also set direction flag for read */ 394 if (data->flags & MMC_DATA_READ) 395 cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); 396 else if (data->flags & MMC_DATA_WRITE) 397 cmdr |= AT91_MCI_TRCMD_START; 398 399 if (data->flags & MMC_DATA_STREAM) 400 cmdr |= AT91_MCI_TRTYP_STREAM; 401 if (data->flags & MMC_DATA_MULTI) 402 cmdr |= AT91_MCI_TRTYP_MULTIPLE; 403 } 404 else { 405 block_length = 0; 406 blocks = 0; 407 } 408 409 if (host->flags & FL_SENT_STOP) 410 cmdr |= AT91_MCI_TRCMD_STOP; 411 412 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) 413 cmdr |= AT91_MCI_OPDCMD; 414 415 /* 416 * Set the arguments and send the command 417 */ 418 pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", 419 cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR)); 420 421 if (!data) { 422 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS); 423 at91_mci_write(host, ATMEL_PDC_RPR, 0); 424 at91_mci_write(host, ATMEL_PDC_RCR, 0); 425 at91_mci_write(host, ATMEL_PDC_RNPR, 0); 426 at91_mci_write(host, ATMEL_PDC_RNCR, 0); 427 at91_mci_write(host, ATMEL_PDC_TPR, 0); 428 at91_mci_write(host, ATMEL_PDC_TCR, 0); 429 at91_mci_write(host, ATMEL_PDC_TNPR, 0); 430 at91_mci_write(host, ATMEL_PDC_TNCR, 0); 431 432 at91_mci_write(host, AT91_MCI_ARGR, cmd->arg); 433 at91_mci_write(host, AT91_MCI_CMDR, cmdr); 434 return AT91_MCI_CMDRDY; 435 } 436 437 mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; /* zero block length and PDC mode */ 438 at91_mci_write(host, AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE); 439 440 /* 441 * Disable the PDC controller 442 */ 443 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 444 445 if (cmdr & AT91_MCI_TRCMD_START) { 446 data->bytes_xfered = 0; 447 host->transfer_index = 0; 448 host->in_use_index = 0; 449 if (cmdr & AT91_MCI_TRDIR) { 450 /* 451 * Handle a read 452 */ 453 host->buffer = NULL; 454 host->total_length = 0; 455 456 at91mci_pre_dma_read(host); 457 ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; 458 } 459 else { 460 /* 461 * Handle a write 462 */ 463 host->total_length = block_length * blocks; 464 host->buffer = dma_alloc_coherent(NULL, 465 host->total_length, 466 &host->physical_address, GFP_KERNEL); 467 468 at91mci_sg_to_dma(host, data); 469 470 pr_debug("Transmitting %d bytes\n", host->total_length); 471 472 at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address); 473 at91_mci_write(host, ATMEL_PDC_TCR, host->total_length / 4); 474 ier = AT91_MCI_TXBUFE; 475 } 476 } 477 478 /* 479 * Send the command and then enable the PDC - not the other way round as 480 * the data sheet says 481 */ 482 483 at91_mci_write(host, AT91_MCI_ARGR, cmd->arg); 484 at91_mci_write(host, AT91_MCI_CMDR, cmdr); 485 486 if (cmdr & AT91_MCI_TRCMD_START) { 487 if (cmdr & AT91_MCI_TRDIR) 488 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 489 else 490 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 491 } 492 return ier; 493} 494 495/* 496 * Wait for a command to complete 497 */ 498static void at91mci_process_command(struct at91mci_host *host, struct mmc_command *cmd) 499{ 500 unsigned int ier; 501 502 ier = at91_mci_send_command(host, cmd); 503 504 pr_debug("setting ier to %08X\n", ier); 505 506 /* Stop on errors or the required value */ 507 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier); 508} 509 510/* 511 * Process the next step in the request 512 */ 513static void at91mci_process_next(struct at91mci_host *host) 514{ 515 if (!(host->flags & FL_SENT_COMMAND)) { 516 host->flags |= FL_SENT_COMMAND; 517 at91mci_process_command(host, host->request->cmd); 518 } 519 else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) { 520 host->flags |= FL_SENT_STOP; 521 at91mci_process_command(host, host->request->stop); 522 } 523 else 524 mmc_request_done(host->mmc, host->request); 525} 526 527/* 528 * Handle a command that has been completed 529 */ 530static void at91mci_completed_command(struct at91mci_host *host) 531{ 532 struct mmc_command *cmd = host->cmd; 533 unsigned int status; 534 535 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); 536 537 cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0)); 538 cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1)); 539 cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2)); 540 cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3)); 541 542 if (host->buffer) { 543 dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address); 544 host->buffer = NULL; 545 } 546 547 status = at91_mci_read(host, AT91_MCI_SR); 548 549 pr_debug("Status = %08X [%08X %08X %08X %08X]\n", 550 status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); 551 552 if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE | 553 AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE | 554 AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)) { 555 if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) { 556 cmd->error = MMC_ERR_NONE; 557 } 558 else { 559 if (status & (AT91_MCI_RTOE | AT91_MCI_DTOE)) 560 cmd->error = MMC_ERR_TIMEOUT; 561 else if (status & (AT91_MCI_RCRCE | AT91_MCI_DCRCE)) 562 cmd->error = MMC_ERR_BADCRC; 563 else if (status & (AT91_MCI_OVRE | AT91_MCI_UNRE)) 564 cmd->error = MMC_ERR_FIFO; 565 else 566 cmd->error = MMC_ERR_FAILED; 567 568 pr_debug("Error detected and set to %d (cmd = %d, retries = %d)\n", 569 cmd->error, cmd->opcode, cmd->retries); 570 } 571 } 572 else 573 cmd->error = MMC_ERR_NONE; 574 575 at91mci_process_next(host); 576} 577 578/* 579 * Handle an MMC request 580 */ 581static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 582{ 583 struct at91mci_host *host = mmc_priv(mmc); 584 host->request = mrq; 585 host->flags = 0; 586 587 at91mci_process_next(host); 588} 589 590/* 591 * Set the IOS 592 */ 593static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 594{ 595 int clkdiv; 596 struct at91mci_host *host = mmc_priv(mmc); 597 unsigned long at91_master_clock = clk_get_rate(host->mci_clk); 598 599 host->bus_mode = ios->bus_mode; 600 601 if (ios->clock == 0) { 602 /* Disable the MCI controller */ 603 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS); 604 clkdiv = 0; 605 } 606 else { 607 /* Enable the MCI controller */ 608 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); 609 610 if ((at91_master_clock % (ios->clock * 2)) == 0) 611 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; 612 else 613 clkdiv = (at91_master_clock / ios->clock) / 2; 614 615 pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv, 616 at91_master_clock / (2 * (clkdiv + 1))); 617 } 618 if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) { 619 pr_debug("MMC: Setting controller bus width to 4\n"); 620 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS); 621 } 622 else { 623 pr_debug("MMC: Setting controller bus width to 1\n"); 624 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); 625 } 626 627 /* Set the clock divider */ 628 at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); 629 630 /* maybe switch power to the card */ 631 if (host->board->vcc_pin) { 632 switch (ios->power_mode) { 633 case MMC_POWER_OFF: 634 at91_set_gpio_value(host->board->vcc_pin, 0); 635 break; 636 case MMC_POWER_UP: 637 case MMC_POWER_ON: 638 at91_set_gpio_value(host->board->vcc_pin, 1); 639 break; 640 } 641 } 642} 643 644/* 645 * Handle an interrupt 646 */ 647static irqreturn_t at91_mci_irq(int irq, void *devid) 648{ 649 struct at91mci_host *host = devid; 650 int completed = 0; 651 unsigned int int_status, int_mask; 652 653 int_status = at91_mci_read(host, AT91_MCI_SR); 654 int_mask = at91_mci_read(host, AT91_MCI_IMR); 655 656 pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, 657 int_status & int_mask); 658 659 int_status = int_status & int_mask; 660 661 if (int_status & AT91_MCI_ERRORS) { 662 completed = 1; 663 664 if (int_status & AT91_MCI_UNRE) 665 pr_debug("MMC: Underrun error\n"); 666 if (int_status & AT91_MCI_OVRE) 667 pr_debug("MMC: Overrun error\n"); 668 if (int_status & AT91_MCI_DTOE) 669 pr_debug("MMC: Data timeout\n"); 670 if (int_status & AT91_MCI_DCRCE) 671 pr_debug("MMC: CRC error in data\n"); 672 if (int_status & AT91_MCI_RTOE) 673 pr_debug("MMC: Response timeout\n"); 674 if (int_status & AT91_MCI_RENDE) 675 pr_debug("MMC: Response end bit error\n"); 676 if (int_status & AT91_MCI_RCRCE) 677 pr_debug("MMC: Response CRC error\n"); 678 if (int_status & AT91_MCI_RDIRE) 679 pr_debug("MMC: Response direction error\n"); 680 if (int_status & AT91_MCI_RINDE) 681 pr_debug("MMC: Response index error\n"); 682 } else { 683 /* Only continue processing if no errors */ 684 685 if (int_status & AT91_MCI_TXBUFE) { 686 pr_debug("TX buffer empty\n"); 687 at91_mci_handle_transmitted(host); 688 } 689 690 if (int_status & AT91_MCI_RXBUFF) { 691 pr_debug("RX buffer full\n"); 692 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY); 693 } 694 695 if (int_status & AT91_MCI_ENDTX) 696 pr_debug("Transmit has ended\n"); 697 698 if (int_status & AT91_MCI_ENDRX) { 699 pr_debug("Receive has ended\n"); 700 at91mci_post_dma_read(host); 701 } 702 703 if (int_status & AT91_MCI_NOTBUSY) { 704 pr_debug("Card is ready\n"); 705 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY); 706 } 707 708 if (int_status & AT91_MCI_DTIP) 709 pr_debug("Data transfer in progress\n"); 710 711 if (int_status & AT91_MCI_BLKE) 712 pr_debug("Block transfer has ended\n"); 713 714 if (int_status & AT91_MCI_TXRDY) 715 pr_debug("Ready to transmit\n"); 716 717 if (int_status & AT91_MCI_RXRDY) 718 pr_debug("Ready to receive\n"); 719 720 if (int_status & AT91_MCI_CMDRDY) { 721 pr_debug("Command ready\n"); 722 completed = 1; 723 } 724 } 725 726 if (completed) { 727 pr_debug("Completed command\n"); 728 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); 729 at91mci_completed_command(host); 730 } else 731 at91_mci_write(host, AT91_MCI_IDR, int_status); 732 733 return IRQ_HANDLED; 734} 735 736static irqreturn_t at91_mmc_det_irq(int irq, void *_host) 737{ 738 struct at91mci_host *host = _host; 739 int present = !at91_get_gpio_value(irq); 740 741 /* 742 * we expect this irq on both insert and remove, 743 * and use a short delay to debounce. 744 */ 745 if (present != host->present) { 746 host->present = present; 747 pr_debug("%s: card %s\n", mmc_hostname(host->mmc), 748 present ? "insert" : "remove"); 749 if (!present) { 750 pr_debug("****** Resetting SD-card bus width ******\n"); 751 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); 752 } 753 mmc_detect_change(host->mmc, msecs_to_jiffies(100)); 754 } 755 return IRQ_HANDLED; 756} 757 758static int at91_mci_get_ro(struct mmc_host *mmc) 759{ 760 int read_only = 0; 761 struct at91mci_host *host = mmc_priv(mmc); 762 763 if (host->board->wp_pin) { 764 read_only = at91_get_gpio_value(host->board->wp_pin); 765 printk(KERN_WARNING "%s: card is %s\n", mmc_hostname(mmc), 766 (read_only ? "read-only" : "read-write") ); 767 } 768 else { 769 printk(KERN_WARNING "%s: host does not support reading read-only " 770 "switch. Assuming write-enable.\n", mmc_hostname(mmc)); 771 } 772 return read_only; 773} 774 775static const struct mmc_host_ops at91_mci_ops = { 776 .request = at91_mci_request, 777 .set_ios = at91_mci_set_ios, 778 .get_ro = at91_mci_get_ro, 779}; 780 781/* 782 * Probe for the device 783 */ 784static int __init at91_mci_probe(struct platform_device *pdev) 785{ 786 struct mmc_host *mmc; 787 struct at91mci_host *host; 788 struct resource *res; 789 int ret; 790 791 pr_debug("Probe MCI devices\n"); 792 793 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 794 if (!res) 795 return -ENXIO; 796 797 if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME)) 798 return -EBUSY; 799 800 mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); 801 if (!mmc) { 802 pr_debug("Failed to allocate mmc host\n"); 803 release_mem_region(res->start, res->end - res->start + 1); 804 return -ENOMEM; 805 } 806 807 mmc->ops = &at91_mci_ops; 808 mmc->f_min = 375000; 809 mmc->f_max = 25000000; 810 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 811 mmc->caps = MMC_CAP_BYTEBLOCK; 812 813 mmc->max_blk_size = 4095; 814 mmc->max_blk_count = mmc->max_req_size; 815 816 host = mmc_priv(mmc); 817 host->mmc = mmc; 818 host->buffer = NULL; 819 host->bus_mode = 0; 820 host->board = pdev->dev.platform_data; 821 if (host->board->wire4) { 822#ifdef SUPPORT_4WIRE 823 mmc->caps |= MMC_CAP_4_BIT_DATA; 824#else 825 printk("AT91 MMC: 4 wire bus mode not supported by this driver - using 1 wire\n"); 826#endif 827 } 828 829 /* 830 * Get Clock 831 */ 832 host->mci_clk = clk_get(&pdev->dev, "mci_clk"); 833 if (IS_ERR(host->mci_clk)) { 834 printk(KERN_ERR "AT91 MMC: no clock defined.\n"); 835 mmc_free_host(mmc); 836 release_mem_region(res->start, res->end - res->start + 1); 837 return -ENODEV; 838 } 839 840 /* 841 * Map I/O region 842 */ 843 host->baseaddr = ioremap(res->start, res->end - res->start + 1); 844 if (!host->baseaddr) { 845 clk_put(host->mci_clk); 846 mmc_free_host(mmc); 847 release_mem_region(res->start, res->end - res->start + 1); 848 return -ENOMEM; 849 } 850 851 /* 852 * Reset hardware 853 */ 854 clk_enable(host->mci_clk); /* Enable the peripheral clock */ 855 at91_mci_disable(host); 856 at91_mci_enable(host); 857 858 /* 859 * Allocate the MCI interrupt 860 */ 861 host->irq = platform_get_irq(pdev, 0); 862 ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED, DRIVER_NAME, host); 863 if (ret) { 864 printk(KERN_ERR "AT91 MMC: Failed to request MCI interrupt\n"); 865 clk_disable(host->mci_clk); 866 clk_put(host->mci_clk); 867 mmc_free_host(mmc); 868 iounmap(host->baseaddr); 869 release_mem_region(res->start, res->end - res->start + 1); 870 return ret; 871 } 872 873 platform_set_drvdata(pdev, mmc); 874 875 /* 876 * Add host to MMC layer 877 */ 878 if (host->board->det_pin) 879 host->present = !at91_get_gpio_value(host->board->det_pin); 880 else 881 host->present = -1; 882 883 mmc_add_host(mmc); 884 885 /* 886 * monitor card insertion/removal if we can 887 */ 888 if (host->board->det_pin) { 889 ret = request_irq(host->board->det_pin, at91_mmc_det_irq, 890 0, DRIVER_NAME, host); 891 if (ret) 892 printk(KERN_ERR "AT91 MMC: Couldn't allocate MMC detect irq\n"); 893 } 894 895 pr_debug("Added MCI driver\n"); 896 897 return 0; 898} 899 900/* 901 * Remove a device 902 */ 903static int __exit at91_mci_remove(struct platform_device *pdev) 904{ 905 struct mmc_host *mmc = platform_get_drvdata(pdev); 906 struct at91mci_host *host; 907 struct resource *res; 908 909 if (!mmc) 910 return -1; 911 912 host = mmc_priv(mmc); 913 914 if (host->present != -1) { 915 free_irq(host->board->det_pin, host); 916 cancel_delayed_work(&host->mmc->detect); 917 } 918 919 at91_mci_disable(host); 920 mmc_remove_host(mmc); 921 free_irq(host->irq, host); 922 923 clk_disable(host->mci_clk); /* Disable the peripheral clock */ 924 clk_put(host->mci_clk); 925 926 iounmap(host->baseaddr); 927 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 928 release_mem_region(res->start, res->end - res->start + 1); 929 930 mmc_free_host(mmc); 931 platform_set_drvdata(pdev, NULL); 932 pr_debug("MCI Removed\n"); 933 934 return 0; 935} 936 937#ifdef CONFIG_PM 938static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state) 939{ 940 struct mmc_host *mmc = platform_get_drvdata(pdev); 941 int ret = 0; 942 943 if (mmc) 944 ret = mmc_suspend_host(mmc, state); 945 946 return ret; 947} 948 949static int at91_mci_resume(struct platform_device *pdev) 950{ 951 struct mmc_host *mmc = platform_get_drvdata(pdev); 952 int ret = 0; 953 954 if (mmc) 955 ret = mmc_resume_host(mmc); 956 957 return ret; 958} 959#else 960#define at91_mci_suspend NULL 961#define at91_mci_resume NULL 962#endif 963 964static struct platform_driver at91_mci_driver = { 965 .remove = __exit_p(at91_mci_remove), 966 .suspend = at91_mci_suspend, 967 .resume = at91_mci_resume, 968 .driver = { 969 .name = DRIVER_NAME, 970 .owner = THIS_MODULE, 971 }, 972}; 973 974static int __init at91_mci_init(void) 975{ 976 return platform_driver_probe(&at91_mci_driver, at91_mci_probe); 977} 978 979static void __exit at91_mci_exit(void) 980{ 981 platform_driver_unregister(&at91_mci_driver); 982} 983 984module_init(at91_mci_init); 985module_exit(at91_mci_exit); 986 987MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver"); 988MODULE_AUTHOR("Nick Randell"); 989MODULE_LICENSE("GPL"); 990