1/* 2 3 cx88x-hw.h - CX2388x register offsets 4 5 Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de) 6 2001 Michael Eskin 7 2002 Yurij Sysoev <yurij@naturesoft.net> 8 2003 Gerd Knorr <kraxel@bytesex.org> 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23*/ 24 25#ifndef _CX88_REG_H_ 26#define _CX88_REG_H_ 27 28/* ---------------------------------------------------------------------- */ 29/* PCI IDs and config space */ 30 31#ifndef PCI_VENDOR_ID_CONEXANT 32# define PCI_VENDOR_ID_CONEXANT 0x14F1 33#endif 34#ifndef PCI_DEVICE_ID_CX2300_VID 35# define PCI_DEVICE_ID_CX2300_VID 0x8800 36#endif 37 38#define CX88X_DEVCTRL 0x40 39#define CX88X_EN_TBFX 0x02 40#define CX88X_EN_VSFX 0x04 41 42/* ---------------------------------------------------------------------- */ 43/* PCI controller registers */ 44 45/* Command and Status Register */ 46#define F0_CMD_STAT_MM 0x2f0004 47#define F1_CMD_STAT_MM 0x2f0104 48#define F2_CMD_STAT_MM 0x2f0204 49#define F3_CMD_STAT_MM 0x2f0304 50#define F4_CMD_STAT_MM 0x2f0404 51 52/* Device Control #1 */ 53#define F0_DEV_CNTRL1_MM 0x2f0040 54#define F1_DEV_CNTRL1_MM 0x2f0140 55#define F2_DEV_CNTRL1_MM 0x2f0240 56#define F3_DEV_CNTRL1_MM 0x2f0340 57#define F4_DEV_CNTRL1_MM 0x2f0440 58 59/* Device Control #1 */ 60#define F0_BAR0_MM 0x2f0010 61#define F1_BAR0_MM 0x2f0110 62#define F2_BAR0_MM 0x2f0210 63#define F3_BAR0_MM 0x2f0310 64#define F4_BAR0_MM 0x2f0410 65 66/* ---------------------------------------------------------------------- */ 67/* DMA Controller registers */ 68 69#define MO_PDMA_STHRSH 0x200000 // Source threshold 70#define MO_PDMA_STADRS 0x200004 // Source target address 71#define MO_PDMA_SIADRS 0x200008 // Source internal address 72#define MO_PDMA_SCNTRL 0x20000C // Source control 73#define MO_PDMA_DTHRSH 0x200010 // Destination threshold 74#define MO_PDMA_DTADRS 0x200014 // Destination target address 75#define MO_PDMA_DIADRS 0x200018 // Destination internal address 76#define MO_PDMA_DCNTRL 0x20001C // Destination control 77#define MO_LD_SSID 0x200030 // Load subsystem ID 78#define MO_DEV_CNTRL2 0x200034 // Device control 79#define MO_PCI_INTMSK 0x200040 // PCI interrupt mask 80#define MO_PCI_INTSTAT 0x200044 // PCI interrupt status 81#define MO_PCI_INTMSTAT 0x200048 // PCI interrupt masked status 82#define MO_VID_INTMSK 0x200050 // Video interrupt mask 83#define MO_VID_INTSTAT 0x200054 // Video interrupt status 84#define MO_VID_INTMSTAT 0x200058 // Video interrupt masked status 85#define MO_VID_INTSSTAT 0x20005C // Video interrupt set status 86#define MO_AUD_INTMSK 0x200060 // Audio interrupt mask 87#define MO_AUD_INTSTAT 0x200064 // Audio interrupt status 88#define MO_AUD_INTMSTAT 0x200068 // Audio interrupt masked status 89#define MO_AUD_INTSSTAT 0x20006C // Audio interrupt set status 90#define MO_TS_INTMSK 0x200070 // Transport stream interrupt mask 91#define MO_TS_INTSTAT 0x200074 // Transport stream interrupt status 92#define MO_TS_INTMSTAT 0x200078 // Transport stream interrupt mask status 93#define MO_TS_INTSSTAT 0x20007C // Transport stream interrupt set status 94#define MO_VIP_INTMSK 0x200080 // VIP interrupt mask 95#define MO_VIP_INTSTAT 0x200084 // VIP interrupt status 96#define MO_VIP_INTMSTAT 0x200088 // VIP interrupt masked status 97#define MO_VIP_INTSSTAT 0x20008C // VIP interrupt set status 98#define MO_GPHST_INTMSK 0x200090 // Host interrupt mask 99#define MO_GPHST_INTSTAT 0x200094 // Host interrupt status 100#define MO_GPHST_INTMSTAT 0x200098 // Host interrupt masked status 101#define MO_GPHST_INTSSTAT 0x20009C // Host interrupt set status 102 103// DMA Channels 1-6 belong to SPIPE 104#define MO_DMA7_PTR1 0x300018 // {24}RW* DMA Current Ptr : Ch#7 105#define MO_DMA8_PTR1 0x30001C // {24}RW* DMA Current Ptr : Ch#8 106 107// DMA Channels 9-20 belong to SPIPE 108#define MO_DMA21_PTR1 0x300080 // {24}R0* DMA Current Ptr : Ch#21 109#define MO_DMA22_PTR1 0x300084 // {24}R0* DMA Current Ptr : Ch#22 110#define MO_DMA23_PTR1 0x300088 // {24}R0* DMA Current Ptr : Ch#23 111#define MO_DMA24_PTR1 0x30008C // {24}R0* DMA Current Ptr : Ch#24 112#define MO_DMA25_PTR1 0x300090 // {24}R0* DMA Current Ptr : Ch#25 113#define MO_DMA26_PTR1 0x300094 // {24}R0* DMA Current Ptr : Ch#26 114#define MO_DMA27_PTR1 0x300098 // {24}R0* DMA Current Ptr : Ch#27 115#define MO_DMA28_PTR1 0x30009C // {24}R0* DMA Current Ptr : Ch#28 116#define MO_DMA29_PTR1 0x3000A0 // {24}R0* DMA Current Ptr : Ch#29 117#define MO_DMA30_PTR1 0x3000A4 // {24}R0* DMA Current Ptr : Ch#30 118#define MO_DMA31_PTR1 0x3000A8 // {24}R0* DMA Current Ptr : Ch#31 119#define MO_DMA32_PTR1 0x3000AC // {24}R0* DMA Current Ptr : Ch#32 120 121#define MO_DMA21_PTR2 0x3000C0 // {24}RW* DMA Tab Ptr : Ch#21 122#define MO_DMA22_PTR2 0x3000C4 // {24}RW* DMA Tab Ptr : Ch#22 123#define MO_DMA23_PTR2 0x3000C8 // {24}RW* DMA Tab Ptr : Ch#23 124#define MO_DMA24_PTR2 0x3000CC // {24}RW* DMA Tab Ptr : Ch#24 125#define MO_DMA25_PTR2 0x3000D0 // {24}RW* DMA Tab Ptr : Ch#25 126#define MO_DMA26_PTR2 0x3000D4 // {24}RW* DMA Tab Ptr : Ch#26 127#define MO_DMA27_PTR2 0x3000D8 // {24}RW* DMA Tab Ptr : Ch#27 128#define MO_DMA28_PTR2 0x3000DC // {24}RW* DMA Tab Ptr : Ch#28 129#define MO_DMA29_PTR2 0x3000E0 // {24}RW* DMA Tab Ptr : Ch#29 130#define MO_DMA30_PTR2 0x3000E4 // {24}RW* DMA Tab Ptr : Ch#30 131#define MO_DMA31_PTR2 0x3000E8 // {24}RW* DMA Tab Ptr : Ch#31 132#define MO_DMA32_PTR2 0x3000EC // {24}RW* DMA Tab Ptr : Ch#32 133 134#define MO_DMA21_CNT1 0x300100 // {11}RW* DMA Buffer Size : Ch#21 135#define MO_DMA22_CNT1 0x300104 // {11}RW* DMA Buffer Size : Ch#22 136#define MO_DMA23_CNT1 0x300108 // {11}RW* DMA Buffer Size : Ch#23 137#define MO_DMA24_CNT1 0x30010C // {11}RW* DMA Buffer Size : Ch#24 138#define MO_DMA25_CNT1 0x300110 // {11}RW* DMA Buffer Size : Ch#25 139#define MO_DMA26_CNT1 0x300114 // {11}RW* DMA Buffer Size : Ch#26 140#define MO_DMA27_CNT1 0x300118 // {11}RW* DMA Buffer Size : Ch#27 141#define MO_DMA28_CNT1 0x30011C // {11}RW* DMA Buffer Size : Ch#28 142#define MO_DMA29_CNT1 0x300120 // {11}RW* DMA Buffer Size : Ch#29 143#define MO_DMA30_CNT1 0x300124 // {11}RW* DMA Buffer Size : Ch#30 144#define MO_DMA31_CNT1 0x300128 // {11}RW* DMA Buffer Size : Ch#31 145#define MO_DMA32_CNT1 0x30012C // {11}RW* DMA Buffer Size : Ch#32 146 147#define MO_DMA21_CNT2 0x300140 // {11}RW* DMA Table Size : Ch#21 148#define MO_DMA22_CNT2 0x300144 // {11}RW* DMA Table Size : Ch#22 149#define MO_DMA23_CNT2 0x300148 // {11}RW* DMA Table Size : Ch#23 150#define MO_DMA24_CNT2 0x30014C // {11}RW* DMA Table Size : Ch#24 151#define MO_DMA25_CNT2 0x300150 // {11}RW* DMA Table Size : Ch#25 152#define MO_DMA26_CNT2 0x300154 // {11}RW* DMA Table Size : Ch#26 153#define MO_DMA27_CNT2 0x300158 // {11}RW* DMA Table Size : Ch#27 154#define MO_DMA28_CNT2 0x30015C // {11}RW* DMA Table Size : Ch#28 155#define MO_DMA29_CNT2 0x300160 // {11}RW* DMA Table Size : Ch#29 156#define MO_DMA30_CNT2 0x300164 // {11}RW* DMA Table Size : Ch#30 157#define MO_DMA31_CNT2 0x300168 // {11}RW* DMA Table Size : Ch#31 158#define MO_DMA32_CNT2 0x30016C // {11}RW* DMA Table Size : Ch#32 159 160 161/* ---------------------------------------------------------------------- */ 162/* Video registers */ 163 164#define MO_VIDY_DMA 0x310000 // {64}RWp Video Y 165#define MO_VIDU_DMA 0x310008 // {64}RWp Video U 166#define MO_VIDV_DMA 0x310010 // {64}RWp Video V 167#define MO_VBI_DMA 0x310018 // {64}RWp VBI (Vertical blanking interval) 168 169#define MO_DEVICE_STATUS 0x310100 170#define MO_INPUT_FORMAT 0x310104 171#define MO_AGC_BURST 0x31010c 172#define MO_CONTR_BRIGHT 0x310110 173#define MO_UV_SATURATION 0x310114 174#define MO_HUE 0x310118 175#define MO_HTOTAL 0x310120 176#define MO_HDELAY_EVEN 0x310124 177#define MO_HDELAY_ODD 0x310128 178#define MO_VDELAY_ODD 0x31012c 179#define MO_VDELAY_EVEN 0x310130 180#define MO_HACTIVE_EVEN 0x31013c 181#define MO_HACTIVE_ODD 0x310140 182#define MO_VACTIVE_EVEN 0x310144 183#define MO_VACTIVE_ODD 0x310148 184#define MO_HSCALE_EVEN 0x31014c 185#define MO_HSCALE_ODD 0x310150 186#define MO_VSCALE_EVEN 0x310154 187#define MO_FILTER_EVEN 0x31015c 188#define MO_VSCALE_ODD 0x310158 189#define MO_FILTER_ODD 0x310160 190#define MO_OUTPUT_FORMAT 0x310164 191 192#define MO_PLL_REG 0x310168 // PLL register 193#define MO_PLL_ADJ_CTRL 0x31016c // PLL adjust control register 194#define MO_SCONV_REG 0x310170 // sample rate conversion register 195#define MO_SCONV_FIFO 0x310174 // sample rate conversion fifo 196#define MO_SUB_STEP 0x310178 // subcarrier step size 197#define MO_SUB_STEP_DR 0x31017c // subcarrier step size for DR line 198 199#define MO_CAPTURE_CTRL 0x310180 // capture control 200#define MO_COLOR_CTRL 0x310184 201#define MO_VBI_PACKET 0x310188 // vbi packet size / delay 202#define MO_FIELD_COUNT 0x310190 // field counter 203#define MO_VIP_CONFIG 0x310194 204#define MO_VBOS_CONTROL 0x3101a8 205 206#define MO_AGC_BACK_VBI 0x310200 207#define MO_AGC_SYNC_TIP1 0x310208 208 209#define MO_VIDY_GPCNT 0x31C020 // {16}RO Video Y general purpose counter 210#define MO_VIDU_GPCNT 0x31C024 // {16}RO Video U general purpose counter 211#define MO_VIDV_GPCNT 0x31C028 // {16}RO Video V general purpose counter 212#define MO_VBI_GPCNT 0x31C02C // {16}RO VBI general purpose counter 213#define MO_VIDY_GPCNTRL 0x31C030 // {2}WO Video Y general purpose control 214#define MO_VIDU_GPCNTRL 0x31C034 // {2}WO Video U general purpose control 215#define MO_VIDV_GPCNTRL 0x31C038 // {2}WO Video V general purpose control 216#define MO_VBI_GPCNTRL 0x31C03C // {2}WO VBI general purpose counter 217#define MO_VID_DMACNTRL 0x31C040 // {8}RW Video DMA control 218#define MO_VID_XFR_STAT 0x31C044 // {1}RO Video transfer status 219 220 221/* ---------------------------------------------------------------------- */ 222/* audio registers */ 223 224#define MO_AUDD_DMA 0x320000 // {64}RWp Audio downstream 225#define MO_AUDU_DMA 0x320008 // {64}RWp Audio upstream 226#define MO_AUDR_DMA 0x320010 // {64}RWp Audio RDS (downstream) 227#define MO_AUDD_GPCNT 0x32C020 // {16}RO Audio down general purpose counter 228#define MO_AUDU_GPCNT 0x32C024 // {16}RO Audio up general purpose counter 229#define MO_AUDR_GPCNT 0x32C028 // {16}RO Audio RDS general purpose counter 230#define MO_AUDD_GPCNTRL 0x32C030 // {2}WO Audio down general purpose control 231#define MO_AUDU_GPCNTRL 0x32C034 // {2}WO Audio up general purpose control 232#define MO_AUDR_GPCNTRL 0x32C038 // {2}WO Audio RDS general purpose control 233#define MO_AUD_DMACNTRL 0x32C040 // {6}RW Audio DMA control 234#define MO_AUD_XFR_STAT 0x32C044 // {1}RO Audio transfer status 235#define MO_AUDD_LNGTH 0x32C048 // {12}RW Audio down line length 236#define MO_AUDR_LNGTH 0x32C04C // {12}RW Audio RDS line length 237 238#define AUD_INIT 0x320100 239#define AUD_INIT_LD 0x320104 240#define AUD_SOFT_RESET 0x320108 241#define AUD_I2SINPUTCNTL 0x320120 242#define AUD_BAUDRATE 0x320124 243#define AUD_I2SOUTPUTCNTL 0x320128 244#define AAGC_HYST 0x320134 245#define AAGC_GAIN 0x320138 246#define AAGC_DEF 0x32013c 247#define AUD_IIR1_0_SEL 0x320150 248#define AUD_IIR1_0_SHIFT 0x320154 249#define AUD_IIR1_1_SEL 0x320158 250#define AUD_IIR1_1_SHIFT 0x32015c 251#define AUD_IIR1_2_SEL 0x320160 252#define AUD_IIR1_2_SHIFT 0x320164 253#define AUD_IIR1_3_SEL 0x320168 254#define AUD_IIR1_3_SHIFT 0x32016c 255#define AUD_IIR1_4_SEL 0x320170 256#define AUD_IIR1_4_SHIFT 0x32017c 257#define AUD_IIR1_5_SEL 0x320180 258#define AUD_IIR1_5_SHIFT 0x320184 259#define AUD_IIR2_0_SEL 0x320190 260#define AUD_IIR2_0_SHIFT 0x320194 261#define AUD_IIR2_1_SEL 0x320198 262#define AUD_IIR2_1_SHIFT 0x32019c 263#define AUD_IIR2_2_SEL 0x3201a0 264#define AUD_IIR2_2_SHIFT 0x3201a4 265#define AUD_IIR2_3_SEL 0x3201a8 266#define AUD_IIR2_3_SHIFT 0x3201ac 267#define AUD_IIR3_0_SEL 0x3201c0 268#define AUD_IIR3_0_SHIFT 0x3201c4 269#define AUD_IIR3_1_SEL 0x3201c8 270#define AUD_IIR3_1_SHIFT 0x3201cc 271#define AUD_IIR3_2_SEL 0x3201d0 272#define AUD_IIR3_2_SHIFT 0x3201d4 273#define AUD_IIR4_0_SEL 0x3201e0 274#define AUD_IIR4_0_SHIFT 0x3201e4 275#define AUD_IIR4_1_SEL 0x3201e8 276#define AUD_IIR4_1_SHIFT 0x3201ec 277#define AUD_IIR4_2_SEL 0x3201f0 278#define AUD_IIR4_2_SHIFT 0x3201f4 279#define AUD_IIR4_0_CA0 0x320200 280#define AUD_IIR4_0_CA1 0x320204 281#define AUD_IIR4_0_CA2 0x320208 282#define AUD_IIR4_0_CB0 0x32020c 283#define AUD_IIR4_0_CB1 0x320210 284#define AUD_IIR4_1_CA0 0x320214 285#define AUD_IIR4_1_CA1 0x320218 286#define AUD_IIR4_1_CA2 0x32021c 287#define AUD_IIR4_1_CB0 0x320220 288#define AUD_IIR4_1_CB1 0x320224 289#define AUD_IIR4_2_CA0 0x320228 290#define AUD_IIR4_2_CA1 0x32022c 291#define AUD_IIR4_2_CA2 0x320230 292#define AUD_IIR4_2_CB0 0x320234 293#define AUD_IIR4_2_CB1 0x320238 294#define AUD_HP_MD_IIR4_1 0x320250 295#define AUD_HP_PROG_IIR4_1 0x320254 296#define AUD_FM_MODE_ENABLE 0x320258 297#define AUD_POLY0_DDS_CONSTANT 0x320270 298#define AUD_DN0_FREQ 0x320274 299#define AUD_DN1_FREQ 0x320278 300#define AUD_DN1_FREQ_SHIFT 0x32027c 301#define AUD_DN1_AFC 0x320280 302#define AUD_DN1_SRC_SEL 0x320284 303#define AUD_DN1_SHFT 0x320288 304#define AUD_DN2_FREQ 0x32028c 305#define AUD_DN2_FREQ_SHIFT 0x320290 306#define AUD_DN2_AFC 0x320294 307#define AUD_DN2_SRC_SEL 0x320298 308#define AUD_DN2_SHFT 0x32029c 309#define AUD_CRDC0_SRC_SEL 0x320300 310#define AUD_CRDC0_SHIFT 0x320304 311#define AUD_CORDIC_SHIFT_0 0x320308 312#define AUD_CRDC1_SRC_SEL 0x32030c 313#define AUD_CRDC1_SHIFT 0x320310 314#define AUD_CORDIC_SHIFT_1 0x320314 315#define AUD_DCOC_0_SRC 0x320320 316#define AUD_DCOC0_SHIFT 0x320324 317#define AUD_DCOC_0_SHIFT_IN0 0x320328 318#define AUD_DCOC_0_SHIFT_IN1 0x32032c 319#define AUD_DCOC_1_SRC 0x320330 320#define AUD_DCOC1_SHIFT 0x320334 321#define AUD_DCOC_1_SHIFT_IN0 0x320338 322#define AUD_DCOC_1_SHIFT_IN1 0x32033c 323#define AUD_DCOC_2_SRC 0x320340 324#define AUD_DCOC2_SHIFT 0x320344 325#define AUD_DCOC_2_SHIFT_IN0 0x320348 326#define AUD_DCOC_2_SHIFT_IN1 0x32034c 327#define AUD_DCOC_PASS_IN 0x320350 328#define AUD_PDET_SRC 0x320370 329#define AUD_PDET_SHIFT 0x320374 330#define AUD_PILOT_BQD_1_K0 0x320380 331#define AUD_PILOT_BQD_1_K1 0x320384 332#define AUD_PILOT_BQD_1_K2 0x320388 333#define AUD_PILOT_BQD_1_K3 0x32038c 334#define AUD_PILOT_BQD_1_K4 0x320390 335#define AUD_PILOT_BQD_2_K0 0x320394 336#define AUD_PILOT_BQD_2_K1 0x320398 337#define AUD_PILOT_BQD_2_K2 0x32039c 338#define AUD_PILOT_BQD_2_K3 0x3203a0 339#define AUD_PILOT_BQD_2_K4 0x3203a4 340#define AUD_THR_FR 0x3203c0 341#define AUD_X_PROG 0x3203c4 342#define AUD_Y_PROG 0x3203c8 343#define AUD_HARMONIC_MULT 0x3203cc 344#define AUD_C1_UP_THR 0x3203d0 345#define AUD_C1_LO_THR 0x3203d4 346#define AUD_C2_UP_THR 0x3203d8 347#define AUD_C2_LO_THR 0x3203dc 348#define AUD_PLL_EN 0x320400 349#define AUD_PLL_SRC 0x320404 350#define AUD_PLL_SHIFT 0x320408 351#define AUD_PLL_IF_SEL 0x32040c 352#define AUD_PLL_IF_SHIFT 0x320410 353#define AUD_BIQUAD_PLL_K0 0x320414 354#define AUD_BIQUAD_PLL_K1 0x320418 355#define AUD_BIQUAD_PLL_K2 0x32041c 356#define AUD_BIQUAD_PLL_K3 0x320420 357#define AUD_BIQUAD_PLL_K4 0x320424 358#define AUD_DEEMPH0_SRC_SEL 0x320440 359#define AUD_DEEMPH0_SHIFT 0x320444 360#define AUD_DEEMPH0_G0 0x320448 361#define AUD_DEEMPH0_A0 0x32044c 362#define AUD_DEEMPH0_B0 0x320450 363#define AUD_DEEMPH0_A1 0x320454 364#define AUD_DEEMPH0_B1 0x320458 365#define AUD_DEEMPH1_SRC_SEL 0x32045c 366#define AUD_DEEMPH1_SHIFT 0x320460 367#define AUD_DEEMPH1_G0 0x320464 368#define AUD_DEEMPH1_A0 0x320468 369#define AUD_DEEMPH1_B0 0x32046c 370#define AUD_DEEMPH1_A1 0x320470 371#define AUD_DEEMPH1_B1 0x320474 372#define AUD_OUT0_SEL 0x320490 373#define AUD_OUT0_SHIFT 0x320494 374#define AUD_OUT1_SEL 0x320498 375#define AUD_OUT1_SHIFT 0x32049c 376#define AUD_RDSI_SEL 0x3204a0 377#define AUD_RDSI_SHIFT 0x3204a4 378#define AUD_RDSQ_SEL 0x3204a8 379#define AUD_RDSQ_SHIFT 0x3204ac 380#define AUD_DBX_IN_GAIN 0x320500 381#define AUD_DBX_WBE_GAIN 0x320504 382#define AUD_DBX_SE_GAIN 0x320508 383#define AUD_DBX_RMS_WBE 0x32050c 384#define AUD_DBX_RMS_SE 0x320510 385#define AUD_DBX_SE_BYPASS 0x320514 386#define AUD_FAWDETCTL 0x320530 387#define AUD_FAWDETWINCTL 0x320534 388#define AUD_DEEMPHGAIN_R 0x320538 389#define AUD_DEEMPHNUMER1_R 0x32053c 390#define AUD_DEEMPHNUMER2_R 0x320540 391#define AUD_DEEMPHDENOM1_R 0x320544 392#define AUD_DEEMPHDENOM2_R 0x320548 393#define AUD_ERRLOGPERIOD_R 0x32054c 394#define AUD_ERRINTRPTTHSHLD1_R 0x320550 395#define AUD_ERRINTRPTTHSHLD2_R 0x320554 396#define AUD_ERRINTRPTTHSHLD3_R 0x320558 397#define AUD_NICAM_STATUS1 0x32055c 398#define AUD_NICAM_STATUS2 0x320560 399#define AUD_ERRLOG1 0x320564 400#define AUD_ERRLOG2 0x320568 401#define AUD_ERRLOG3 0x32056c 402#define AUD_DAC_BYPASS_L 0x320580 403#define AUD_DAC_BYPASS_R 0x320584 404#define AUD_DAC_BYPASS_CTL 0x320588 405#define AUD_CTL 0x32058c 406#define AUD_STATUS 0x320590 407#define AUD_VOL_CTL 0x320594 408#define AUD_BAL_CTL 0x320598 409#define AUD_START_TIMER 0x3205b0 410#define AUD_MODE_CHG_TIMER 0x3205b4 411#define AUD_POLYPH80SCALEFAC 0x3205b8 412#define AUD_DMD_RA_DDS 0x3205bc 413#define AUD_I2S_RA_DDS 0x3205c0 414#define AUD_RATE_THRES_DMD 0x3205d0 415#define AUD_RATE_THRES_I2S 0x3205d4 416#define AUD_RATE_ADJ1 0x3205d8 417#define AUD_RATE_ADJ2 0x3205dc 418#define AUD_RATE_ADJ3 0x3205e0 419#define AUD_RATE_ADJ4 0x3205e4 420#define AUD_RATE_ADJ5 0x3205e8 421#define AUD_APB_IN_RATE_ADJ 0x3205ec 422#define AUD_I2SCNTL 0x3205ec 423#define AUD_PHASE_FIX_CTL 0x3205f0 424#define AUD_PLL_PRESCALE 0x320600 425#define AUD_PLL_DDS 0x320604 426#define AUD_PLL_INT 0x320608 427#define AUD_PLL_FRAC 0x32060c 428#define AUD_PLL_JTAG 0x320620 429#define AUD_PLL_SPMP 0x320624 430#define AUD_AFE_12DB_EN 0x320628 431 432// Audio QAM Register Addresses 433#define AUD_PDF_DDS_CNST_BYTE2 0x320d01 434#define AUD_PDF_DDS_CNST_BYTE1 0x320d02 435#define AUD_PDF_DDS_CNST_BYTE0 0x320d03 436#define AUD_PHACC_FREQ_8MSB 0x320d2a 437#define AUD_PHACC_FREQ_8LSB 0x320d2b 438#define AUD_QAM_MODE 0x320d04 439 440 441/* ---------------------------------------------------------------------- */ 442/* transport stream registers */ 443 444#define MO_TS_DMA 0x330000 // {64}RWp Transport stream downstream 445#define MO_TS_GPCNT 0x33C020 // {16}RO TS general purpose counter 446#define MO_TS_GPCNTRL 0x33C030 // {2}WO TS general purpose control 447#define MO_TS_DMACNTRL 0x33C040 // {6}RW TS DMA control 448#define MO_TS_XFR_STAT 0x33C044 // {1}RO TS transfer status 449#define MO_TS_LNGTH 0x33C048 // {12}RW TS line length 450 451#define TS_HW_SOP_CNTRL 0x33C04C 452#define TS_GEN_CNTRL 0x33C050 453#define TS_BD_PKT_STAT 0x33C054 454#define TS_SOP_STAT 0x33C058 455#define TS_FIFO_OVFL_STAT 0x33C05C 456#define TS_VALERR_CNTRL 0x33C060 457 458 459/* ---------------------------------------------------------------------- */ 460/* VIP registers */ 461 462#define MO_VIPD_DMA 0x340000 // {64}RWp VIP downstream 463#define MO_VIPU_DMA 0x340008 // {64}RWp VIP upstream 464#define MO_VIPD_GPCNT 0x34C020 // {16}RO VIP down general purpose counter 465#define MO_VIPU_GPCNT 0x34C024 // {16}RO VIP up general purpose counter 466#define MO_VIPD_GPCNTRL 0x34C030 // {2}WO VIP down general purpose control 467#define MO_VIPU_GPCNTRL 0x34C034 // {2}WO VIP up general purpose control 468#define MO_VIP_DMACNTRL 0x34C040 // {6}RW VIP DMA control 469#define MO_VIP_XFR_STAT 0x34C044 // {1}RO VIP transfer status 470#define MO_VIP_CFG 0x340048 // VIP configuration 471#define MO_VIPU_CNTRL 0x34004C // VIP upstream control #1 472#define MO_VIPD_CNTRL 0x340050 // VIP downstream control #2 473#define MO_VIPD_LNGTH 0x340054 // VIP downstream line length 474#define MO_VIP_BRSTLN 0x340058 // VIP burst length 475#define MO_VIP_INTCNTRL 0x34C05C // VIP Interrupt Control 476#define MO_VIP_XFTERM 0x340060 // VIP transfer terminate 477 478 479/* ---------------------------------------------------------------------- */ 480/* misc registers */ 481 482#define MO_M2M_DMA 0x350000 // {64}RWp Mem2Mem DMA Bfr 483#define MO_GP0_IO 0x350010 // {32}RW* GPIOoutput enablesdata I/O 484#define MO_GP1_IO 0x350014 // {32}RW* GPIOoutput enablesdata I/O 485#define MO_GP2_IO 0x350018 // {32}RW* GPIOoutput enablesdata I/O 486#define MO_GP3_IO 0x35001C // {32}RW* GPIO Mode/Ctrloutput enables 487#define MO_GPIO 0x350020 // {32}RW* GPIO I2C Ctrldata I/O 488#define MO_GPOE 0x350024 // {32}RW GPIO I2C Ctrloutput enables 489#define MO_GP_ISM 0x350028 // {16}WO GPIO Intr Sens/Pol 490 491#define MO_PLL_B 0x35C008 // {32}RW* PLL Control for ASB bus clks 492#define MO_M2M_CNT 0x35C024 // {32}RW Mem2Mem DMA Cnt 493#define MO_M2M_XSUM 0x35C028 // {32}RO M2M XOR-Checksum 494#define MO_CRC 0x35C02C // {16}RW CRC16 init/result 495#define MO_CRC_D 0x35C030 // {32}WO CRC16 new data in 496#define MO_TM_CNT_LDW 0x35C034 // {32}RO Timer : Counter low dword 497#define MO_TM_CNT_UW 0x35C038 // {16}RO Timer : Counter high word 498#define MO_TM_LMT_LDW 0x35C03C // {32}RW Timer : Limit low dword 499#define MO_TM_LMT_UW 0x35C040 // {32}RW Timer : Limit high word 500#define MO_PINMUX_IO 0x35C044 // {8}RW Pin Mux Control 501#define MO_TSTSEL_IO 0x35C048 // {2}RW Pin Mux Control 502#define MO_AFECFG_IO 0x35C04C // AFE configuration reg 503#define MO_DDS_IO 0x35C050 // DDS Increment reg 504#define MO_DDSCFG_IO 0x35C054 // DDS Configuration reg 505#define MO_SAMPLE_IO 0x35C058 // IRIn sample reg 506#define MO_SRST_IO 0x35C05C // Output system reset reg 507 508#define MO_INT1_MSK 0x35C060 // DMA RISC interrupt mask 509#define MO_INT1_STAT 0x35C064 // DMA RISC interrupt status 510#define MO_INT1_MSTAT 0x35C068 // DMA RISC interrupt masked status 511 512 513/* ---------------------------------------------------------------------- */ 514/* i2c bus registers */ 515 516#define MO_I2C 0x368000 // I2C data/control 517#define MO_I2C_DIV (0xf<<4) 518#define MO_I2C_SYNC (1<<3) 519#define MO_I2C_W3B (1<<2) 520#define MO_I2C_SCL (1<<1) 521#define MO_I2C_SDA (1<<0) 522 523 524/* ---------------------------------------------------------------------- */ 525/* general purpose host registers */ 526 527#define MO_GPHSTD_DMA 0x350000 // {64}RWp Host downstream 528#define MO_GPHSTU_DMA 0x350008 // {64}RWp Host upstream 529#define MO_GPHSTU_CNTRL 0x380048 // Host upstream control #1 530#define MO_GPHSTD_CNTRL 0x38004C // Host downstream control #2 531#define MO_GPHSTD_LNGTH 0x380050 // Host downstream line length 532#define MO_GPHST_WSC 0x380054 // Host wait state control 533#define MO_GPHST_XFR 0x380058 // Host transfer control 534#define MO_GPHST_WDTH 0x38005C // Host interface width 535#define MO_GPHST_HDSHK 0x380060 // Host peripheral handshake 536#define MO_GPHST_MUX16 0x380064 // Host muxed 16-bit transfer parameters 537#define MO_GPHST_MODE 0x380068 // Host mode select 538 539#define MO_GPHSTD_GPCNT 0x35C020 // Host down general purpose counter 540#define MO_GPHSTU_GPCNT 0x35C024 // Host up general purpose counter 541#define MO_GPHSTD_GPCNTRL 0x38C030 // Host down general purpose control 542#define MO_GPHSTU_GPCNTRL 0x38C034 // Host up general purpose control 543#define MO_GPHST_DMACNTRL 0x38C040 // Host DMA control 544#define MO_GPHST_XFR_STAT 0x38C044 // Host transfer status 545#define MO_GPHST_SOFT_RST 0x38C06C // Host software reset 546 547 548/* ---------------------------------------------------------------------- */ 549/* RISC instructions */ 550 551#define RISC_SYNC 0x80000000 552#define RISC_SYNC_ODD 0x80000000 553#define RISC_SYNC_EVEN 0x80000200 554#define RISC_RESYNC 0x80008000 555#define RISC_RESYNC_ODD 0x80008000 556#define RISC_RESYNC_EVEN 0x80008200 557#define RISC_WRITE 0x10000000 558#define RISC_WRITEC 0x50000000 559#define RISC_READ 0x90000000 560#define RISC_READC 0xA0000000 561#define RISC_JUMP 0x70000000 562#define RISC_SKIP 0x20000000 563#define RISC_WRITERM 0xB0000000 564#define RISC_WRITECM 0xC0000000 565#define RISC_WRITECR 0xD0000000 566#define RISC_IMM 0x00000001 567 568#define RISC_SOL 0x08000000 569#define RISC_EOL 0x04000000 570 571#define RISC_IRQ2 0x02000000 572#define RISC_IRQ1 0x01000000 573 574#define RISC_CNT_NONE 0x00000000 575#define RISC_CNT_INC 0x00010000 576#define RISC_CNT_RSVR 0x00020000 577#define RISC_CNT_RESET 0x00030000 578#define RISC_JMP_SRP 0x01 579 580 581/* ---------------------------------------------------------------------- */ 582/* various constants */ 583 584#define SEL_BTSC 0x01 585#define SEL_EIAJ 0x02 586#define SEL_A2 0x04 587#define SEL_SAP 0x08 588#define SEL_NICAM 0x10 589#define SEL_FMRADIO 0x20 590 591// AUD_CTL 592#define EN_BTSC_FORCE_MONO 0 593#define EN_BTSC_FORCE_STEREO 1 594#define EN_BTSC_FORCE_SAP 2 595#define EN_BTSC_AUTO_STEREO 3 596#define EN_BTSC_AUTO_SAP 4 597 598#define EN_A2_FORCE_MONO1 8 599#define EN_A2_FORCE_MONO2 9 600#define EN_A2_FORCE_STEREO 10 601#define EN_A2_AUTO_MONO2 11 602#define EN_A2_AUTO_STEREO 12 603 604#define EN_EIAJ_FORCE_MONO1 16 605#define EN_EIAJ_FORCE_MONO2 17 606#define EN_EIAJ_FORCE_STEREO 18 607#define EN_EIAJ_AUTO_MONO2 19 608#define EN_EIAJ_AUTO_STEREO 20 609 610#define EN_NICAM_FORCE_MONO1 32 611#define EN_NICAM_FORCE_MONO2 33 612#define EN_NICAM_FORCE_STEREO 34 613#define EN_NICAM_AUTO_MONO2 35 614#define EN_NICAM_AUTO_STEREO 36 615 616#define EN_FMRADIO_FORCE_MONO 24 617#define EN_FMRADIO_FORCE_STEREO 25 618#define EN_FMRADIO_AUTO_STEREO 26 619 620#define EN_NICAM_AUTO_FALLBACK 0x00000040 621#define EN_FMRADIO_EN_RDS 0x00000200 622#define EN_NICAM_TRY_AGAIN_BIT 0x00000400 623#define EN_DAC_ENABLE 0x00001000 624#define EN_I2SOUT_ENABLE 0x00002000 625#define EN_I2SIN_STR2DAC 0x00004000 626#define EN_I2SIN_ENABLE 0x00008000 627 628#define EN_DMTRX_SUMDIFF (0 << 7) 629#define EN_DMTRX_SUMR (1 << 7) 630#define EN_DMTRX_LR (2 << 7) 631#define EN_DMTRX_MONO (3 << 7) 632#define EN_DMTRX_BYPASS (1 << 11) 633 634// Video 635#define VID_CAPTURE_CONTROL 0x310180 636 637#define CX23880_CAP_CTL_CAPTURE_VBI_ODD (1<<3) 638#define CX23880_CAP_CTL_CAPTURE_VBI_EVEN (1<<2) 639#define CX23880_CAP_CTL_CAPTURE_ODD (1<<1) 640#define CX23880_CAP_CTL_CAPTURE_EVEN (1<<0) 641 642#define VideoInputMux0 0x0 643#define VideoInputMux1 0x1 644#define VideoInputMux2 0x2 645#define VideoInputMux3 0x3 646#define VideoInputTuner 0x0 647#define VideoInputComposite 0x1 648#define VideoInputSVideo 0x2 649#define VideoInputOther 0x3 650 651#define Xtal0 0x1 652#define Xtal1 0x2 653#define XtalAuto 0x3 654 655#define VideoFormatAuto 0x0 656#define VideoFormatNTSC 0x1 657#define VideoFormatNTSCJapan 0x2 658#define VideoFormatNTSC443 0x3 659#define VideoFormatPAL 0x4 660#define VideoFormatPALB 0x4 661#define VideoFormatPALD 0x4 662#define VideoFormatPALG 0x4 663#define VideoFormatPALH 0x4 664#define VideoFormatPALI 0x4 665#define VideoFormatPALBDGHI 0x4 666#define VideoFormatPALM 0x5 667#define VideoFormatPALN 0x6 668#define VideoFormatPALNC 0x7 669#define VideoFormatPAL60 0x8 670#define VideoFormatSECAM 0x9 671 672#define VideoFormatAuto27MHz 0x10 673#define VideoFormatNTSC27MHz 0x11 674#define VideoFormatNTSCJapan27MHz 0x12 675#define VideoFormatNTSC44327MHz 0x13 676#define VideoFormatPAL27MHz 0x14 677#define VideoFormatPALB27MHz 0x14 678#define VideoFormatPALD27MHz 0x14 679#define VideoFormatPALG27MHz 0x14 680#define VideoFormatPALH27MHz 0x14 681#define VideoFormatPALI27MHz 0x14 682#define VideoFormatPALBDGHI27MHz 0x14 683#define VideoFormatPALM27MHz 0x15 684#define VideoFormatPALN27MHz 0x16 685#define VideoFormatPALNC27MHz 0x17 686#define VideoFormatPAL6027MHz 0x18 687#define VideoFormatSECAM27MHz 0x19 688 689#define NominalUSECAM 0x87 690#define NominalVSECAM 0x85 691#define NominalUNTSC 0xFE 692#define NominalVNTSC 0xB4 693 694#define NominalContrast 0xD8 695 696#define HFilterAutoFormat 0x0 697#define HFilterCIF 0x1 698#define HFilterQCIF 0x2 699#define HFilterICON 0x3 700 701#define VFilter2TapInterpolate 0 702#define VFilter3TapInterpolate 1 703#define VFilter4TapInterpolate 2 704#define VFilter5TapInterpolate 3 705#define VFilter2TapNoInterpolate 4 706#define VFilter3TapNoInterpolate 5 707#define VFilter4TapNoInterpolate 6 708#define VFilter5TapNoInterpolate 7 709 710#define ColorFormatRGB32 0x0000 711#define ColorFormatRGB24 0x0011 712#define ColorFormatRGB16 0x0022 713#define ColorFormatRGB15 0x0033 714#define ColorFormatYUY2 0x0044 715#define ColorFormatBTYUV 0x0055 716#define ColorFormatY8 0x0066 717#define ColorFormatRGB8 0x0077 718#define ColorFormatPL422 0x0088 719#define ColorFormatPL411 0x0099 720#define ColorFormatYUV12 0x00AA 721#define ColorFormatYUV9 0x00BB 722#define ColorFormatRAW 0x00EE 723#define ColorFormatBSWAP 0x0300 724#define ColorFormatWSWAP 0x0c00 725#define ColorFormatEvenMask 0x050f 726#define ColorFormatOddMask 0x0af0 727#define ColorFormatGamma 0x1000 728 729#define Interlaced 0x1 730#define NonInterlaced 0x0 731 732#define FieldEven 0x1 733#define FieldOdd 0x0 734 735#define TGReadWriteMode 0x0 736#define TGEnableMode 0x1 737 738#define DV_CbAlign 0x0 739#define DV_Y0Align 0x1 740#define DV_CrAlign 0x2 741#define DV_Y1Align 0x3 742 743#define DVF_Analog 0x0 744#define DVF_CCIR656 0x1 745#define DVF_ByteStream 0x2 746#define DVF_ExtVSYNC 0x4 747#define DVF_ExtField 0x5 748 749#define CHANNEL_VID_Y 0x1 750#define CHANNEL_VID_U 0x2 751#define CHANNEL_VID_V 0x3 752#define CHANNEL_VID_VBI 0x4 753#define CHANNEL_AUD_DN 0x5 754#define CHANNEL_AUD_UP 0x6 755#define CHANNEL_AUD_RDS_DN 0x7 756#define CHANNEL_MPEG_DN 0x8 757#define CHANNEL_VIP_DN 0x9 758#define CHANNEL_VIP_UP 0xA 759#define CHANNEL_HOST_DN 0xB 760#define CHANNEL_HOST_UP 0xC 761#define CHANNEL_FIRST 0x1 762#define CHANNEL_LAST 0xC 763 764#define GP_COUNT_CONTROL_NONE 0x0 765#define GP_COUNT_CONTROL_INC 0x1 766#define GP_COUNT_CONTROL_RESERVED 0x2 767#define GP_COUNT_CONTROL_RESET 0x3 768 769#define PLL_PRESCALE_BY_2 2 770#define PLL_PRESCALE_BY_3 3 771#define PLL_PRESCALE_BY_4 4 772#define PLL_PRESCALE_BY_5 5 773 774#define HLNotchFilter4xFsc 0 775#define HLNotchFilterSquare 1 776#define HLNotchFilter135NTSC 2 777#define HLNotchFilter135PAL 3 778 779#define NTSC_8x_SUB_CARRIER 28.63636E6 780#define PAL_8x_SUB_CARRIER 35.46895E6 781 782// Default analog settings 783#define DEFAULT_HUE_NTSC 0x00 784#define DEFAULT_BRIGHTNESS_NTSC 0x00 785#define DEFAULT_CONTRAST_NTSC 0x39 786#define DEFAULT_SAT_U_NTSC 0x7F 787#define DEFAULT_SAT_V_NTSC 0x5A 788 789typedef enum 790{ 791 SOURCE_TUNER = 0, 792 SOURCE_COMPOSITE, 793 SOURCE_SVIDEO, 794 SOURCE_OTHER1, 795 SOURCE_OTHER2, 796 SOURCE_COMPVIASVIDEO, 797 SOURCE_CCIR656 798} VIDEOSOURCETYPE; 799 800#endif /* _CX88_REG_H_ */ 801