1#include <media/saa7146_vv.h> 2 3static int vbi_pixel_to_capture = 720 * 2; 4 5static int vbi_workaround(struct saa7146_dev *dev) 6{ 7 struct saa7146_vv *vv = dev->vv_data; 8 9 u32 *cpu; 10 dma_addr_t dma_addr; 11 12 int count = 0; 13 int i; 14 15 DECLARE_WAITQUEUE(wait, current); 16 17 DEB_VBI(("dev:%p\n",dev)); 18 19 20 cpu = pci_alloc_consistent(dev->pci, 4096, &dma_addr); 21 if (NULL == cpu) 22 return -ENOMEM; 23 24 saa7146_write(dev, BASE_EVEN3, dma_addr); 25 saa7146_write(dev, BASE_ODD3, dma_addr+vbi_pixel_to_capture); 26 saa7146_write(dev, PROT_ADDR3, dma_addr+4096); 27 saa7146_write(dev, PITCH3, vbi_pixel_to_capture); 28 saa7146_write(dev, BASE_PAGE3, 0x0); 29 saa7146_write(dev, NUM_LINE_BYTE3, (2<<16)|((vbi_pixel_to_capture)<<0)); 30 saa7146_write(dev, MC2, MASK_04|MASK_20); 31 32 /* load brs-control register */ 33 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4)); 34 /* BXO = 1h, BRS to outbound */ 35 WRITE_RPS1(0xc000008c); 36 /* wait for vbi_a or vbi_b*/ 37 if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) { 38 DEB_D(("...using port b\n")); 39 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_E_FID_B); 40 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_O_FID_B); 41/* 42 WRITE_RPS1(CMD_PAUSE | MASK_09); 43*/ 44 } else { 45 DEB_D(("...using port a\n")); 46 WRITE_RPS1(CMD_PAUSE | MASK_10); 47 } 48 /* upload brs */ 49 WRITE_RPS1(CMD_UPLOAD | MASK_08); 50 /* load brs-control register */ 51 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4)); 52 /* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */ 53 WRITE_RPS1(((1728-(vbi_pixel_to_capture)) << 7) | MASK_19); 54 /* wait for brs_done */ 55 WRITE_RPS1(CMD_PAUSE | MASK_08); 56 /* upload brs */ 57 WRITE_RPS1(CMD_UPLOAD | MASK_08); 58 /* load video-dma3 NumLines3 and NumBytes3 */ 59 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4)); 60 /* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */ 61 WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture)); 62 /* load brs-control register */ 63 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4)); 64 /* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */ 65 WRITE_RPS1((540 << 7) | (5 << 19)); // 5 == vbi_start 66 /* wait for brs_done */ 67 WRITE_RPS1(CMD_PAUSE | MASK_08); 68 /* upload brs and video-dma3*/ 69 WRITE_RPS1(CMD_UPLOAD | MASK_08 | MASK_04); 70 /* load mc2 register: enable dma3 */ 71 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4)); 72 WRITE_RPS1(MASK_20 | MASK_04); 73 /* generate interrupt */ 74 WRITE_RPS1(CMD_INTERRUPT); 75 /* stop rps1 */ 76 WRITE_RPS1(CMD_STOP); 77 78 for(i = 0; i < 2; i++) { 79 80 saa7146_write(dev, MC2, MASK_31|MASK_15); 81 82 saa7146_write(dev, NUM_LINE_BYTE3, (1<<16)|(2<<0)); 83 saa7146_write(dev, MC2, MASK_04|MASK_20); 84 85 /* enable rps1 irqs */ 86 SAA7146_IER_ENABLE(dev,MASK_28); 87 88 /* prepare to wait to be woken up by the irq-handler */ 89 add_wait_queue(&vv->vbi_wq, &wait); 90 current->state = TASK_INTERRUPTIBLE; 91 92 saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle); 93 saa7146_write(dev, MC1, (MASK_13 | MASK_29)); 94 95 schedule(); 96 97 DEB_VBI(("brs bug workaround %d/1.\n",i)); 98 99 remove_wait_queue(&vv->vbi_wq, &wait); 100 current->state = TASK_RUNNING; 101 102 /* disable rps1 irqs */ 103 SAA7146_IER_DISABLE(dev,MASK_28); 104 105 /* stop video-dma3 */ 106 saa7146_write(dev, MC1, MASK_20); 107 108 if(signal_pending(current)) { 109 110 DEB_VBI(("aborted (rps:0x%08x).\n",saa7146_read(dev,RPS_ADDR1))); 111 112 /* stop rps1 for sure */ 113 saa7146_write(dev, MC1, MASK_29); 114 115 pci_free_consistent(dev->pci, 4096, cpu, dma_addr); 116 return -EINTR; 117 } 118 } 119 120 pci_free_consistent(dev->pci, 4096, cpu, dma_addr); 121 return 0; 122} 123 124static void saa7146_set_vbi_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next) 125{ 126 struct saa7146_vv *vv = dev->vv_data; 127 128 struct saa7146_video_dma vdma3; 129 130 int count = 0; 131 unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B; 132 unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B; 133 134/* 135 vdma3.base_even = 0xc8000000+2560*70; 136 vdma3.base_odd = 0xc8000000; 137 vdma3.prot_addr = 0xc8000000+2560*164; 138 vdma3.pitch = 2560; 139 vdma3.base_page = 0; 140 vdma3.num_line_byte = (64<<16)|((vbi_pixel_to_capture)<<0); // set above! 141*/ 142 vdma3.base_even = buf->pt[2].offset; 143 vdma3.base_odd = buf->pt[2].offset + 16 * vbi_pixel_to_capture; 144 vdma3.prot_addr = buf->pt[2].offset + 16 * 2 * vbi_pixel_to_capture; 145 vdma3.pitch = vbi_pixel_to_capture; 146 vdma3.base_page = buf->pt[2].dma | ME1; 147 vdma3.num_line_byte = (16 << 16) | vbi_pixel_to_capture; 148 149 saa7146_write_out_dma(dev, 3, &vdma3); 150 151 /* write beginning of rps-program */ 152 count = 0; 153 154 /* wait for o_fid_a/b / e_fid_a/b toggle only if bit 1 is not set */ 155 156 /* we don't wait here for the first field anymore. this is different from the video 157 capture and might cause that the first buffer is only half filled (with only 158 one field). but since this is some sort of streaming data, this is not that negative. 159 but by doing this, we can use the whole engine from video-buf.c... */ 160 161/* 162 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | e_wait); 163 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | o_wait); 164*/ 165 /* set bit 1 */ 166 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC2/4)); 167 WRITE_RPS1(MASK_28 | MASK_12); 168 169 /* turn on video-dma3 */ 170 WRITE_RPS1(CMD_WR_REG_MASK | (MC1/4)); 171 WRITE_RPS1(MASK_04 | MASK_20); /* => mask */ 172 WRITE_RPS1(MASK_04 | MASK_20); /* => values */ 173 174 /* wait for o_fid_a/b / e_fid_a/b toggle */ 175 WRITE_RPS1(CMD_PAUSE | o_wait); 176 WRITE_RPS1(CMD_PAUSE | e_wait); 177 178 /* generate interrupt */ 179 WRITE_RPS1(CMD_INTERRUPT); 180 181 /* stop */ 182 WRITE_RPS1(CMD_STOP); 183 184 /* enable rps1 irqs */ 185 SAA7146_IER_ENABLE(dev, MASK_28); 186 187 /* write the address of the rps-program */ 188 saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle); 189 190 /* turn on rps */ 191 saa7146_write(dev, MC1, (MASK_13 | MASK_29)); 192} 193 194static int buffer_activate(struct saa7146_dev *dev, 195 struct saa7146_buf *buf, 196 struct saa7146_buf *next) 197{ 198 struct saa7146_vv *vv = dev->vv_data; 199 buf->vb.state = STATE_ACTIVE; 200 201 DEB_VBI(("dev:%p, buf:%p, next:%p\n",dev,buf,next)); 202 saa7146_set_vbi_capture(dev,buf,next); 203 204 mod_timer(&vv->vbi_q.timeout, jiffies+BUFFER_TIMEOUT); 205 return 0; 206} 207 208static int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,enum v4l2_field field) 209{ 210 struct file *file = q->priv_data; 211 struct saa7146_fh *fh = file->private_data; 212 struct saa7146_dev *dev = fh->dev; 213 struct saa7146_buf *buf = (struct saa7146_buf *)vb; 214 215 int err = 0; 216 int lines, llength, size; 217 218 lines = 16 * 2 ; /* 2 fields */ 219 llength = vbi_pixel_to_capture; 220 size = lines * llength; 221 222 DEB_VBI(("vb:%p\n",vb)); 223 224 if (0 != buf->vb.baddr && buf->vb.bsize < size) { 225 DEB_VBI(("size mismatch.\n")); 226 return -EINVAL; 227 } 228 229 if (buf->vb.size != size) 230 saa7146_dma_free(dev,q,buf); 231 232 if (STATE_NEEDS_INIT == buf->vb.state) { 233 buf->vb.width = llength; 234 buf->vb.height = lines; 235 buf->vb.size = size; 236 buf->vb.field = field; 237 238 saa7146_pgtable_free(dev->pci, &buf->pt[2]); 239 saa7146_pgtable_alloc(dev->pci, &buf->pt[2]); 240 241 err = videobuf_iolock(q,&buf->vb, NULL); 242 if (err) 243 goto oops; 244 err = saa7146_pgtable_build_single(dev->pci, &buf->pt[2], buf->vb.dma.sglist, buf->vb.dma.sglen); 245 if (0 != err) 246 return err; 247 } 248 buf->vb.state = STATE_PREPARED; 249 buf->activate = buffer_activate; 250 251 return 0; 252 253 oops: 254 DEB_VBI(("error out.\n")); 255 saa7146_dma_free(dev,q,buf); 256 257 return err; 258} 259 260static int buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size) 261{ 262 int llength,lines; 263 264 lines = 16 * 2 ; /* 2 fields */ 265 llength = vbi_pixel_to_capture; 266 267 *size = lines * llength; 268 *count = 2; 269 270 DEB_VBI(("count:%d, size:%d\n",*count,*size)); 271 272 return 0; 273} 274 275static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) 276{ 277 struct file *file = q->priv_data; 278 struct saa7146_fh *fh = file->private_data; 279 struct saa7146_dev *dev = fh->dev; 280 struct saa7146_vv *vv = dev->vv_data; 281 struct saa7146_buf *buf = (struct saa7146_buf *)vb; 282 283 DEB_VBI(("vb:%p\n",vb)); 284 saa7146_buffer_queue(dev,&vv->vbi_q,buf); 285} 286 287static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb) 288{ 289 struct file *file = q->priv_data; 290 struct saa7146_fh *fh = file->private_data; 291 struct saa7146_dev *dev = fh->dev; 292 struct saa7146_buf *buf = (struct saa7146_buf *)vb; 293 294 DEB_VBI(("vb:%p\n",vb)); 295 saa7146_dma_free(dev,q,buf); 296} 297 298static struct videobuf_queue_ops vbi_qops = { 299 .buf_setup = buffer_setup, 300 .buf_prepare = buffer_prepare, 301 .buf_queue = buffer_queue, 302 .buf_release = buffer_release, 303}; 304 305/* ------------------------------------------------------------------ */ 306 307static void vbi_stop(struct saa7146_fh *fh, struct file *file) 308{ 309 struct saa7146_dev *dev = fh->dev; 310 struct saa7146_vv *vv = dev->vv_data; 311 unsigned long flags; 312 DEB_VBI(("dev:%p, fh:%p\n",dev, fh)); 313 314 spin_lock_irqsave(&dev->slock,flags); 315 316 /* disable rps1 */ 317 saa7146_write(dev, MC1, MASK_29); 318 319 /* disable rps1 irqs */ 320 SAA7146_IER_DISABLE(dev, MASK_28); 321 322 /* shut down dma 3 transfers */ 323 saa7146_write(dev, MC1, MASK_20); 324 325 if (vv->vbi_q.curr) { 326 saa7146_buffer_finish(dev,&vv->vbi_q,STATE_DONE); 327 } 328 329 videobuf_queue_cancel(&fh->vbi_q); 330 331 vv->vbi_streaming = NULL; 332 333 del_timer(&vv->vbi_q.timeout); 334 del_timer(&fh->vbi_read_timeout); 335 336 spin_unlock_irqrestore(&dev->slock, flags); 337} 338 339static void vbi_read_timeout(unsigned long data) 340{ 341 struct file *file = (struct file*)data; 342 struct saa7146_fh *fh = file->private_data; 343 struct saa7146_dev *dev = fh->dev; 344 345 DEB_VBI(("dev:%p, fh:%p\n",dev, fh)); 346 347 vbi_stop(fh, file); 348} 349 350static void vbi_init(struct saa7146_dev *dev, struct saa7146_vv *vv) 351{ 352 DEB_VBI(("dev:%p\n",dev)); 353 354 INIT_LIST_HEAD(&vv->vbi_q.queue); 355 356 init_timer(&vv->vbi_q.timeout); 357 vv->vbi_q.timeout.function = saa7146_buffer_timeout; 358 vv->vbi_q.timeout.data = (unsigned long)(&vv->vbi_q); 359 vv->vbi_q.dev = dev; 360 361 init_waitqueue_head(&vv->vbi_wq); 362} 363 364static int vbi_open(struct saa7146_dev *dev, struct file *file) 365{ 366 struct saa7146_fh *fh = (struct saa7146_fh *)file->private_data; 367 368 u32 arbtr_ctrl = saa7146_read(dev, PCI_BT_V1); 369 int ret = 0; 370 371 DEB_VBI(("dev:%p, fh:%p\n",dev,fh)); 372 373 ret = saa7146_res_get(fh, RESOURCE_DMA3_BRS); 374 if (0 == ret) { 375 DEB_S(("cannot get vbi RESOURCE_DMA3_BRS resource\n")); 376 return -EBUSY; 377 } 378 379 /* adjust arbitrition control for video dma 3 */ 380 arbtr_ctrl &= ~0x1f0000; 381 arbtr_ctrl |= 0x1d0000; 382 saa7146_write(dev, PCI_BT_V1, arbtr_ctrl); 383 saa7146_write(dev, MC2, (MASK_04|MASK_20)); 384 385 memset(&fh->vbi_fmt,0,sizeof(fh->vbi_fmt)); 386 387 fh->vbi_fmt.sampling_rate = 27000000; 388 fh->vbi_fmt.offset = 248; /* todo */ 389 fh->vbi_fmt.samples_per_line = vbi_pixel_to_capture; 390 fh->vbi_fmt.sample_format = V4L2_PIX_FMT_GREY; 391 392 fh->vbi_fmt.start[0] = 5; 393 fh->vbi_fmt.count[0] = 16; 394 fh->vbi_fmt.start[1] = 312; 395 fh->vbi_fmt.count[1] = 16; 396 397 videobuf_queue_init(&fh->vbi_q, &vbi_qops, 398 dev->pci, &dev->slock, 399 V4L2_BUF_TYPE_VBI_CAPTURE, 400 V4L2_FIELD_SEQ_TB, 401 sizeof(struct saa7146_buf), 402 file); 403 mutex_init(&fh->vbi_q.lock); 404 405 init_timer(&fh->vbi_read_timeout); 406 fh->vbi_read_timeout.function = vbi_read_timeout; 407 fh->vbi_read_timeout.data = (unsigned long)file; 408 409 /* initialize the brs */ 410 if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) { 411 saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19)); 412 } else { 413 saa7146_write(dev, BRS_CTRL, 0x00000001); 414 415 if (0 != (ret = vbi_workaround(dev))) { 416 DEB_VBI(("vbi workaround failed!\n")); 417 /* return ret;*/ 418 } 419 } 420 421 /* upload brs register */ 422 saa7146_write(dev, MC2, (MASK_08|MASK_24)); 423 return 0; 424} 425 426static void vbi_close(struct saa7146_dev *dev, struct file *file) 427{ 428 struct saa7146_fh *fh = (struct saa7146_fh *)file->private_data; 429 struct saa7146_vv *vv = dev->vv_data; 430 DEB_VBI(("dev:%p, fh:%p\n",dev,fh)); 431 432 if( fh == vv->vbi_streaming ) { 433 vbi_stop(fh, file); 434 } 435 saa7146_res_free(fh, RESOURCE_DMA3_BRS); 436} 437 438static void vbi_irq_done(struct saa7146_dev *dev, unsigned long status) 439{ 440 struct saa7146_vv *vv = dev->vv_data; 441 spin_lock(&dev->slock); 442 443 if (vv->vbi_q.curr) { 444 DEB_VBI(("dev:%p, curr:%p\n",dev,vv->vbi_q.curr)); 445 /* this must be += 2, one count for each field */ 446 vv->vbi_fieldcount+=2; 447 vv->vbi_q.curr->vb.field_count = vv->vbi_fieldcount; 448 saa7146_buffer_finish(dev,&vv->vbi_q,STATE_DONE); 449 } else { 450 DEB_VBI(("dev:%p\n",dev)); 451 } 452 saa7146_buffer_next(dev,&vv->vbi_q,1); 453 454 spin_unlock(&dev->slock); 455} 456 457static ssize_t vbi_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 458{ 459 struct saa7146_fh *fh = file->private_data; 460 struct saa7146_dev *dev = fh->dev; 461 struct saa7146_vv *vv = dev->vv_data; 462 ssize_t ret = 0; 463 464 DEB_VBI(("dev:%p, fh:%p\n",dev,fh)); 465 466 if( NULL == vv->vbi_streaming ) { 467 vv->vbi_streaming = fh; 468 } 469 470 if( fh != vv->vbi_streaming ) { 471 DEB_VBI(("open %p is already using vbi capture.",vv->vbi_streaming)); 472 return -EBUSY; 473 } 474 475 mod_timer(&fh->vbi_read_timeout, jiffies+BUFFER_TIMEOUT); 476 ret = videobuf_read_stream(&fh->vbi_q, data, count, ppos, 1, 477 file->f_flags & O_NONBLOCK); 478/* 479 printk("BASE_ODD3: 0x%08x\n", saa7146_read(dev, BASE_ODD3)); 480 printk("BASE_EVEN3: 0x%08x\n", saa7146_read(dev, BASE_EVEN3)); 481 printk("PROT_ADDR3: 0x%08x\n", saa7146_read(dev, PROT_ADDR3)); 482 printk("PITCH3: 0x%08x\n", saa7146_read(dev, PITCH3)); 483 printk("BASE_PAGE3: 0x%08x\n", saa7146_read(dev, BASE_PAGE3)); 484 printk("NUM_LINE_BYTE3: 0x%08x\n", saa7146_read(dev, NUM_LINE_BYTE3)); 485 printk("BRS_CTRL: 0x%08x\n", saa7146_read(dev, BRS_CTRL)); 486*/ 487 return ret; 488} 489 490struct saa7146_use_ops saa7146_vbi_uops = { 491 .init = vbi_init, 492 .open = vbi_open, 493 .release = vbi_close, 494 .irq_done = vbi_irq_done, 495 .read = vbi_read, 496}; 497