1/*************************************************************************/ 2/* $Id: hfc4s8s_l1.c,v 1.1.1.1 2007/08/03 18:52:35 Exp $ */ 3/* HFC-4S/8S low layer interface for Cologne Chip HFC-4S/8S isdn chips */ 4/* The low layer (L1) is implemented as a loadable module for usage with */ 5/* the HiSax isdn driver for passive cards. */ 6/* */ 7/* Author: Werner Cornelius */ 8/* (C) 2003 Cornelius Consult (werner@cornelius-consult.de) */ 9/* */ 10/* Driver maintained by Cologne Chip */ 11/* - Martin Bachem, support@colognechip.com */ 12/* */ 13/* This driver only works with chip revisions >= 1, older revision 0 */ 14/* engineering samples (only first manufacturer sample cards) will not */ 15/* work and are rejected by the driver. */ 16/* */ 17/* This file distributed under the GNU GPL. */ 18/* */ 19/* See Version History at the end of this file */ 20/* */ 21/*************************************************************************/ 22 23#include <linux/module.h> 24#include <linux/init.h> 25#include <linux/pci.h> 26#include <linux/interrupt.h> 27#include <linux/delay.h> 28#include <linux/timer.h> 29#include <linux/skbuff.h> 30#include <linux/wait.h> 31#include <asm/io.h> 32#include "hisax_if.h" 33#include "hfc4s8s_l1.h" 34 35static const char hfc4s8s_rev[] = "Revision: 1.10"; 36 37/***************************************************************/ 38/* adjustable transparent mode fifo threshold */ 39/* The value defines the used fifo threshold with the equation */ 40/* */ 41/* notify number of bytes = 2 * 2 ^ TRANS_FIFO_THRES */ 42/* */ 43/* The default value is 5 which results in a buffer size of 64 */ 44/* and an interrupt rate of 8ms. */ 45/* The maximum value is 7 due to fifo size restrictions. */ 46/* Values below 3-4 are not recommended due to high interrupt */ 47/* load of the processor. For non critical applications the */ 48/* value should be raised to 7 to reduce any interrupt overhead*/ 49/***************************************************************/ 50#define TRANS_FIFO_THRES 5 51 52/*************/ 53/* constants */ 54/*************/ 55#define CLOCKMODE_0 0 /* ext. 24.576 MhZ clk freq, int. single clock mode */ 56#define CLOCKMODE_1 1 /* ext. 49.576 MhZ clk freq, int. single clock mode */ 57#define CHIP_ID_SHIFT 4 58#define HFC_MAX_ST 8 59#define MAX_D_FRAME_SIZE 270 60#define MAX_B_FRAME_SIZE 1536 61#define TRANS_TIMER_MODE (TRANS_FIFO_THRES & 0xf) 62#define TRANS_FIFO_BYTES (2 << TRANS_FIFO_THRES) 63#define MAX_F_CNT 0x0f 64 65#define CLKDEL_NT 0x6c 66#define CLKDEL_TE 0xf 67#define CTRL0_NT 4 68#define CTRL0_TE 0 69 70#define L1_TIMER_T4 2 /* minimum in jiffies */ 71#define L1_TIMER_T3 (7 * HZ) /* activation timeout */ 72#define L1_TIMER_T1 ((120 * HZ) / 1000) /* NT mode deactivation timeout */ 73 74 75/******************/ 76/* types and vars */ 77/******************/ 78static int card_cnt; 79 80/* private driver_data */ 81typedef struct { 82 int chip_id; 83 int clock_mode; 84 int max_st_ports; 85 char *device_name; 86} hfc4s8s_param; 87 88static struct pci_device_id hfc4s8s_ids[] = { 89 {.vendor = PCI_VENDOR_ID_CCD, 90 .device = PCI_DEVICE_ID_4S, 91 .subvendor = 0x1397, 92 .subdevice = 0x08b4, 93 .driver_data = 94 (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_0, 4, 95 "HFC-4S Evaluation Board"}), 96 }, 97 {.vendor = PCI_VENDOR_ID_CCD, 98 .device = PCI_DEVICE_ID_8S, 99 .subvendor = 0x1397, 100 .subdevice = 0x16b8, 101 .driver_data = 102 (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_0, 8, 103 "HFC-8S Evaluation Board"}), 104 }, 105 {.vendor = PCI_VENDOR_ID_CCD, 106 .device = PCI_DEVICE_ID_4S, 107 .subvendor = 0x1397, 108 .subdevice = 0xb520, 109 .driver_data = 110 (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_1, 4, 111 "IOB4ST"}), 112 }, 113 {.vendor = PCI_VENDOR_ID_CCD, 114 .device = PCI_DEVICE_ID_8S, 115 .subvendor = 0x1397, 116 .subdevice = 0xb522, 117 .driver_data = 118 (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_1, 8, 119 "IOB8ST"}), 120 }, 121 {} 122}; 123 124MODULE_DEVICE_TABLE(pci, hfc4s8s_ids); 125 126MODULE_AUTHOR("Werner Cornelius, werner@cornelius-consult.de"); 127MODULE_DESCRIPTION("ISDN layer 1 for Cologne Chip HFC-4S/8S chips"); 128MODULE_LICENSE("GPL"); 129 130/***********/ 131/* layer 1 */ 132/***********/ 133struct hfc4s8s_btype { 134 spinlock_t lock; 135 struct hisax_b_if b_if; 136 struct hfc4s8s_l1 *l1p; 137 struct sk_buff_head tx_queue; 138 struct sk_buff *tx_skb; 139 struct sk_buff *rx_skb; 140 __u8 *rx_ptr; 141 int tx_cnt; 142 int bchan; 143 int mode; 144}; 145 146struct _hfc4s8s_hw; 147 148struct hfc4s8s_l1 { 149 spinlock_t lock; 150 struct _hfc4s8s_hw *hw; /* pointer to hardware area */ 151 int l1_state; /* actual l1 state */ 152 struct timer_list l1_timer; /* layer 1 timer structure */ 153 int nt_mode; /* set to nt mode */ 154 int st_num; /* own index */ 155 int enabled; /* interface is enabled */ 156 struct sk_buff_head d_tx_queue; /* send queue */ 157 int tx_cnt; /* bytes to send */ 158 struct hisax_d_if d_if; /* D-channel interface */ 159 struct hfc4s8s_btype b_ch[2]; /* B-channel data */ 160 struct hisax_b_if *b_table[2]; 161}; 162 163/**********************/ 164/* hardware structure */ 165/**********************/ 166typedef struct _hfc4s8s_hw { 167 spinlock_t lock; 168 169 int cardnum; 170 int ifnum; 171 int iobase; 172 int nt_mode; 173 u_char *membase; 174 u_char *hw_membase; 175 void *pdev; 176 int max_fifo; 177 hfc4s8s_param driver_data; 178 int irq; 179 int fifo_sched_cnt; 180 struct work_struct tqueue; 181 struct hfc4s8s_l1 l1[HFC_MAX_ST]; 182 char card_name[60]; 183 struct { 184 u_char r_irq_ctrl; 185 u_char r_ctrl0; 186 volatile u_char r_irq_statech; /* active isdn l1 status */ 187 u_char r_irqmsk_statchg; /* enabled isdn status ints */ 188 u_char r_irq_fifo_blx[8]; /* fifo status registers */ 189 u_char fifo_rx_trans_enables[8]; /* mask for enabled transparent rx fifos */ 190 u_char fifo_slow_timer_service[8]; /* mask for fifos needing slower timer service */ 191 volatile u_char r_irq_oview; /* contents of overview register */ 192 volatile u_char timer_irq; 193 int timer_usg_cnt; /* number of channels using timer */ 194 } mr; 195} hfc4s8s_hw; 196 197 198 199/***************************/ 200/* inline function defines */ 201/***************************/ 202#ifdef HISAX_HFC4S8S_PCIMEM /* inline functions memory mapped */ 203 204/* memory write and dummy IO read to avoid PCI byte merge problems */ 205#define Write_hfc8(a,b,c) {(*((volatile u_char *)(a->membase+b)) = c); inb(a->iobase+4);} 206/* memory write without dummy IO access for fifo data access */ 207#define fWrite_hfc8(a,b,c) (*((volatile u_char *)(a->membase+b)) = c) 208#define Read_hfc8(a,b) (*((volatile u_char *)(a->membase+b))) 209#define Write_hfc16(a,b,c) (*((volatile unsigned short *)(a->membase+b)) = c) 210#define Read_hfc16(a,b) (*((volatile unsigned short *)(a->membase+b))) 211#define Write_hfc32(a,b,c) (*((volatile unsigned long *)(a->membase+b)) = c) 212#define Read_hfc32(a,b) (*((volatile unsigned long *)(a->membase+b))) 213#define wait_busy(a) {while ((Read_hfc8(a, R_STATUS) & M_BUSY));} 214#define PCI_ENA_MEMIO 0x03 215 216#else 217 218/* inline functions io mapped */ 219static inline void 220SetRegAddr(hfc4s8s_hw * a, u_char b) 221{ 222 outb(b, (a->iobase) + 4); 223} 224 225static inline u_char 226GetRegAddr(hfc4s8s_hw * a) 227{ 228 return (inb((volatile u_int) (a->iobase + 4))); 229} 230 231 232static inline void 233Write_hfc8(hfc4s8s_hw * a, u_char b, u_char c) 234{ 235 SetRegAddr(a, b); 236 outb(c, a->iobase); 237} 238 239static inline void 240fWrite_hfc8(hfc4s8s_hw * a, u_char c) 241{ 242 outb(c, a->iobase); 243} 244 245static inline void 246Write_hfc16(hfc4s8s_hw * a, u_char b, u_short c) 247{ 248 SetRegAddr(a, b); 249 outw(c, a->iobase); 250} 251 252static inline void 253Write_hfc32(hfc4s8s_hw * a, u_char b, u_long c) 254{ 255 SetRegAddr(a, b); 256 outl(c, a->iobase); 257} 258 259static inline void 260fWrite_hfc32(hfc4s8s_hw * a, u_long c) 261{ 262 outl(c, a->iobase); 263} 264 265static inline u_char 266Read_hfc8(hfc4s8s_hw * a, u_char b) 267{ 268 SetRegAddr(a, b); 269 return (inb((volatile u_int) a->iobase)); 270} 271 272static inline u_char 273fRead_hfc8(hfc4s8s_hw * a) 274{ 275 return (inb((volatile u_int) a->iobase)); 276} 277 278 279static inline u_short 280Read_hfc16(hfc4s8s_hw * a, u_char b) 281{ 282 SetRegAddr(a, b); 283 return (inw((volatile u_int) a->iobase)); 284} 285 286static inline u_long 287Read_hfc32(hfc4s8s_hw * a, u_char b) 288{ 289 SetRegAddr(a, b); 290 return (inl((volatile u_int) a->iobase)); 291} 292 293static inline u_long 294fRead_hfc32(hfc4s8s_hw * a) 295{ 296 return (inl((volatile u_int) a->iobase)); 297} 298 299static inline void 300wait_busy(hfc4s8s_hw * a) 301{ 302 SetRegAddr(a, R_STATUS); 303 while (inb((volatile u_int) a->iobase) & M_BUSY); 304} 305 306#define PCI_ENA_REGIO 0x01 307 308#endif /* HISAX_HFC4S8S_PCIMEM */ 309 310/******************************************************/ 311/* function to read critical counter registers that */ 312/* may be udpated by the chip during read */ 313/******************************************************/ 314static u_char 315Read_hfc8_stable(hfc4s8s_hw * hw, int reg) 316{ 317 u_char ref8; 318 u_char in8; 319 ref8 = Read_hfc8(hw, reg); 320 while (((in8 = Read_hfc8(hw, reg)) != ref8)) { 321 ref8 = in8; 322 } 323 return in8; 324} 325 326static int 327Read_hfc16_stable(hfc4s8s_hw * hw, int reg) 328{ 329 int ref16; 330 int in16; 331 332 ref16 = Read_hfc16(hw, reg); 333 while (((in16 = Read_hfc16(hw, reg)) != ref16)) { 334 ref16 = in16; 335 } 336 return in16; 337} 338 339/*****************************/ 340/* D-channel call from HiSax */ 341/*****************************/ 342static void 343dch_l2l1(struct hisax_d_if *iface, int pr, void *arg) 344{ 345 struct hfc4s8s_l1 *l1 = iface->ifc.priv; 346 struct sk_buff *skb = (struct sk_buff *) arg; 347 u_long flags; 348 349 switch (pr) { 350 351 case (PH_DATA | REQUEST): 352 if (!l1->enabled) { 353 dev_kfree_skb(skb); 354 break; 355 } 356 spin_lock_irqsave(&l1->lock, flags); 357 skb_queue_tail(&l1->d_tx_queue, skb); 358 if ((skb_queue_len(&l1->d_tx_queue) == 1) && 359 (l1->tx_cnt <= 0)) { 360 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= 361 0x10; 362 spin_unlock_irqrestore(&l1->lock, flags); 363 schedule_work(&l1->hw->tqueue); 364 } else 365 spin_unlock_irqrestore(&l1->lock, flags); 366 break; 367 368 case (PH_ACTIVATE | REQUEST): 369 if (!l1->enabled) 370 break; 371 if (!l1->nt_mode) { 372 if (l1->l1_state < 6) { 373 spin_lock_irqsave(&l1->lock, 374 flags); 375 376 Write_hfc8(l1->hw, R_ST_SEL, 377 l1->st_num); 378 Write_hfc8(l1->hw, A_ST_WR_STA, 379 0x60); 380 mod_timer(&l1->l1_timer, 381 jiffies + L1_TIMER_T3); 382 spin_unlock_irqrestore(&l1->lock, 383 flags); 384 } else if (l1->l1_state == 7) 385 l1->d_if.ifc.l1l2(&l1->d_if.ifc, 386 PH_ACTIVATE | 387 INDICATION, 388 NULL); 389 } else { 390 if (l1->l1_state != 3) { 391 spin_lock_irqsave(&l1->lock, 392 flags); 393 Write_hfc8(l1->hw, R_ST_SEL, 394 l1->st_num); 395 Write_hfc8(l1->hw, A_ST_WR_STA, 396 0x60); 397 spin_unlock_irqrestore(&l1->lock, 398 flags); 399 } else if (l1->l1_state == 3) 400 l1->d_if.ifc.l1l2(&l1->d_if.ifc, 401 PH_ACTIVATE | 402 INDICATION, 403 NULL); 404 } 405 break; 406 407 default: 408 printk(KERN_INFO 409 "HFC-4S/8S: Unknown D-chan cmd 0x%x received, ignored\n", 410 pr); 411 break; 412 } 413 if (!l1->enabled) 414 l1->d_if.ifc.l1l2(&l1->d_if.ifc, 415 PH_DEACTIVATE | INDICATION, NULL); 416} /* dch_l2l1 */ 417 418/*****************************/ 419/* B-channel call from HiSax */ 420/*****************************/ 421static void 422bch_l2l1(struct hisax_if *ifc, int pr, void *arg) 423{ 424 struct hfc4s8s_btype *bch = ifc->priv; 425 struct hfc4s8s_l1 *l1 = bch->l1p; 426 struct sk_buff *skb = (struct sk_buff *) arg; 427 long mode = (long) arg; 428 u_long flags; 429 430 switch (pr) { 431 432 case (PH_DATA | REQUEST): 433 if (!l1->enabled || (bch->mode == L1_MODE_NULL)) { 434 dev_kfree_skb(skb); 435 break; 436 } 437 spin_lock_irqsave(&l1->lock, flags); 438 skb_queue_tail(&bch->tx_queue, skb); 439 if (!bch->tx_skb && (bch->tx_cnt <= 0)) { 440 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= 441 ((bch->bchan == 1) ? 1 : 4); 442 spin_unlock_irqrestore(&l1->lock, flags); 443 schedule_work(&l1->hw->tqueue); 444 } else 445 spin_unlock_irqrestore(&l1->lock, flags); 446 break; 447 448 case (PH_ACTIVATE | REQUEST): 449 case (PH_DEACTIVATE | REQUEST): 450 if (!l1->enabled) 451 break; 452 if (pr == (PH_DEACTIVATE | REQUEST)) 453 mode = L1_MODE_NULL; 454 455 switch (mode) { 456 case L1_MODE_HDLC: 457 spin_lock_irqsave(&l1->lock, 458 flags); 459 l1->hw->mr.timer_usg_cnt++; 460 l1->hw->mr. 461 fifo_slow_timer_service[l1-> 462 st_num] 463 |= 464 ((bch->bchan == 465 1) ? 0x2 : 0x8); 466 Write_hfc8(l1->hw, R_FIFO, 467 (l1->st_num * 8 + 468 ((bch->bchan == 469 1) ? 0 : 2))); 470 wait_busy(l1->hw); 471 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ 472 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ 473 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable TX interrupts for hdlc */ 474 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ 475 wait_busy(l1->hw); 476 477 Write_hfc8(l1->hw, R_FIFO, 478 (l1->st_num * 8 + 479 ((bch->bchan == 480 1) ? 1 : 3))); 481 wait_busy(l1->hw); 482 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ 483 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ 484 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable RX interrupts for hdlc */ 485 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ 486 487 Write_hfc8(l1->hw, R_ST_SEL, 488 l1->st_num); 489 l1->hw->mr.r_ctrl0 |= 490 (bch->bchan & 3); 491 Write_hfc8(l1->hw, A_ST_CTRL0, 492 l1->hw->mr.r_ctrl0); 493 bch->mode = L1_MODE_HDLC; 494 spin_unlock_irqrestore(&l1->lock, 495 flags); 496 497 bch->b_if.ifc.l1l2(&bch->b_if.ifc, 498 PH_ACTIVATE | 499 INDICATION, 500 NULL); 501 break; 502 503 case L1_MODE_TRANS: 504 spin_lock_irqsave(&l1->lock, 505 flags); 506 l1->hw->mr. 507 fifo_rx_trans_enables[l1-> 508 st_num] 509 |= 510 ((bch->bchan == 511 1) ? 0x2 : 0x8); 512 l1->hw->mr.timer_usg_cnt++; 513 Write_hfc8(l1->hw, R_FIFO, 514 (l1->st_num * 8 + 515 ((bch->bchan == 516 1) ? 0 : 2))); 517 wait_busy(l1->hw); 518 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ 519 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ 520 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ 521 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ 522 wait_busy(l1->hw); 523 524 Write_hfc8(l1->hw, R_FIFO, 525 (l1->st_num * 8 + 526 ((bch->bchan == 527 1) ? 1 : 3))); 528 wait_busy(l1->hw); 529 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ 530 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ 531 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ 532 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ 533 534 Write_hfc8(l1->hw, R_ST_SEL, 535 l1->st_num); 536 l1->hw->mr.r_ctrl0 |= 537 (bch->bchan & 3); 538 Write_hfc8(l1->hw, A_ST_CTRL0, 539 l1->hw->mr.r_ctrl0); 540 bch->mode = L1_MODE_TRANS; 541 spin_unlock_irqrestore(&l1->lock, 542 flags); 543 544 bch->b_if.ifc.l1l2(&bch->b_if.ifc, 545 PH_ACTIVATE | 546 INDICATION, 547 NULL); 548 break; 549 550 default: 551 if (bch->mode == L1_MODE_NULL) 552 break; 553 spin_lock_irqsave(&l1->lock, 554 flags); 555 l1->hw->mr. 556 fifo_slow_timer_service[l1-> 557 st_num] 558 &= 559 ~((bch->bchan == 560 1) ? 0x3 : 0xc); 561 l1->hw->mr. 562 fifo_rx_trans_enables[l1-> 563 st_num] 564 &= 565 ~((bch->bchan == 566 1) ? 0x3 : 0xc); 567 l1->hw->mr.timer_usg_cnt--; 568 Write_hfc8(l1->hw, R_FIFO, 569 (l1->st_num * 8 + 570 ((bch->bchan == 571 1) ? 0 : 2))); 572 wait_busy(l1->hw); 573 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ 574 wait_busy(l1->hw); 575 Write_hfc8(l1->hw, R_FIFO, 576 (l1->st_num * 8 + 577 ((bch->bchan == 578 1) ? 1 : 3))); 579 wait_busy(l1->hw); 580 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ 581 Write_hfc8(l1->hw, R_ST_SEL, 582 l1->st_num); 583 l1->hw->mr.r_ctrl0 &= 584 ~(bch->bchan & 3); 585 Write_hfc8(l1->hw, A_ST_CTRL0, 586 l1->hw->mr.r_ctrl0); 587 spin_unlock_irqrestore(&l1->lock, 588 flags); 589 590 bch->mode = L1_MODE_NULL; 591 bch->b_if.ifc.l1l2(&bch->b_if.ifc, 592 PH_DEACTIVATE | 593 INDICATION, 594 NULL); 595 if (bch->tx_skb) { 596 dev_kfree_skb(bch->tx_skb); 597 bch->tx_skb = NULL; 598 } 599 if (bch->rx_skb) { 600 dev_kfree_skb(bch->rx_skb); 601 bch->rx_skb = NULL; 602 } 603 skb_queue_purge(&bch->tx_queue); 604 bch->tx_cnt = 0; 605 bch->rx_ptr = NULL; 606 break; 607 } 608 609 /* timer is only used when at least one b channel */ 610 /* is set up to transparent mode */ 611 if (l1->hw->mr.timer_usg_cnt) { 612 Write_hfc8(l1->hw, R_IRQMSK_MISC, 613 M_TI_IRQMSK); 614 } else { 615 Write_hfc8(l1->hw, R_IRQMSK_MISC, 0); 616 } 617 618 break; 619 620 default: 621 printk(KERN_INFO 622 "HFC-4S/8S: Unknown B-chan cmd 0x%x received, ignored\n", 623 pr); 624 break; 625 } 626 if (!l1->enabled) 627 bch->b_if.ifc.l1l2(&bch->b_if.ifc, 628 PH_DEACTIVATE | INDICATION, NULL); 629} /* bch_l2l1 */ 630 631/**************************/ 632/* layer 1 timer function */ 633/**************************/ 634static void 635hfc_l1_timer(struct hfc4s8s_l1 *l1) 636{ 637 u_long flags; 638 639 if (!l1->enabled) 640 return; 641 642 spin_lock_irqsave(&l1->lock, flags); 643 if (l1->nt_mode) { 644 l1->l1_state = 1; 645 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); 646 Write_hfc8(l1->hw, A_ST_WR_STA, 0x11); 647 spin_unlock_irqrestore(&l1->lock, flags); 648 l1->d_if.ifc.l1l2(&l1->d_if.ifc, 649 PH_DEACTIVATE | INDICATION, NULL); 650 spin_lock_irqsave(&l1->lock, flags); 651 l1->l1_state = 1; 652 Write_hfc8(l1->hw, A_ST_WR_STA, 0x1); 653 spin_unlock_irqrestore(&l1->lock, flags); 654 } else { 655 /* activation timed out */ 656 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); 657 Write_hfc8(l1->hw, A_ST_WR_STA, 0x13); 658 spin_unlock_irqrestore(&l1->lock, flags); 659 l1->d_if.ifc.l1l2(&l1->d_if.ifc, 660 PH_DEACTIVATE | INDICATION, NULL); 661 spin_lock_irqsave(&l1->lock, flags); 662 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); 663 Write_hfc8(l1->hw, A_ST_WR_STA, 0x3); 664 spin_unlock_irqrestore(&l1->lock, flags); 665 } 666} /* hfc_l1_timer */ 667 668/****************************************/ 669/* a complete D-frame has been received */ 670/****************************************/ 671static void 672rx_d_frame(struct hfc4s8s_l1 *l1p, int ech) 673{ 674 int z1, z2; 675 u_char f1, f2, df; 676 struct sk_buff *skb; 677 u_char *cp; 678 679 680 if (!l1p->enabled) 681 return; 682 do { 683 /* E/D RX fifo */ 684 Write_hfc8(l1p->hw, R_FIFO, 685 (l1p->st_num * 8 + ((ech) ? 7 : 5))); 686 wait_busy(l1p->hw); 687 688 f1 = Read_hfc8_stable(l1p->hw, A_F1); 689 f2 = Read_hfc8(l1p->hw, A_F2); 690 df = f1 - f2; 691 if ((f1 - f2) < 0) 692 df = f1 - f2 + MAX_F_CNT + 1; 693 694 695 if (!df) { 696 return; /* no complete frame in fifo */ 697 } 698 699 z1 = Read_hfc16_stable(l1p->hw, A_Z1); 700 z2 = Read_hfc16(l1p->hw, A_Z2); 701 702 z1 = z1 - z2 + 1; 703 if (z1 < 0) 704 z1 += 384; 705 706 if (!(skb = dev_alloc_skb(MAX_D_FRAME_SIZE))) { 707 printk(KERN_INFO 708 "HFC-4S/8S: Could not allocate D/E " 709 "channel receive buffer"); 710 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2); 711 wait_busy(l1p->hw); 712 return; 713 } 714 715 if (((z1 < 4) || (z1 > MAX_D_FRAME_SIZE))) { 716 if (skb) 717 dev_kfree_skb(skb); 718 /* remove errornous D frame */ 719 if (df == 1) { 720 /* reset fifo */ 721 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2); 722 wait_busy(l1p->hw); 723 return; 724 } else { 725 /* read errornous D frame */ 726 727#ifndef HISAX_HFC4S8S_PCIMEM 728 SetRegAddr(l1p->hw, A_FIFO_DATA0); 729#endif 730 731 while (z1 >= 4) { 732#ifdef HISAX_HFC4S8S_PCIMEM 733 Read_hfc32(l1p->hw, A_FIFO_DATA0); 734#else 735 fRead_hfc32(l1p->hw); 736#endif 737 z1 -= 4; 738 } 739 740 while (z1--) 741#ifdef HISAX_HFC4S8S_PCIMEM 742 Read_hfc8(l1p->hw, A_FIFO_DATA0); 743#else 744 fRead_hfc8(l1p->hw); 745#endif 746 747 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); 748 wait_busy(l1p->hw); 749 return; 750 } 751 } 752 753 cp = skb->data; 754 755#ifndef HISAX_HFC4S8S_PCIMEM 756 SetRegAddr(l1p->hw, A_FIFO_DATA0); 757#endif 758 759 while (z1 >= 4) { 760#ifdef HISAX_HFC4S8S_PCIMEM 761 *((unsigned long *) cp) = 762 Read_hfc32(l1p->hw, A_FIFO_DATA0); 763#else 764 *((unsigned long *) cp) = fRead_hfc32(l1p->hw); 765#endif 766 cp += 4; 767 z1 -= 4; 768 } 769 770 while (z1--) 771#ifdef HISAX_HFC4S8S_PCIMEM 772 *cp++ = Read_hfc8(l1p->hw, A_FIFO_DATA0); 773#else 774 *cp++ = fRead_hfc8(l1p->hw); 775#endif 776 777 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ 778 wait_busy(l1p->hw); 779 780 if (*(--cp)) { 781 dev_kfree_skb(skb); 782 } else { 783 skb->len = (cp - skb->data) - 2; 784 if (ech) 785 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, 786 PH_DATA_E | INDICATION, 787 skb); 788 else 789 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, 790 PH_DATA | INDICATION, 791 skb); 792 } 793 } while (1); 794} /* rx_d_frame */ 795 796/*************************************************************/ 797/* a B-frame has been received (perhaps not fully completed) */ 798/*************************************************************/ 799static void 800rx_b_frame(struct hfc4s8s_btype *bch) 801{ 802 int z1, z2, hdlc_complete; 803 u_char f1, f2; 804 struct hfc4s8s_l1 *l1 = bch->l1p; 805 struct sk_buff *skb; 806 807 if (!l1->enabled || (bch->mode == L1_MODE_NULL)) 808 return; 809 810 do { 811 /* RX Fifo */ 812 Write_hfc8(l1->hw, R_FIFO, 813 (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3))); 814 wait_busy(l1->hw); 815 816 if (bch->mode == L1_MODE_HDLC) { 817 f1 = Read_hfc8_stable(l1->hw, A_F1); 818 f2 = Read_hfc8(l1->hw, A_F2); 819 hdlc_complete = ((f1 ^ f2) & MAX_F_CNT); 820 } else 821 hdlc_complete = 0; 822 z1 = Read_hfc16_stable(l1->hw, A_Z1); 823 z2 = Read_hfc16(l1->hw, A_Z2); 824 z1 = (z1 - z2); 825 if (hdlc_complete) 826 z1++; 827 if (z1 < 0) 828 z1 += 384; 829 830 if (!z1) 831 break; 832 833 if (!(skb = bch->rx_skb)) { 834 if (! 835 (skb = 836 dev_alloc_skb((bch->mode == 837 L1_MODE_TRANS) ? z1 838 : (MAX_B_FRAME_SIZE + 3)))) { 839 printk(KERN_ERR 840 "HFC-4S/8S: Could not allocate B " 841 "channel receive buffer"); 842 return; 843 } 844 bch->rx_ptr = skb->data; 845 bch->rx_skb = skb; 846 } 847 848 skb->len = (bch->rx_ptr - skb->data) + z1; 849 850 /* HDLC length check */ 851 if ((bch->mode == L1_MODE_HDLC) && 852 ((hdlc_complete && (skb->len < 4)) || 853 (skb->len > (MAX_B_FRAME_SIZE + 3)))) { 854 855 skb->len = 0; 856 bch->rx_ptr = skb->data; 857 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ 858 wait_busy(l1->hw); 859 return; 860 } 861#ifndef HISAX_HFC4S8S_PCIMEM 862 SetRegAddr(l1->hw, A_FIFO_DATA0); 863#endif 864 865 while (z1 >= 4) { 866#ifdef HISAX_HFC4S8S_PCIMEM 867 *((unsigned long *) bch->rx_ptr) = 868 Read_hfc32(l1->hw, A_FIFO_DATA0); 869#else 870 *((unsigned long *) bch->rx_ptr) = 871 fRead_hfc32(l1->hw); 872#endif 873 bch->rx_ptr += 4; 874 z1 -= 4; 875 } 876 877 while (z1--) 878#ifdef HISAX_HFC4S8S_PCIMEM 879 *(bch->rx_ptr++) = Read_hfc8(l1->hw, A_FIFO_DATA0); 880#else 881 *(bch->rx_ptr++) = fRead_hfc8(l1->hw); 882#endif 883 884 if (hdlc_complete) { 885 /* increment f counter */ 886 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); 887 wait_busy(l1->hw); 888 889 /* hdlc crc check */ 890 bch->rx_ptr--; 891 if (*bch->rx_ptr) { 892 skb->len = 0; 893 bch->rx_ptr = skb->data; 894 continue; 895 } 896 skb->len -= 3; 897 } 898 if (hdlc_complete || (bch->mode == L1_MODE_TRANS)) { 899 bch->rx_skb = NULL; 900 bch->rx_ptr = NULL; 901 bch->b_if.ifc.l1l2(&bch->b_if.ifc, 902 PH_DATA | INDICATION, skb); 903 } 904 905 } while (1); 906} /* rx_b_frame */ 907 908/********************************************/ 909/* a D-frame has been/should be transmitted */ 910/********************************************/ 911static void 912tx_d_frame(struct hfc4s8s_l1 *l1p) 913{ 914 struct sk_buff *skb; 915 u_char f1, f2; 916 u_char *cp; 917 long cnt; 918 919 if (l1p->l1_state != 7) 920 return; 921 922 /* TX fifo */ 923 Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4)); 924 wait_busy(l1p->hw); 925 926 f1 = Read_hfc8(l1p->hw, A_F1); 927 f2 = Read_hfc8_stable(l1p->hw, A_F2); 928 929 if ((f1 ^ f2) & MAX_F_CNT) 930 return; /* fifo is still filled */ 931 932 if (l1p->tx_cnt > 0) { 933 cnt = l1p->tx_cnt; 934 l1p->tx_cnt = 0; 935 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DATA | CONFIRM, 936 (void *) cnt); 937 } 938 939 if ((skb = skb_dequeue(&l1p->d_tx_queue))) { 940 cp = skb->data; 941 cnt = skb->len; 942#ifndef HISAX_HFC4S8S_PCIMEM 943 SetRegAddr(l1p->hw, A_FIFO_DATA0); 944#endif 945 946 while (cnt >= 4) { 947#ifdef HISAX_HFC4S8S_PCIMEM 948 fWrite_hfc32(l1p->hw, A_FIFO_DATA0, 949 *(unsigned long *) cp); 950#else 951 SetRegAddr(l1p->hw, A_FIFO_DATA0); 952 fWrite_hfc32(l1p->hw, *(unsigned long *) cp); 953#endif 954 cp += 4; 955 cnt -= 4; 956 } 957 958#ifdef HISAX_HFC4S8S_PCIMEM 959 while (cnt--) 960 fWrite_hfc8(l1p->hw, A_FIFO_DATA0, *cp++); 961#else 962 while (cnt--) 963 fWrite_hfc8(l1p->hw, *cp++); 964#endif 965 966 l1p->tx_cnt = skb->truesize; 967 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ 968 wait_busy(l1p->hw); 969 970 dev_kfree_skb(skb); 971 } 972} /* tx_d_frame */ 973 974/******************************************************/ 975/* a B-frame may be transmitted (or is not completed) */ 976/******************************************************/ 977static void 978tx_b_frame(struct hfc4s8s_btype *bch) 979{ 980 struct sk_buff *skb; 981 struct hfc4s8s_l1 *l1 = bch->l1p; 982 u_char *cp; 983 int cnt, max, hdlc_num; 984 long ack_len = 0; 985 986 if (!l1->enabled || (bch->mode == L1_MODE_NULL)) 987 return; 988 989 /* TX fifo */ 990 Write_hfc8(l1->hw, R_FIFO, 991 (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2))); 992 wait_busy(l1->hw); 993 do { 994 995 if (bch->mode == L1_MODE_HDLC) { 996 hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT; 997 hdlc_num -= 998 (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT); 999 if (hdlc_num < 0) 1000 hdlc_num += 16; 1001 if (hdlc_num >= 15) 1002 break; /* fifo still filled up with hdlc frames */ 1003 } else 1004 hdlc_num = 0; 1005 1006 if (!(skb = bch->tx_skb)) { 1007 if (!(skb = skb_dequeue(&bch->tx_queue))) { 1008 l1->hw->mr.fifo_slow_timer_service[l1-> 1009 st_num] 1010 &= ~((bch->bchan == 1) ? 1 : 4); 1011 break; /* list empty */ 1012 } 1013 bch->tx_skb = skb; 1014 bch->tx_cnt = 0; 1015 } 1016 1017 if (!hdlc_num) 1018 l1->hw->mr.fifo_slow_timer_service[l1->st_num] |= 1019 ((bch->bchan == 1) ? 1 : 4); 1020 else 1021 l1->hw->mr.fifo_slow_timer_service[l1->st_num] &= 1022 ~((bch->bchan == 1) ? 1 : 4); 1023 1024 max = Read_hfc16_stable(l1->hw, A_Z2); 1025 max -= Read_hfc16(l1->hw, A_Z1); 1026 if (max <= 0) 1027 max += 384; 1028 max--; 1029 1030 if (max < 16) 1031 break; /* don't write to small amounts of bytes */ 1032 1033 cnt = skb->len - bch->tx_cnt; 1034 if (cnt > max) 1035 cnt = max; 1036 cp = skb->data + bch->tx_cnt; 1037 bch->tx_cnt += cnt; 1038 1039#ifndef HISAX_HFC4S8S_PCIMEM 1040 SetRegAddr(l1->hw, A_FIFO_DATA0); 1041#endif 1042 while (cnt >= 4) { 1043#ifdef HISAX_HFC4S8S_PCIMEM 1044 fWrite_hfc32(l1->hw, A_FIFO_DATA0, 1045 *(unsigned long *) cp); 1046#else 1047 fWrite_hfc32(l1->hw, *(unsigned long *) cp); 1048#endif 1049 cp += 4; 1050 cnt -= 4; 1051 } 1052 1053 while (cnt--) 1054#ifdef HISAX_HFC4S8S_PCIMEM 1055 fWrite_hfc8(l1->hw, A_FIFO_DATA0, *cp++); 1056#else 1057 fWrite_hfc8(l1->hw, *cp++); 1058#endif 1059 1060 if (bch->tx_cnt >= skb->len) { 1061 if (bch->mode == L1_MODE_HDLC) { 1062 /* increment f counter */ 1063 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); 1064 } 1065 ack_len += skb->truesize; 1066 bch->tx_skb = NULL; 1067 bch->tx_cnt = 0; 1068 dev_kfree_skb(skb); 1069 } else 1070 /* Re-Select */ 1071 Write_hfc8(l1->hw, R_FIFO, 1072 (l1->st_num * 8 + 1073 ((bch->bchan == 1) ? 0 : 2))); 1074 wait_busy(l1->hw); 1075 } while (1); 1076 1077 if (ack_len) 1078 bch->b_if.ifc.l1l2((struct hisax_if *) &bch->b_if, 1079 PH_DATA | CONFIRM, (void *) ack_len); 1080} /* tx_b_frame */ 1081 1082/*************************************/ 1083/* bottom half handler for interrupt */ 1084/*************************************/ 1085static void 1086hfc4s8s_bh(struct work_struct *work) 1087{ 1088 hfc4s8s_hw *hw = container_of(work, hfc4s8s_hw, tqueue); 1089 u_char b; 1090 struct hfc4s8s_l1 *l1p; 1091 volatile u_char *fifo_stat; 1092 int idx; 1093 1094 /* handle layer 1 state changes */ 1095 b = 1; 1096 l1p = hw->l1; 1097 while (b) { 1098 if ((b & hw->mr.r_irq_statech)) { 1099 /* reset l1 event */ 1100 hw->mr.r_irq_statech &= ~b; 1101 if (l1p->enabled) { 1102 if (l1p->nt_mode) { 1103 u_char oldstate = l1p->l1_state; 1104 1105 Write_hfc8(l1p->hw, R_ST_SEL, 1106 l1p->st_num); 1107 l1p->l1_state = 1108 Read_hfc8(l1p->hw, 1109 A_ST_RD_STA) & 0xf; 1110 1111 if ((oldstate == 3) 1112 && (l1p->l1_state != 3)) 1113 l1p->d_if.ifc.l1l2(&l1p-> 1114 d_if. 1115 ifc, 1116 PH_DEACTIVATE 1117 | 1118 INDICATION, 1119 NULL); 1120 1121 if (l1p->l1_state != 2) { 1122 del_timer(&l1p->l1_timer); 1123 if (l1p->l1_state == 3) { 1124 l1p->d_if.ifc. 1125 l1l2(&l1p-> 1126 d_if.ifc, 1127 PH_ACTIVATE 1128 | 1129 INDICATION, 1130 NULL); 1131 } 1132 } else { 1133 /* allow transition */ 1134 Write_hfc8(hw, A_ST_WR_STA, 1135 M_SET_G2_G3); 1136 mod_timer(&l1p->l1_timer, 1137 jiffies + 1138 L1_TIMER_T1); 1139 } 1140 printk(KERN_INFO 1141 "HFC-4S/8S: NT ch %d l1 state %d -> %d\n", 1142 l1p->st_num, oldstate, 1143 l1p->l1_state); 1144 } else { 1145 u_char oldstate = l1p->l1_state; 1146 1147 Write_hfc8(l1p->hw, R_ST_SEL, 1148 l1p->st_num); 1149 l1p->l1_state = 1150 Read_hfc8(l1p->hw, 1151 A_ST_RD_STA) & 0xf; 1152 1153 if (((l1p->l1_state == 3) && 1154 ((oldstate == 7) || 1155 (oldstate == 8))) || 1156 ((timer_pending 1157 (&l1p->l1_timer)) 1158 && (l1p->l1_state == 8))) { 1159 mod_timer(&l1p->l1_timer, 1160 L1_TIMER_T4 + 1161 jiffies); 1162 } else { 1163 if (l1p->l1_state == 7) { 1164 del_timer(&l1p-> 1165 l1_timer); 1166 l1p->d_if.ifc. 1167 l1l2(&l1p-> 1168 d_if.ifc, 1169 PH_ACTIVATE 1170 | 1171 INDICATION, 1172 NULL); 1173 tx_d_frame(l1p); 1174 } 1175 if (l1p->l1_state == 3) { 1176 if (oldstate != 3) 1177 l1p->d_if. 1178 ifc. 1179 l1l2 1180 (&l1p-> 1181 d_if. 1182 ifc, 1183 PH_DEACTIVATE 1184 | 1185 INDICATION, 1186 NULL); 1187 } 1188 } 1189 printk(KERN_INFO 1190 "HFC-4S/8S: TE %d ch %d l1 state %d -> %d\n", 1191 l1p->hw->cardnum, 1192 l1p->st_num, oldstate, 1193 l1p->l1_state); 1194 } 1195 } 1196 } 1197 b <<= 1; 1198 l1p++; 1199 } 1200 1201 /* now handle the fifos */ 1202 idx = 0; 1203 fifo_stat = hw->mr.r_irq_fifo_blx; 1204 l1p = hw->l1; 1205 while (idx < hw->driver_data.max_st_ports) { 1206 1207 if (hw->mr.timer_irq) { 1208 *fifo_stat |= hw->mr.fifo_rx_trans_enables[idx]; 1209 if (hw->fifo_sched_cnt <= 0) { 1210 *fifo_stat |= 1211 hw->mr.fifo_slow_timer_service[l1p-> 1212 st_num]; 1213 } 1214 } 1215 /* ignore fifo 6 (TX E fifo) */ 1216 *fifo_stat &= 0xff - 0x40; 1217 1218 while (*fifo_stat) { 1219 1220 if (!l1p->nt_mode) { 1221 /* RX Fifo has data to read */ 1222 if ((*fifo_stat & 0x20)) { 1223 *fifo_stat &= ~0x20; 1224 rx_d_frame(l1p, 0); 1225 } 1226 /* E Fifo has data to read */ 1227 if ((*fifo_stat & 0x80)) { 1228 *fifo_stat &= ~0x80; 1229 rx_d_frame(l1p, 1); 1230 } 1231 /* TX Fifo completed send */ 1232 if ((*fifo_stat & 0x10)) { 1233 *fifo_stat &= ~0x10; 1234 tx_d_frame(l1p); 1235 } 1236 } 1237 /* B1 RX Fifo has data to read */ 1238 if ((*fifo_stat & 0x2)) { 1239 *fifo_stat &= ~0x2; 1240 rx_b_frame(l1p->b_ch); 1241 } 1242 /* B1 TX Fifo has send completed */ 1243 if ((*fifo_stat & 0x1)) { 1244 *fifo_stat &= ~0x1; 1245 tx_b_frame(l1p->b_ch); 1246 } 1247 /* B2 RX Fifo has data to read */ 1248 if ((*fifo_stat & 0x8)) { 1249 *fifo_stat &= ~0x8; 1250 rx_b_frame(l1p->b_ch + 1); 1251 } 1252 /* B2 TX Fifo has send completed */ 1253 if ((*fifo_stat & 0x4)) { 1254 *fifo_stat &= ~0x4; 1255 tx_b_frame(l1p->b_ch + 1); 1256 } 1257 } 1258 fifo_stat++; 1259 l1p++; 1260 idx++; 1261 } 1262 1263 if (hw->fifo_sched_cnt <= 0) 1264 hw->fifo_sched_cnt += (1 << (7 - TRANS_TIMER_MODE)); 1265 hw->mr.timer_irq = 0; /* clear requested timer irq */ 1266} /* hfc4s8s_bh */ 1267 1268/*********************/ 1269/* interrupt handler */ 1270/*********************/ 1271static irqreturn_t 1272hfc4s8s_interrupt(int intno, void *dev_id) 1273{ 1274 hfc4s8s_hw *hw = dev_id; 1275 u_char b, ovr; 1276 volatile u_char *ovp; 1277 int idx; 1278 u_char old_ioreg; 1279 1280 if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN)) 1281 return IRQ_NONE; 1282 1283#ifndef HISAX_HFC4S8S_PCIMEM 1284 /* read current selected regsister */ 1285 old_ioreg = GetRegAddr(hw); 1286#endif 1287 1288 /* Layer 1 State change */ 1289 hw->mr.r_irq_statech |= 1290 (Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg); 1291 if (! 1292 (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA))) 1293&& !hw->mr.r_irq_statech) { 1294#ifndef HISAX_HFC4S8S_PCIMEM 1295 SetRegAddr(hw, old_ioreg); 1296#endif 1297 return IRQ_NONE; 1298 } 1299 1300 /* timer event */ 1301 if (Read_hfc8(hw, R_IRQ_MISC) & M_TI_IRQ) { 1302 hw->mr.timer_irq = 1; 1303 hw->fifo_sched_cnt--; 1304 } 1305 1306 /* FIFO event */ 1307 if ((ovr = Read_hfc8(hw, R_IRQ_OVIEW))) { 1308 hw->mr.r_irq_oview |= ovr; 1309 idx = R_IRQ_FIFO_BL0; 1310 ovp = hw->mr.r_irq_fifo_blx; 1311 while (ovr) { 1312 if ((ovr & 1)) { 1313 *ovp |= Read_hfc8(hw, idx); 1314 } 1315 ovp++; 1316 idx++; 1317 ovr >>= 1; 1318 } 1319 } 1320 1321 /* queue the request to allow other cards to interrupt */ 1322 schedule_work(&hw->tqueue); 1323 1324#ifndef HISAX_HFC4S8S_PCIMEM 1325 SetRegAddr(hw, old_ioreg); 1326#endif 1327 return IRQ_HANDLED; 1328} /* hfc4s8s_interrupt */ 1329 1330/***********************************************************************/ 1331/* reset the complete chip, don't release the chips irq but disable it */ 1332/***********************************************************************/ 1333static void 1334chipreset(hfc4s8s_hw * hw) 1335{ 1336 u_long flags; 1337 1338 spin_lock_irqsave(&hw->lock, flags); 1339 Write_hfc8(hw, R_CTRL, 0); /* use internal RAM */ 1340 Write_hfc8(hw, R_RAM_MISC, 0); /* 32k*8 RAM */ 1341 Write_hfc8(hw, R_FIFO_MD, 0); /* fifo mode 386 byte/fifo simple mode */ 1342 Write_hfc8(hw, R_CIRM, M_SRES); /* reset chip */ 1343 hw->mr.r_irq_ctrl = 0; /* interrupt is inactive */ 1344 spin_unlock_irqrestore(&hw->lock, flags); 1345 1346 udelay(3); 1347 Write_hfc8(hw, R_CIRM, 0); /* disable reset */ 1348 wait_busy(hw); 1349 1350 Write_hfc8(hw, R_PCM_MD0, M_PCM_MD); /* master mode */ 1351 Write_hfc8(hw, R_RAM_MISC, M_FZ_MD); /* transmit fifo option */ 1352 if (hw->driver_data.clock_mode == 1) 1353 Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK); /* PCM clk / 2 */ 1354 Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE); /* timer interval */ 1355 1356 memset(&hw->mr, 0, sizeof(hw->mr)); 1357} /* chipreset */ 1358 1359/********************************************/ 1360/* disable/enable hardware in nt or te mode */ 1361/********************************************/ 1362static void 1363hfc_hardware_enable(hfc4s8s_hw * hw, int enable, int nt_mode) 1364{ 1365 u_long flags; 1366 char if_name[40]; 1367 int i; 1368 1369 if (enable) { 1370 /* save system vars */ 1371 hw->nt_mode = nt_mode; 1372 1373 /* enable fifo and state irqs, but not global irq enable */ 1374 hw->mr.r_irq_ctrl = M_FIFO_IRQ; 1375 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); 1376 hw->mr.r_irqmsk_statchg = 0; 1377 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg); 1378 Write_hfc8(hw, R_PWM_MD, 0x80); 1379 Write_hfc8(hw, R_PWM1, 26); 1380 if (!nt_mode) 1381 Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC); 1382 1383 /* enable the line interfaces and fifos */ 1384 for (i = 0; i < hw->driver_data.max_st_ports; i++) { 1385 hw->mr.r_irqmsk_statchg |= (1 << i); 1386 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg); 1387 Write_hfc8(hw, R_ST_SEL, i); 1388 Write_hfc8(hw, A_ST_CLK_DLY, 1389 ((nt_mode) ? CLKDEL_NT : CLKDEL_TE)); 1390 hw->mr.r_ctrl0 = ((nt_mode) ? CTRL0_NT : CTRL0_TE); 1391 Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0); 1392 Write_hfc8(hw, A_ST_CTRL2, 3); 1393 Write_hfc8(hw, A_ST_WR_STA, 0); /* enable state machine */ 1394 1395 hw->l1[i].enabled = 1; 1396 hw->l1[i].nt_mode = nt_mode; 1397 1398 if (!nt_mode) { 1399 /* setup E-fifo */ 1400 Write_hfc8(hw, R_FIFO, i * 8 + 7); /* E fifo */ 1401 wait_busy(hw); 1402 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ 1403 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ 1404 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ 1405 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ 1406 wait_busy(hw); 1407 1408 /* setup D RX-fifo */ 1409 Write_hfc8(hw, R_FIFO, i * 8 + 5); /* RX fifo */ 1410 wait_busy(hw); 1411 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ 1412 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ 1413 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ 1414 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ 1415 wait_busy(hw); 1416 1417 /* setup D TX-fifo */ 1418 Write_hfc8(hw, R_FIFO, i * 8 + 4); /* TX fifo */ 1419 wait_busy(hw); 1420 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ 1421 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ 1422 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ 1423 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ 1424 wait_busy(hw); 1425 } 1426 1427 sprintf(if_name, "hfc4s8s_%d%d_", hw->cardnum, i); 1428 1429 if (hisax_register 1430 (&hw->l1[i].d_if, hw->l1[i].b_table, if_name, 1431 ((nt_mode) ? 3 : 2))) { 1432 1433 hw->l1[i].enabled = 0; 1434 hw->mr.r_irqmsk_statchg &= ~(1 << i); 1435 Write_hfc8(hw, R_SCI_MSK, 1436 hw->mr.r_irqmsk_statchg); 1437 printk(KERN_INFO 1438 "HFC-4S/8S: Unable to register S/T device %s, break\n", 1439 if_name); 1440 break; 1441 } 1442 } 1443 spin_lock_irqsave(&hw->lock, flags); 1444 hw->mr.r_irq_ctrl |= M_GLOB_IRQ_EN; 1445 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); 1446 spin_unlock_irqrestore(&hw->lock, flags); 1447 } else { 1448 /* disable hardware */ 1449 spin_lock_irqsave(&hw->lock, flags); 1450 hw->mr.r_irq_ctrl &= ~M_GLOB_IRQ_EN; 1451 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); 1452 spin_unlock_irqrestore(&hw->lock, flags); 1453 1454 for (i = hw->driver_data.max_st_ports - 1; i >= 0; i--) { 1455 hw->l1[i].enabled = 0; 1456 hisax_unregister(&hw->l1[i].d_if); 1457 del_timer(&hw->l1[i].l1_timer); 1458 skb_queue_purge(&hw->l1[i].d_tx_queue); 1459 skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue); 1460 skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue); 1461 } 1462 chipreset(hw); 1463 } 1464} /* hfc_hardware_enable */ 1465 1466/******************************************/ 1467/* disable memory mapped ports / io ports */ 1468/******************************************/ 1469static void 1470release_pci_ports(hfc4s8s_hw * hw) 1471{ 1472 pci_write_config_word(hw->pdev, PCI_COMMAND, 0); 1473#ifdef HISAX_HFC4S8S_PCIMEM 1474 if (hw->membase) 1475 iounmap((void *) hw->membase); 1476#else 1477 if (hw->iobase) 1478 release_region(hw->iobase, 8); 1479#endif 1480} 1481 1482/*****************************************/ 1483/* enable memory mapped ports / io ports */ 1484/*****************************************/ 1485static void 1486enable_pci_ports(hfc4s8s_hw * hw) 1487{ 1488#ifdef HISAX_HFC4S8S_PCIMEM 1489 pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_MEMIO); 1490#else 1491 pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO); 1492#endif 1493} 1494 1495/*************************************/ 1496/* initialise the HFC-4s/8s hardware */ 1497/* return 0 on success. */ 1498/*************************************/ 1499static int __devinit 1500setup_instance(hfc4s8s_hw * hw) 1501{ 1502 int err = -EIO; 1503 int i; 1504 1505 for (i = 0; i < HFC_MAX_ST; i++) { 1506 struct hfc4s8s_l1 *l1p; 1507 1508 l1p = hw->l1 + i; 1509 spin_lock_init(&l1p->lock); 1510 l1p->hw = hw; 1511 l1p->l1_timer.function = (void *) hfc_l1_timer; 1512 l1p->l1_timer.data = (long) (l1p); 1513 init_timer(&l1p->l1_timer); 1514 l1p->st_num = i; 1515 skb_queue_head_init(&l1p->d_tx_queue); 1516 l1p->d_if.ifc.priv = hw->l1 + i; 1517 l1p->d_if.ifc.l2l1 = (void *) dch_l2l1; 1518 1519 spin_lock_init(&l1p->b_ch[0].lock); 1520 l1p->b_ch[0].b_if.ifc.l2l1 = (void *) bch_l2l1; 1521 l1p->b_ch[0].b_if.ifc.priv = (void *) &l1p->b_ch[0]; 1522 l1p->b_ch[0].l1p = hw->l1 + i; 1523 l1p->b_ch[0].bchan = 1; 1524 l1p->b_table[0] = &l1p->b_ch[0].b_if; 1525 skb_queue_head_init(&l1p->b_ch[0].tx_queue); 1526 1527 spin_lock_init(&l1p->b_ch[1].lock); 1528 l1p->b_ch[1].b_if.ifc.l2l1 = (void *) bch_l2l1; 1529 l1p->b_ch[1].b_if.ifc.priv = (void *) &l1p->b_ch[1]; 1530 l1p->b_ch[1].l1p = hw->l1 + i; 1531 l1p->b_ch[1].bchan = 2; 1532 l1p->b_table[1] = &l1p->b_ch[1].b_if; 1533 skb_queue_head_init(&l1p->b_ch[1].tx_queue); 1534 } 1535 1536 enable_pci_ports(hw); 1537 chipreset(hw); 1538 1539 i = Read_hfc8(hw, R_CHIP_ID) >> CHIP_ID_SHIFT; 1540 if (i != hw->driver_data.chip_id) { 1541 printk(KERN_INFO 1542 "HFC-4S/8S: invalid chip id 0x%x instead of 0x%x, card ignored\n", 1543 i, hw->driver_data.chip_id); 1544 goto out; 1545 } 1546 1547 i = Read_hfc8(hw, R_CHIP_RV) & 0xf; 1548 if (!i) { 1549 printk(KERN_INFO 1550 "HFC-4S/8S: chip revision 0 not supported, card ignored\n"); 1551 goto out; 1552 } 1553 1554 INIT_WORK(&hw->tqueue, hfc4s8s_bh); 1555 1556 if (request_irq 1557 (hw->irq, hfc4s8s_interrupt, IRQF_SHARED, hw->card_name, hw)) { 1558 printk(KERN_INFO 1559 "HFC-4S/8S: unable to alloc irq %d, card ignored\n", 1560 hw->irq); 1561 goto out; 1562 } 1563#ifdef HISAX_HFC4S8S_PCIMEM 1564 printk(KERN_INFO 1565 "HFC-4S/8S: found PCI card at membase 0x%p, irq %d\n", 1566 hw->hw_membase, hw->irq); 1567#else 1568 printk(KERN_INFO 1569 "HFC-4S/8S: found PCI card at iobase 0x%x, irq %d\n", 1570 hw->iobase, hw->irq); 1571#endif 1572 1573 hfc_hardware_enable(hw, 1, 0); 1574 1575 return (0); 1576 1577 out: 1578 hw->irq = 0; 1579 release_pci_ports(hw); 1580 kfree(hw); 1581 return (err); 1582} 1583 1584/*****************************************/ 1585/* PCI hotplug interface: probe new card */ 1586/*****************************************/ 1587static int __devinit 1588hfc4s8s_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1589{ 1590 int err = -ENOMEM; 1591 hfc4s8s_param *driver_data = (hfc4s8s_param *) ent->driver_data; 1592 hfc4s8s_hw *hw; 1593 1594 if (!(hw = kzalloc(sizeof(hfc4s8s_hw), GFP_ATOMIC))) { 1595 printk(KERN_ERR "No kmem for HFC-4S/8S card\n"); 1596 return (err); 1597 } 1598 1599 hw->pdev = pdev; 1600 err = pci_enable_device(pdev); 1601 1602 if (err) 1603 goto out; 1604 1605 hw->cardnum = card_cnt; 1606 sprintf(hw->card_name, "hfc4s8s_%d", hw->cardnum); 1607 printk(KERN_INFO "HFC-4S/8S: found adapter %s (%s) at %s\n", 1608 driver_data->device_name, hw->card_name, pci_name(pdev)); 1609 1610 spin_lock_init(&hw->lock); 1611 1612 hw->driver_data = *driver_data; 1613 hw->irq = pdev->irq; 1614 hw->iobase = pci_resource_start(pdev, 0); 1615 1616#ifdef HISAX_HFC4S8S_PCIMEM 1617 hw->hw_membase = (u_char *) pci_resource_start(pdev, 1); 1618 hw->membase = ioremap((ulong) hw->hw_membase, 256); 1619#else 1620 if (!request_region(hw->iobase, 8, hw->card_name)) { 1621 printk(KERN_INFO 1622 "HFC-4S/8S: failed to rquest address space at 0x%04x\n", 1623 hw->iobase); 1624 goto out; 1625 } 1626#endif 1627 1628 pci_set_drvdata(pdev, hw); 1629 err = setup_instance(hw); 1630 if (!err) 1631 card_cnt++; 1632 return (err); 1633 1634 out: 1635 kfree(hw); 1636 return (err); 1637} 1638 1639/**************************************/ 1640/* PCI hotplug interface: remove card */ 1641/**************************************/ 1642static void __devexit 1643hfc4s8s_remove(struct pci_dev *pdev) 1644{ 1645 hfc4s8s_hw *hw = pci_get_drvdata(pdev); 1646 1647 printk(KERN_INFO "HFC-4S/8S: removing card %d\n", hw->cardnum); 1648 hfc_hardware_enable(hw, 0, 0); 1649 1650 if (hw->irq) 1651 free_irq(hw->irq, hw); 1652 hw->irq = 0; 1653 release_pci_ports(hw); 1654 1655 card_cnt--; 1656 pci_disable_device(pdev); 1657 kfree(hw); 1658 return; 1659} 1660 1661static struct pci_driver hfc4s8s_driver = { 1662 .name = "hfc4s8s_l1", 1663 .probe = hfc4s8s_probe, 1664 .remove = __devexit_p(hfc4s8s_remove), 1665 .id_table = hfc4s8s_ids, 1666}; 1667 1668/**********************/ 1669/* driver Module init */ 1670/**********************/ 1671static int __init 1672hfc4s8s_module_init(void) 1673{ 1674 int err; 1675 1676 printk(KERN_INFO 1677 "HFC-4S/8S: Layer 1 driver module for HFC-4S/8S isdn chips, %s\n", 1678 hfc4s8s_rev); 1679 printk(KERN_INFO 1680 "HFC-4S/8S: (C) 2003 Cornelius Consult, www.cornelius-consult.de\n"); 1681 1682 card_cnt = 0; 1683 1684 err = pci_register_driver(&hfc4s8s_driver); 1685 if (err < 0) { 1686 goto out; 1687 } 1688 printk(KERN_INFO "HFC-4S/8S: found %d cards\n", card_cnt); 1689 1690#if !defined(CONFIG_HOTPLUG) 1691 if (err == 0) { 1692 err = -ENODEV; 1693 pci_unregister_driver(&hfc4s8s_driver); 1694 goto out; 1695 } 1696#endif 1697 1698 return 0; 1699 out: 1700 return (err); 1701} /* hfc4s8s_init_hw */ 1702 1703/*************************************/ 1704/* driver module exit : */ 1705/* release the HFC-4s/8s hardware */ 1706/*************************************/ 1707static void __exit 1708hfc4s8s_module_exit(void) 1709{ 1710 pci_unregister_driver(&hfc4s8s_driver); 1711 printk(KERN_INFO "HFC-4S/8S: module removed\n"); 1712} /* hfc4s8s_release_hw */ 1713 1714module_init(hfc4s8s_module_init); 1715module_exit(hfc4s8s_module_exit); 1716