1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 * 33 * $Id: mthca_eq.c,v 1.1.1.1 2007/08/03 18:52:32 Exp $ 34 */ 35 36#include <linux/errno.h> 37#include <linux/interrupt.h> 38#include <linux/pci.h> 39 40#include "mthca_dev.h" 41#include "mthca_cmd.h" 42#include "mthca_config_reg.h" 43 44enum { 45 MTHCA_NUM_ASYNC_EQE = 0x80, 46 MTHCA_NUM_CMD_EQE = 0x80, 47 MTHCA_NUM_SPARE_EQE = 0x80, 48 MTHCA_EQ_ENTRY_SIZE = 0x20 49}; 50 51/* 52 * Must be packed because start is 64 bits but only aligned to 32 bits. 53 */ 54struct mthca_eq_context { 55 __be32 flags; 56 __be64 start; 57 __be32 logsize_usrpage; 58 __be32 tavor_pd; /* reserved for Arbel */ 59 u8 reserved1[3]; 60 u8 intr; 61 __be32 arbel_pd; /* lost_count for Tavor */ 62 __be32 lkey; 63 u32 reserved2[2]; 64 __be32 consumer_index; 65 __be32 producer_index; 66 u32 reserved3[4]; 67} __attribute__((packed)); 68 69#define MTHCA_EQ_STATUS_OK ( 0 << 28) 70#define MTHCA_EQ_STATUS_OVERFLOW ( 9 << 28) 71#define MTHCA_EQ_STATUS_WRITE_FAIL (10 << 28) 72#define MTHCA_EQ_OWNER_SW ( 0 << 24) 73#define MTHCA_EQ_OWNER_HW ( 1 << 24) 74#define MTHCA_EQ_FLAG_TR ( 1 << 18) 75#define MTHCA_EQ_FLAG_OI ( 1 << 17) 76#define MTHCA_EQ_STATE_ARMED ( 1 << 8) 77#define MTHCA_EQ_STATE_FIRED ( 2 << 8) 78#define MTHCA_EQ_STATE_ALWAYS_ARMED ( 3 << 8) 79#define MTHCA_EQ_STATE_ARBEL ( 8 << 8) 80 81enum { 82 MTHCA_EVENT_TYPE_COMP = 0x00, 83 MTHCA_EVENT_TYPE_PATH_MIG = 0x01, 84 MTHCA_EVENT_TYPE_COMM_EST = 0x02, 85 MTHCA_EVENT_TYPE_SQ_DRAINED = 0x03, 86 MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 87 MTHCA_EVENT_TYPE_SRQ_LIMIT = 0x14, 88 MTHCA_EVENT_TYPE_CQ_ERROR = 0x04, 89 MTHCA_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 90 MTHCA_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 91 MTHCA_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 92 MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 93 MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 94 MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 95 MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 96 MTHCA_EVENT_TYPE_PORT_CHANGE = 0x09, 97 MTHCA_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 98 MTHCA_EVENT_TYPE_ECC_DETECT = 0x0e, 99 MTHCA_EVENT_TYPE_CMD = 0x0a 100}; 101 102#define MTHCA_ASYNC_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_PATH_MIG) | \ 103 (1ULL << MTHCA_EVENT_TYPE_COMM_EST) | \ 104 (1ULL << MTHCA_EVENT_TYPE_SQ_DRAINED) | \ 105 (1ULL << MTHCA_EVENT_TYPE_CQ_ERROR) | \ 106 (1ULL << MTHCA_EVENT_TYPE_WQ_CATAS_ERROR) | \ 107 (1ULL << MTHCA_EVENT_TYPE_EEC_CATAS_ERROR) | \ 108 (1ULL << MTHCA_EVENT_TYPE_PATH_MIG_FAILED) | \ 109 (1ULL << MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 110 (1ULL << MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 111 (1ULL << MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR) | \ 112 (1ULL << MTHCA_EVENT_TYPE_PORT_CHANGE) | \ 113 (1ULL << MTHCA_EVENT_TYPE_ECC_DETECT)) 114#define MTHCA_SRQ_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 115 (1ULL << MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ 116 (1ULL << MTHCA_EVENT_TYPE_SRQ_LIMIT)) 117#define MTHCA_CMD_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_CMD) 118 119#define MTHCA_EQ_DB_INC_CI (1 << 24) 120#define MTHCA_EQ_DB_REQ_NOT (2 << 24) 121#define MTHCA_EQ_DB_DISARM_CQ (3 << 24) 122#define MTHCA_EQ_DB_SET_CI (4 << 24) 123#define MTHCA_EQ_DB_ALWAYS_ARM (5 << 24) 124 125struct mthca_eqe { 126 u8 reserved1; 127 u8 type; 128 u8 reserved2; 129 u8 subtype; 130 union { 131 u32 raw[6]; 132 struct { 133 __be32 cqn; 134 } __attribute__((packed)) comp; 135 struct { 136 u16 reserved1; 137 __be16 token; 138 u32 reserved2; 139 u8 reserved3[3]; 140 u8 status; 141 __be64 out_param; 142 } __attribute__((packed)) cmd; 143 struct { 144 __be32 qpn; 145 } __attribute__((packed)) qp; 146 struct { 147 __be32 srqn; 148 } __attribute__((packed)) srq; 149 struct { 150 __be32 cqn; 151 u32 reserved1; 152 u8 reserved2[3]; 153 u8 syndrome; 154 } __attribute__((packed)) cq_err; 155 struct { 156 u32 reserved1[2]; 157 __be32 port; 158 } __attribute__((packed)) port_change; 159 } event; 160 u8 reserved3[3]; 161 u8 owner; 162} __attribute__((packed)); 163 164#define MTHCA_EQ_ENTRY_OWNER_SW (0 << 7) 165#define MTHCA_EQ_ENTRY_OWNER_HW (1 << 7) 166 167static inline u64 async_mask(struct mthca_dev *dev) 168{ 169 return dev->mthca_flags & MTHCA_FLAG_SRQ ? 170 MTHCA_ASYNC_EVENT_MASK | MTHCA_SRQ_EVENT_MASK : 171 MTHCA_ASYNC_EVENT_MASK; 172} 173 174static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) 175{ 176 __be32 doorbell[2]; 177 178 doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_SET_CI | eq->eqn); 179 doorbell[1] = cpu_to_be32(ci & (eq->nent - 1)); 180 181 /* 182 * This barrier makes sure that all updates to ownership bits 183 * done by set_eqe_hw() hit memory before the consumer index 184 * is updated. set_eq_ci() allows the HCA to possibly write 185 * more EQ entries, and we want to avoid the exceedingly 186 * unlikely possibility of the HCA writing an entry and then 187 * having set_eqe_hw() overwrite the owner field. 188 */ 189 wmb(); 190 mthca_write64(doorbell, 191 dev->kar + MTHCA_EQ_DOORBELL, 192 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 193} 194 195static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) 196{ 197 /* See comment in tavor_set_eq_ci() above. */ 198 wmb(); 199 __raw_writel((__force u32) cpu_to_be32(ci), 200 dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8); 201 /* We still want ordering, just not swabbing, so add a barrier */ 202 mb(); 203} 204 205static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) 206{ 207 if (mthca_is_memfree(dev)) 208 arbel_set_eq_ci(dev, eq, ci); 209 else 210 tavor_set_eq_ci(dev, eq, ci); 211} 212 213static inline void tavor_eq_req_not(struct mthca_dev *dev, int eqn) 214{ 215 __be32 doorbell[2]; 216 217 doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_REQ_NOT | eqn); 218 doorbell[1] = 0; 219 220 mthca_write64(doorbell, 221 dev->kar + MTHCA_EQ_DOORBELL, 222 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 223} 224 225static inline void arbel_eq_req_not(struct mthca_dev *dev, u32 eqn_mask) 226{ 227 writel(eqn_mask, dev->eq_regs.arbel.eq_arm); 228} 229 230static inline void disarm_cq(struct mthca_dev *dev, int eqn, int cqn) 231{ 232 if (!mthca_is_memfree(dev)) { 233 __be32 doorbell[2]; 234 235 doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_DISARM_CQ | eqn); 236 doorbell[1] = cpu_to_be32(cqn); 237 238 mthca_write64(doorbell, 239 dev->kar + MTHCA_EQ_DOORBELL, 240 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 241 } 242} 243 244static inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry) 245{ 246 unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE; 247 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE; 248} 249 250static inline struct mthca_eqe* next_eqe_sw(struct mthca_eq *eq) 251{ 252 struct mthca_eqe* eqe; 253 eqe = get_eqe(eq, eq->cons_index); 254 return (MTHCA_EQ_ENTRY_OWNER_HW & eqe->owner) ? NULL : eqe; 255} 256 257static inline void set_eqe_hw(struct mthca_eqe *eqe) 258{ 259 eqe->owner = MTHCA_EQ_ENTRY_OWNER_HW; 260} 261 262static void port_change(struct mthca_dev *dev, int port, int active) 263{ 264 struct ib_event record; 265 266 mthca_dbg(dev, "Port change to %s for port %d\n", 267 active ? "active" : "down", port); 268 269 record.device = &dev->ib_dev; 270 record.event = active ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 271 record.element.port_num = port; 272 273 ib_dispatch_event(&record); 274} 275 276static int mthca_eq_int(struct mthca_dev *dev, struct mthca_eq *eq) 277{ 278 struct mthca_eqe *eqe; 279 int disarm_cqn; 280 int eqes_found = 0; 281 int set_ci = 0; 282 283 while ((eqe = next_eqe_sw(eq))) { 284 /* 285 * Make sure we read EQ entry contents after we've 286 * checked the ownership bit. 287 */ 288 rmb(); 289 290 switch (eqe->type) { 291 case MTHCA_EVENT_TYPE_COMP: 292 disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; 293 disarm_cq(dev, eq->eqn, disarm_cqn); 294 mthca_cq_completion(dev, disarm_cqn); 295 break; 296 297 case MTHCA_EVENT_TYPE_PATH_MIG: 298 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 299 IB_EVENT_PATH_MIG); 300 break; 301 302 case MTHCA_EVENT_TYPE_COMM_EST: 303 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 304 IB_EVENT_COMM_EST); 305 break; 306 307 case MTHCA_EVENT_TYPE_SQ_DRAINED: 308 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 309 IB_EVENT_SQ_DRAINED); 310 break; 311 312 case MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE: 313 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 314 IB_EVENT_QP_LAST_WQE_REACHED); 315 break; 316 317 case MTHCA_EVENT_TYPE_SRQ_LIMIT: 318 mthca_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff, 319 IB_EVENT_SRQ_LIMIT_REACHED); 320 break; 321 322 case MTHCA_EVENT_TYPE_WQ_CATAS_ERROR: 323 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 324 IB_EVENT_QP_FATAL); 325 break; 326 327 case MTHCA_EVENT_TYPE_PATH_MIG_FAILED: 328 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 329 IB_EVENT_PATH_MIG_ERR); 330 break; 331 332 case MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 333 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 334 IB_EVENT_QP_REQ_ERR); 335 break; 336 337 case MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR: 338 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 339 IB_EVENT_QP_ACCESS_ERR); 340 break; 341 342 case MTHCA_EVENT_TYPE_CMD: 343 mthca_cmd_event(dev, 344 be16_to_cpu(eqe->event.cmd.token), 345 eqe->event.cmd.status, 346 be64_to_cpu(eqe->event.cmd.out_param)); 347 break; 348 349 case MTHCA_EVENT_TYPE_PORT_CHANGE: 350 port_change(dev, 351 (be32_to_cpu(eqe->event.port_change.port) >> 28) & 3, 352 eqe->subtype == 0x4); 353 break; 354 355 case MTHCA_EVENT_TYPE_CQ_ERROR: 356 mthca_warn(dev, "CQ %s on CQN %06x\n", 357 eqe->event.cq_err.syndrome == 1 ? 358 "overrun" : "access violation", 359 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); 360 mthca_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn), 361 IB_EVENT_CQ_ERR); 362 break; 363 364 case MTHCA_EVENT_TYPE_EQ_OVERFLOW: 365 mthca_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); 366 break; 367 368 case MTHCA_EVENT_TYPE_EEC_CATAS_ERROR: 369 case MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR: 370 case MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR: 371 case MTHCA_EVENT_TYPE_ECC_DETECT: 372 default: 373 mthca_warn(dev, "Unhandled event %02x(%02x) on EQ %d\n", 374 eqe->type, eqe->subtype, eq->eqn); 375 break; 376 }; 377 378 set_eqe_hw(eqe); 379 ++eq->cons_index; 380 eqes_found = 1; 381 ++set_ci; 382 383 /* 384 * The HCA will think the queue has overflowed if we 385 * don't tell it we've been processing events. We 386 * create our EQs with MTHCA_NUM_SPARE_EQE extra 387 * entries, so we must update our consumer index at 388 * least that often. 389 */ 390 if (unlikely(set_ci >= MTHCA_NUM_SPARE_EQE)) { 391 /* 392 * Conditional on hca_type is OK here because 393 * this is a rare case, not the fast path. 394 */ 395 set_eq_ci(dev, eq, eq->cons_index); 396 set_ci = 0; 397 } 398 } 399 400 /* 401 * Rely on caller to set consumer index so that we don't have 402 * to test hca_type in our interrupt handling fast path. 403 */ 404 return eqes_found; 405} 406 407static irqreturn_t mthca_tavor_interrupt(int irq, void *dev_ptr) 408{ 409 struct mthca_dev *dev = dev_ptr; 410 u32 ecr; 411 int i; 412 413 if (dev->eq_table.clr_mask) 414 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); 415 416 ecr = readl(dev->eq_regs.tavor.ecr_base + 4); 417 if (!ecr) 418 return IRQ_NONE; 419 420 writel(ecr, dev->eq_regs.tavor.ecr_base + 421 MTHCA_ECR_CLR_BASE - MTHCA_ECR_BASE + 4); 422 423 for (i = 0; i < MTHCA_NUM_EQ; ++i) 424 if (ecr & dev->eq_table.eq[i].eqn_mask) { 425 if (mthca_eq_int(dev, &dev->eq_table.eq[i])) 426 tavor_set_eq_ci(dev, &dev->eq_table.eq[i], 427 dev->eq_table.eq[i].cons_index); 428 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn); 429 } 430 431 return IRQ_HANDLED; 432} 433 434static irqreturn_t mthca_tavor_msi_x_interrupt(int irq, void *eq_ptr) 435{ 436 struct mthca_eq *eq = eq_ptr; 437 struct mthca_dev *dev = eq->dev; 438 439 mthca_eq_int(dev, eq); 440 tavor_set_eq_ci(dev, eq, eq->cons_index); 441 tavor_eq_req_not(dev, eq->eqn); 442 443 /* MSI-X vectors always belong to us */ 444 return IRQ_HANDLED; 445} 446 447static irqreturn_t mthca_arbel_interrupt(int irq, void *dev_ptr) 448{ 449 struct mthca_dev *dev = dev_ptr; 450 int work = 0; 451 int i; 452 453 if (dev->eq_table.clr_mask) 454 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); 455 456 for (i = 0; i < MTHCA_NUM_EQ; ++i) 457 if (mthca_eq_int(dev, &dev->eq_table.eq[i])) { 458 work = 1; 459 arbel_set_eq_ci(dev, &dev->eq_table.eq[i], 460 dev->eq_table.eq[i].cons_index); 461 } 462 463 arbel_eq_req_not(dev, dev->eq_table.arm_mask); 464 465 return IRQ_RETVAL(work); 466} 467 468static irqreturn_t mthca_arbel_msi_x_interrupt(int irq, void *eq_ptr) 469{ 470 struct mthca_eq *eq = eq_ptr; 471 struct mthca_dev *dev = eq->dev; 472 473 mthca_eq_int(dev, eq); 474 arbel_set_eq_ci(dev, eq, eq->cons_index); 475 arbel_eq_req_not(dev, eq->eqn_mask); 476 477 /* MSI-X vectors always belong to us */ 478 return IRQ_HANDLED; 479} 480 481static int mthca_create_eq(struct mthca_dev *dev, 482 int nent, 483 u8 intr, 484 struct mthca_eq *eq) 485{ 486 int npages; 487 u64 *dma_list = NULL; 488 dma_addr_t t; 489 struct mthca_mailbox *mailbox; 490 struct mthca_eq_context *eq_context; 491 int err = -ENOMEM; 492 int i; 493 u8 status; 494 495 eq->dev = dev; 496 eq->nent = roundup_pow_of_two(max(nent, 2)); 497 npages = ALIGN(eq->nent * MTHCA_EQ_ENTRY_SIZE, PAGE_SIZE) / PAGE_SIZE; 498 499 eq->page_list = kmalloc(npages * sizeof *eq->page_list, 500 GFP_KERNEL); 501 if (!eq->page_list) 502 goto err_out; 503 504 for (i = 0; i < npages; ++i) 505 eq->page_list[i].buf = NULL; 506 507 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL); 508 if (!dma_list) 509 goto err_out_free; 510 511 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 512 if (IS_ERR(mailbox)) 513 goto err_out_free; 514 eq_context = mailbox->buf; 515 516 for (i = 0; i < npages; ++i) { 517 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev, 518 PAGE_SIZE, &t, GFP_KERNEL); 519 if (!eq->page_list[i].buf) 520 goto err_out_free_pages; 521 522 dma_list[i] = t; 523 pci_unmap_addr_set(&eq->page_list[i], mapping, t); 524 525 memset(eq->page_list[i].buf, 0, PAGE_SIZE); 526 } 527 528 for (i = 0; i < eq->nent; ++i) 529 set_eqe_hw(get_eqe(eq, i)); 530 531 eq->eqn = mthca_alloc(&dev->eq_table.alloc); 532 if (eq->eqn == -1) 533 goto err_out_free_pages; 534 535 err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num, 536 dma_list, PAGE_SHIFT, npages, 537 0, npages * PAGE_SIZE, 538 MTHCA_MPT_FLAG_LOCAL_WRITE | 539 MTHCA_MPT_FLAG_LOCAL_READ, 540 &eq->mr); 541 if (err) 542 goto err_out_free_eq; 543 544 memset(eq_context, 0, sizeof *eq_context); 545 eq_context->flags = cpu_to_be32(MTHCA_EQ_STATUS_OK | 546 MTHCA_EQ_OWNER_HW | 547 MTHCA_EQ_STATE_ARMED | 548 MTHCA_EQ_FLAG_TR); 549 if (mthca_is_memfree(dev)) 550 eq_context->flags |= cpu_to_be32(MTHCA_EQ_STATE_ARBEL); 551 552 eq_context->logsize_usrpage = cpu_to_be32((ffs(eq->nent) - 1) << 24); 553 if (mthca_is_memfree(dev)) { 554 eq_context->arbel_pd = cpu_to_be32(dev->driver_pd.pd_num); 555 } else { 556 eq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index); 557 eq_context->tavor_pd = cpu_to_be32(dev->driver_pd.pd_num); 558 } 559 eq_context->intr = intr; 560 eq_context->lkey = cpu_to_be32(eq->mr.ibmr.lkey); 561 562 err = mthca_SW2HW_EQ(dev, mailbox, eq->eqn, &status); 563 if (err) { 564 mthca_warn(dev, "SW2HW_EQ failed (%d)\n", err); 565 goto err_out_free_mr; 566 } 567 if (status) { 568 mthca_warn(dev, "SW2HW_EQ returned status 0x%02x\n", 569 status); 570 err = -EINVAL; 571 goto err_out_free_mr; 572 } 573 574 kfree(dma_list); 575 mthca_free_mailbox(dev, mailbox); 576 577 eq->eqn_mask = swab32(1 << eq->eqn); 578 eq->cons_index = 0; 579 580 dev->eq_table.arm_mask |= eq->eqn_mask; 581 582 mthca_dbg(dev, "Allocated EQ %d with %d entries\n", 583 eq->eqn, eq->nent); 584 585 return err; 586 587 err_out_free_mr: 588 mthca_free_mr(dev, &eq->mr); 589 590 err_out_free_eq: 591 mthca_free(&dev->eq_table.alloc, eq->eqn); 592 593 err_out_free_pages: 594 for (i = 0; i < npages; ++i) 595 if (eq->page_list[i].buf) 596 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, 597 eq->page_list[i].buf, 598 pci_unmap_addr(&eq->page_list[i], 599 mapping)); 600 601 mthca_free_mailbox(dev, mailbox); 602 603 err_out_free: 604 kfree(eq->page_list); 605 kfree(dma_list); 606 607 err_out: 608 return err; 609} 610 611static void mthca_free_eq(struct mthca_dev *dev, 612 struct mthca_eq *eq) 613{ 614 struct mthca_mailbox *mailbox; 615 int err; 616 u8 status; 617 int npages = (eq->nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) / 618 PAGE_SIZE; 619 int i; 620 621 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 622 if (IS_ERR(mailbox)) 623 return; 624 625 err = mthca_HW2SW_EQ(dev, mailbox, eq->eqn, &status); 626 if (err) 627 mthca_warn(dev, "HW2SW_EQ failed (%d)\n", err); 628 if (status) 629 mthca_warn(dev, "HW2SW_EQ returned status 0x%02x\n", status); 630 631 dev->eq_table.arm_mask &= ~eq->eqn_mask; 632 633 if (0) { 634 mthca_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn); 635 for (i = 0; i < sizeof (struct mthca_eq_context) / 4; ++i) { 636 if (i % 4 == 0) 637 printk("[%02x] ", i * 4); 638 printk(" %08x", be32_to_cpup(mailbox->buf + i * 4)); 639 if ((i + 1) % 4 == 0) 640 printk("\n"); 641 } 642 } 643 644 mthca_free_mr(dev, &eq->mr); 645 for (i = 0; i < npages; ++i) 646 pci_free_consistent(dev->pdev, PAGE_SIZE, 647 eq->page_list[i].buf, 648 pci_unmap_addr(&eq->page_list[i], mapping)); 649 650 kfree(eq->page_list); 651 mthca_free_mailbox(dev, mailbox); 652} 653 654static void mthca_free_irqs(struct mthca_dev *dev) 655{ 656 int i; 657 658 if (dev->eq_table.have_irq) 659 free_irq(dev->pdev->irq, dev); 660 for (i = 0; i < MTHCA_NUM_EQ; ++i) 661 if (dev->eq_table.eq[i].have_irq) 662 free_irq(dev->eq_table.eq[i].msi_x_vector, 663 dev->eq_table.eq + i); 664} 665 666static int mthca_map_reg(struct mthca_dev *dev, 667 unsigned long offset, unsigned long size, 668 void __iomem **map) 669{ 670 unsigned long base = pci_resource_start(dev->pdev, 0); 671 672 if (!request_mem_region(base + offset, size, DRV_NAME)) 673 return -EBUSY; 674 675 *map = ioremap(base + offset, size); 676 if (!*map) { 677 release_mem_region(base + offset, size); 678 return -ENOMEM; 679 } 680 681 return 0; 682} 683 684static void mthca_unmap_reg(struct mthca_dev *dev, unsigned long offset, 685 unsigned long size, void __iomem *map) 686{ 687 unsigned long base = pci_resource_start(dev->pdev, 0); 688 689 release_mem_region(base + offset, size); 690 iounmap(map); 691} 692 693static int mthca_map_eq_regs(struct mthca_dev *dev) 694{ 695 if (mthca_is_memfree(dev)) { 696 /* 697 * We assume that the EQ arm and EQ set CI registers 698 * fall within the first BAR. We can't trust the 699 * values firmware gives us, since those addresses are 700 * valid on the HCA's side of the PCI bus but not 701 * necessarily the host side. 702 */ 703 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) & 704 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE, 705 &dev->clr_base)) { 706 mthca_err(dev, "Couldn't map interrupt clear register, " 707 "aborting.\n"); 708 return -ENOMEM; 709 } 710 711 /* 712 * Add 4 because we limit ourselves to EQs 0 ... 31, 713 * so we only need the low word of the register. 714 */ 715 if (mthca_map_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) & 716 dev->fw.arbel.eq_arm_base) + 4, 4, 717 &dev->eq_regs.arbel.eq_arm)) { 718 mthca_err(dev, "Couldn't map EQ arm register, aborting.\n"); 719 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) & 720 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE, 721 dev->clr_base); 722 return -ENOMEM; 723 } 724 725 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) & 726 dev->fw.arbel.eq_set_ci_base, 727 MTHCA_EQ_SET_CI_SIZE, 728 &dev->eq_regs.arbel.eq_set_ci_base)) { 729 mthca_err(dev, "Couldn't map EQ CI register, aborting.\n"); 730 mthca_unmap_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) & 731 dev->fw.arbel.eq_arm_base) + 4, 4, 732 dev->eq_regs.arbel.eq_arm); 733 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) & 734 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE, 735 dev->clr_base); 736 return -ENOMEM; 737 } 738 } else { 739 if (mthca_map_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE, 740 &dev->clr_base)) { 741 mthca_err(dev, "Couldn't map interrupt clear register, " 742 "aborting.\n"); 743 return -ENOMEM; 744 } 745 746 if (mthca_map_reg(dev, MTHCA_ECR_BASE, 747 MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE, 748 &dev->eq_regs.tavor.ecr_base)) { 749 mthca_err(dev, "Couldn't map ecr register, " 750 "aborting.\n"); 751 mthca_unmap_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE, 752 dev->clr_base); 753 return -ENOMEM; 754 } 755 } 756 757 return 0; 758 759} 760 761static void mthca_unmap_eq_regs(struct mthca_dev *dev) 762{ 763 if (mthca_is_memfree(dev)) { 764 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) & 765 dev->fw.arbel.eq_set_ci_base, 766 MTHCA_EQ_SET_CI_SIZE, 767 dev->eq_regs.arbel.eq_set_ci_base); 768 mthca_unmap_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) & 769 dev->fw.arbel.eq_arm_base) + 4, 4, 770 dev->eq_regs.arbel.eq_arm); 771 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) & 772 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE, 773 dev->clr_base); 774 } else { 775 mthca_unmap_reg(dev, MTHCA_ECR_BASE, 776 MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE, 777 dev->eq_regs.tavor.ecr_base); 778 mthca_unmap_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE, 779 dev->clr_base); 780 } 781} 782 783int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt) 784{ 785 int ret; 786 u8 status; 787 788 /* 789 * We assume that mapping one page is enough for the whole EQ 790 * context table. This is fine with all current HCAs, because 791 * we only use 32 EQs and each EQ uses 32 bytes of context 792 * memory, or 1 KB total. 793 */ 794 dev->eq_table.icm_virt = icm_virt; 795 dev->eq_table.icm_page = alloc_page(GFP_HIGHUSER); 796 if (!dev->eq_table.icm_page) 797 return -ENOMEM; 798 dev->eq_table.icm_dma = pci_map_page(dev->pdev, dev->eq_table.icm_page, 0, 799 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 800 if (pci_dma_mapping_error(dev->eq_table.icm_dma)) { 801 __free_page(dev->eq_table.icm_page); 802 return -ENOMEM; 803 } 804 805 ret = mthca_MAP_ICM_page(dev, dev->eq_table.icm_dma, icm_virt, &status); 806 if (!ret && status) 807 ret = -EINVAL; 808 if (ret) { 809 pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE, 810 PCI_DMA_BIDIRECTIONAL); 811 __free_page(dev->eq_table.icm_page); 812 } 813 814 return ret; 815} 816 817void mthca_unmap_eq_icm(struct mthca_dev *dev) 818{ 819 u8 status; 820 821 mthca_UNMAP_ICM(dev, dev->eq_table.icm_virt, 1, &status); 822 pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE, 823 PCI_DMA_BIDIRECTIONAL); 824 __free_page(dev->eq_table.icm_page); 825} 826 827int mthca_init_eq_table(struct mthca_dev *dev) 828{ 829 int err; 830 u8 status; 831 u8 intr; 832 int i; 833 834 err = mthca_alloc_init(&dev->eq_table.alloc, 835 dev->limits.num_eqs, 836 dev->limits.num_eqs - 1, 837 dev->limits.reserved_eqs); 838 if (err) 839 return err; 840 841 err = mthca_map_eq_regs(dev); 842 if (err) 843 goto err_out_free; 844 845 if (dev->mthca_flags & MTHCA_FLAG_MSI || 846 dev->mthca_flags & MTHCA_FLAG_MSI_X) { 847 dev->eq_table.clr_mask = 0; 848 } else { 849 dev->eq_table.clr_mask = 850 swab32(1 << (dev->eq_table.inta_pin & 31)); 851 dev->eq_table.clr_int = dev->clr_base + 852 (dev->eq_table.inta_pin < 32 ? 4 : 0); 853 } 854 855 dev->eq_table.arm_mask = 0; 856 857 intr = (dev->mthca_flags & MTHCA_FLAG_MSI) ? 858 128 : dev->eq_table.inta_pin; 859 860 err = mthca_create_eq(dev, dev->limits.num_cqs + MTHCA_NUM_SPARE_EQE, 861 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 128 : intr, 862 &dev->eq_table.eq[MTHCA_EQ_COMP]); 863 if (err) 864 goto err_out_unmap; 865 866 err = mthca_create_eq(dev, MTHCA_NUM_ASYNC_EQE + MTHCA_NUM_SPARE_EQE, 867 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 129 : intr, 868 &dev->eq_table.eq[MTHCA_EQ_ASYNC]); 869 if (err) 870 goto err_out_comp; 871 872 err = mthca_create_eq(dev, MTHCA_NUM_CMD_EQE + MTHCA_NUM_SPARE_EQE, 873 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 130 : intr, 874 &dev->eq_table.eq[MTHCA_EQ_CMD]); 875 if (err) 876 goto err_out_async; 877 878 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) { 879 static const char *eq_name[] = { 880 [MTHCA_EQ_COMP] = DRV_NAME " (comp)", 881 [MTHCA_EQ_ASYNC] = DRV_NAME " (async)", 882 [MTHCA_EQ_CMD] = DRV_NAME " (cmd)" 883 }; 884 885 for (i = 0; i < MTHCA_NUM_EQ; ++i) { 886 err = request_irq(dev->eq_table.eq[i].msi_x_vector, 887 mthca_is_memfree(dev) ? 888 mthca_arbel_msi_x_interrupt : 889 mthca_tavor_msi_x_interrupt, 890 0, eq_name[i], dev->eq_table.eq + i); 891 if (err) 892 goto err_out_cmd; 893 dev->eq_table.eq[i].have_irq = 1; 894 } 895 } else { 896 err = request_irq(dev->pdev->irq, 897 mthca_is_memfree(dev) ? 898 mthca_arbel_interrupt : 899 mthca_tavor_interrupt, 900 IRQF_SHARED, DRV_NAME, dev); 901 if (err) 902 goto err_out_cmd; 903 dev->eq_table.have_irq = 1; 904 } 905 906 err = mthca_MAP_EQ(dev, async_mask(dev), 907 0, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status); 908 if (err) 909 mthca_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", 910 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, err); 911 if (status) 912 mthca_warn(dev, "MAP_EQ for async EQ %d returned status 0x%02x\n", 913 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, status); 914 915 err = mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK, 916 0, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status); 917 if (err) 918 mthca_warn(dev, "MAP_EQ for cmd EQ %d failed (%d)\n", 919 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, err); 920 if (status) 921 mthca_warn(dev, "MAP_EQ for cmd EQ %d returned status 0x%02x\n", 922 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, status); 923 924 for (i = 0; i < MTHCA_NUM_EQ; ++i) 925 if (mthca_is_memfree(dev)) 926 arbel_eq_req_not(dev, dev->eq_table.eq[i].eqn_mask); 927 else 928 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn); 929 930 return 0; 931 932err_out_cmd: 933 mthca_free_irqs(dev); 934 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_CMD]); 935 936err_out_async: 937 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_ASYNC]); 938 939err_out_comp: 940 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_COMP]); 941 942err_out_unmap: 943 mthca_unmap_eq_regs(dev); 944 945err_out_free: 946 mthca_alloc_cleanup(&dev->eq_table.alloc); 947 return err; 948} 949 950void mthca_cleanup_eq_table(struct mthca_dev *dev) 951{ 952 u8 status; 953 int i; 954 955 mthca_free_irqs(dev); 956 957 mthca_MAP_EQ(dev, async_mask(dev), 958 1, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status); 959 mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK, 960 1, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status); 961 962 for (i = 0; i < MTHCA_NUM_EQ; ++i) 963 mthca_free_eq(dev, &dev->eq_table.eq[i]); 964 965 mthca_unmap_eq_regs(dev); 966 967 mthca_alloc_cleanup(&dev->eq_table.alloc); 968} 969