1#ifndef _IPATH_KERNEL_H 2#define _IPATH_KERNEL_H 3/* 4 * Copyright (c) 2006 QLogic, Inc. All rights reserved. 5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36/* 37 * This header file is the base header file for infinipath kernel code 38 * ipath_user.h serves a similar purpose for user code. 39 */ 40 41#include <linux/interrupt.h> 42#include <linux/pci.h> 43#include <linux/dma-mapping.h> 44#include <asm/io.h> 45 46#include "ipath_common.h" 47#include "ipath_debug.h" 48#include "ipath_registers.h" 49 50/* only s/w major version of InfiniPath we can handle */ 51#define IPATH_CHIP_VERS_MAJ 2U 52 53/* don't care about this except printing */ 54#define IPATH_CHIP_VERS_MIN 0U 55 56/* temporary, maybe always */ 57extern struct infinipath_stats ipath_stats; 58 59#define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ 60 61struct ipath_portdata { 62 void **port_rcvegrbuf; 63 dma_addr_t *port_rcvegrbuf_phys; 64 /* rcvhdrq base, needs mmap before useful */ 65 void *port_rcvhdrq; 66 /* kernel virtual address where hdrqtail is updated */ 67 void *port_rcvhdrtail_kvaddr; 68 /* 69 * temp buffer for expected send setup, allocated at open, instead 70 * of each setup call 71 */ 72 void *port_tid_pg_list; 73 /* when waiting for rcv or pioavail */ 74 wait_queue_head_t port_wait; 75 /* 76 * rcvegr bufs base, physical, must fit 77 * in 44 bits so 32 bit programs mmap64 44 bit works) 78 */ 79 dma_addr_t port_rcvegr_phys; 80 /* mmap of hdrq, must fit in 44 bits */ 81 dma_addr_t port_rcvhdrq_phys; 82 dma_addr_t port_rcvhdrqtailaddr_phys; 83 /* 84 * number of opens (including slave subports) on this instance 85 * (ignoring forks, dup, etc. for now) 86 */ 87 int port_cnt; 88 /* 89 * how much space to leave at start of eager TID entries for 90 * protocol use, on each TID 91 */ 92 /* instead of calculating it */ 93 unsigned port_port; 94 /* non-zero if port is being shared. */ 95 u16 port_subport_cnt; 96 /* non-zero if port is being shared. */ 97 u16 port_subport_id; 98 /* chip offset of PIO buffers for this port */ 99 u32 port_piobufs; 100 /* how many alloc_pages() chunks in port_rcvegrbuf_pages */ 101 u32 port_rcvegrbuf_chunks; 102 /* how many egrbufs per chunk */ 103 u32 port_rcvegrbufs_perchunk; 104 /* order for port_rcvegrbuf_pages */ 105 size_t port_rcvegrbuf_size; 106 /* rcvhdrq size (for freeing) */ 107 size_t port_rcvhdrq_size; 108 /* next expected TID to check when looking for free */ 109 u32 port_tidcursor; 110 /* next expected TID to check */ 111 unsigned long port_flag; 112 /* WAIT_RCV that timed out, no interrupt */ 113 u32 port_rcvwait_to; 114 /* WAIT_PIO that timed out, no interrupt */ 115 u32 port_piowait_to; 116 /* WAIT_RCV already happened, no wait */ 117 u32 port_rcvnowait; 118 /* WAIT_PIO already happened, no wait */ 119 u32 port_pionowait; 120 /* total number of rcvhdrqfull errors */ 121 u32 port_hdrqfull; 122 /* pid of process using this port */ 123 pid_t port_pid; 124 /* same size as task_struct .comm[] */ 125 char port_comm[16]; 126 /* pkeys set by this use of this port */ 127 u16 port_pkeys[4]; 128 /* so file ops can get at unit */ 129 struct ipath_devdata *port_dd; 130 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ 131 void *subport_uregbase; 132 /* An array of pages for the eager receive buffers * N */ 133 void *subport_rcvegrbuf; 134 /* An array of pages for the eager header queue entries * N */ 135 void *subport_rcvhdr_base; 136 /* The version of the library which opened this port */ 137 u32 userversion; 138 /* Bitmask of active slaves */ 139 u32 active_slaves; 140}; 141 142struct sk_buff; 143 144/* 145 * control information for layered drivers 146 */ 147struct _ipath_layer { 148 void *l_arg; 149}; 150 151struct ipath_skbinfo { 152 struct sk_buff *skb; 153 dma_addr_t phys; 154}; 155 156struct ipath_devdata { 157 struct list_head ipath_list; 158 159 struct ipath_kregs const *ipath_kregs; 160 struct ipath_cregs const *ipath_cregs; 161 162 /* mem-mapped pointer to base of chip regs */ 163 u64 __iomem *ipath_kregbase; 164 /* end of mem-mapped chip space; range checking */ 165 u64 __iomem *ipath_kregend; 166 /* physical address of chip for io_remap, etc. */ 167 unsigned long ipath_physaddr; 168 /* base of memory alloced for ipath_kregbase, for free */ 169 u64 *ipath_kregalloc; 170 /* 171 * virtual address where port0 rcvhdrqtail updated for this unit. 172 * only written to by the chip, not the driver. 173 */ 174 volatile __le64 *ipath_hdrqtailptr; 175 /* ipath_cfgports pointers */ 176 struct ipath_portdata **ipath_pd; 177 /* sk_buffs used by port 0 eager receive queue */ 178 struct ipath_skbinfo *ipath_port0_skbinfo; 179 /* kvirt address of 1st 2k pio buffer */ 180 void __iomem *ipath_pio2kbase; 181 /* kvirt address of 1st 4k pio buffer */ 182 void __iomem *ipath_pio4kbase; 183 /* 184 * points to area where PIOavail registers will be DMA'ed. 185 * Has to be on a page of it's own, because the page will be 186 * mapped into user program space. This copy is *ONLY* ever 187 * written by DMA, not by the driver! Need a copy per device 188 * when we get to multiple devices 189 */ 190 volatile __le64 *ipath_pioavailregs_dma; 191 /* physical address where updates occur */ 192 dma_addr_t ipath_pioavailregs_phys; 193 struct _ipath_layer ipath_layer; 194 /* setup intr */ 195 int (*ipath_f_intrsetup)(struct ipath_devdata *); 196 /* setup on-chip bus config */ 197 int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *); 198 /* hard reset chip */ 199 int (*ipath_f_reset)(struct ipath_devdata *); 200 int (*ipath_f_get_boardname)(struct ipath_devdata *, char *, 201 size_t); 202 void (*ipath_f_init_hwerrors)(struct ipath_devdata *); 203 void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *, 204 size_t); 205 void (*ipath_f_quiet_serdes)(struct ipath_devdata *); 206 int (*ipath_f_bringup_serdes)(struct ipath_devdata *); 207 int (*ipath_f_early_init)(struct ipath_devdata *); 208 void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned); 209 void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*, 210 u32, unsigned long); 211 void (*ipath_f_tidtemplate)(struct ipath_devdata *); 212 void (*ipath_f_cleanup)(struct ipath_devdata *); 213 void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64); 214 /* fill out chip-specific fields */ 215 int (*ipath_f_get_base_info)(struct ipath_portdata *, void *); 216 /* free irq */ 217 void (*ipath_f_free_irq)(struct ipath_devdata *); 218 struct ipath_ibdev *verbs_dev; 219 struct timer_list verbs_timer; 220 /* total dwords sent (summed from counter) */ 221 u64 ipath_sword; 222 /* total dwords rcvd (summed from counter) */ 223 u64 ipath_rword; 224 /* total packets sent (summed from counter) */ 225 u64 ipath_spkts; 226 /* total packets rcvd (summed from counter) */ 227 u64 ipath_rpkts; 228 /* ipath_statusp initially points to this. */ 229 u64 _ipath_status; 230 /* GUID for this interface, in network order */ 231 __be64 ipath_guid; 232 /* 233 * aggregrate of error bits reported since last cleared, for 234 * limiting of error reporting 235 */ 236 ipath_err_t ipath_lasterror; 237 /* 238 * aggregrate of error bits reported since last cleared, for 239 * limiting of hwerror reporting 240 */ 241 ipath_err_t ipath_lasthwerror; 242 /* 243 * errors masked because they occur too fast, also includes errors 244 * that are always ignored (ipath_ignorederrs) 245 */ 246 ipath_err_t ipath_maskederrs; 247 /* time in jiffies at which to re-enable maskederrs */ 248 unsigned long ipath_unmasktime; 249 /* 250 * errors always ignored (masked), at least for a given 251 * chip/device, because they are wrong or not useful 252 */ 253 ipath_err_t ipath_ignorederrs; 254 /* count of egrfull errors, combined for all ports */ 255 u64 ipath_last_tidfull; 256 /* for ipath_qcheck() */ 257 u64 ipath_lastport0rcv_cnt; 258 /* template for writing TIDs */ 259 u64 ipath_tidtemplate; 260 /* value to write to free TIDs */ 261 u64 ipath_tidinvalid; 262 /* IBA6120 rcv interrupt setup */ 263 u64 ipath_rhdrhead_intr_off; 264 265 /* size of memory at ipath_kregbase */ 266 u32 ipath_kregsize; 267 /* number of registers used for pioavail */ 268 u32 ipath_pioavregs; 269 /* IPATH_POLL, etc. */ 270 u32 ipath_flags; 271 /* ipath_flags driver is waiting for */ 272 u32 ipath_state_wanted; 273 /* last buffer for user use, first buf for kernel use is this 274 * index. */ 275 u32 ipath_lastport_piobuf; 276 /* is a stats timer active */ 277 u32 ipath_stats_timer_active; 278 /* dwords sent read from counter */ 279 u32 ipath_lastsword; 280 /* dwords received read from counter */ 281 u32 ipath_lastrword; 282 /* sent packets read from counter */ 283 u32 ipath_lastspkts; 284 /* received packets read from counter */ 285 u32 ipath_lastrpkts; 286 /* pio bufs allocated per port */ 287 u32 ipath_pbufsport; 288 /* 289 * number of ports configured as max; zero is set to number chip 290 * supports, less gives more pio bufs/port, etc. 291 */ 292 u32 ipath_cfgports; 293 /* port0 rcvhdrq head offset */ 294 u32 ipath_port0head; 295 /* count of port 0 hdrqfull errors */ 296 u32 ipath_p0_hdrqfull; 297 298 /* 299 * (*cfgports) used to suppress multiple instances of same 300 * port staying stuck at same point 301 */ 302 u32 *ipath_lastrcvhdrqtails; 303 /* 304 * (*cfgports) used to suppress multiple instances of same 305 * port staying stuck at same point 306 */ 307 u32 *ipath_lastegrheads; 308 /* 309 * index of last piobuffer we used. Speeds up searching, by 310 * starting at this point. Doesn't matter if multiple cpu's use and 311 * update, last updater is only write that matters. Whenever it 312 * wraps, we update shadow copies. Need a copy per device when we 313 * get to multiple devices 314 */ 315 u32 ipath_lastpioindex; 316 /* max length of freezemsg */ 317 u32 ipath_freezelen; 318 /* 319 * consecutive times we wanted a PIO buffer but were unable to 320 * get one 321 */ 322 u32 ipath_consec_nopiobuf; 323 /* 324 * hint that we should update ipath_pioavailshadow before 325 * looking for a PIO buffer 326 */ 327 u32 ipath_upd_pio_shadow; 328 /* so we can rewrite it after a chip reset */ 329 u32 ipath_pcibar0; 330 /* so we can rewrite it after a chip reset */ 331 u32 ipath_pcibar1; 332 333 /* interrupt number */ 334 int ipath_irq; 335 /* HT/PCI Vendor ID (here for NodeInfo) */ 336 u16 ipath_vendorid; 337 /* HT/PCI Device ID (here for NodeInfo) */ 338 u16 ipath_deviceid; 339 /* offset in HT config space of slave/primary interface block */ 340 u8 ipath_ht_slave_off; 341 /* for write combining settings */ 342 unsigned long ipath_wc_cookie; 343 unsigned long ipath_wc_base; 344 unsigned long ipath_wc_len; 345 /* ref count for each pkey */ 346 atomic_t ipath_pkeyrefs[4]; 347 /* shadow copy of all exptids physaddr; used only by funcsim */ 348 u64 *ipath_tidsimshadow; 349 /* shadow copy of struct page *'s for exp tid pages */ 350 struct page **ipath_pageshadow; 351 /* shadow copy of dma handles for exp tid pages */ 352 dma_addr_t *ipath_physshadow; 353 spinlock_t ipath_tid_lock; 354 355 /* 356 * IPATH_STATUS_*, 357 * this address is mapped readonly into user processes so they can 358 * get status cheaply, whenever they want. 359 */ 360 u64 *ipath_statusp; 361 /* freeze msg if hw error put chip in freeze */ 362 char *ipath_freezemsg; 363 /* pci access data structure */ 364 struct pci_dev *pcidev; 365 struct cdev *user_cdev; 366 struct cdev *diag_cdev; 367 struct class_device *user_class_dev; 368 struct class_device *diag_class_dev; 369 /* timer used to prevent stats overflow, error throttling, etc. */ 370 struct timer_list ipath_stats_timer; 371 /* check for stale messages in rcv queue */ 372 /* only allow one intr at a time. */ 373 unsigned long ipath_rcv_pending; 374 void *ipath_dummy_hdrq; /* used after port close */ 375 dma_addr_t ipath_dummy_hdrq_phys; 376 377 /* 378 * Shadow copies of registers; size indicates read access size. 379 * Most of them are readonly, but some are write-only register, 380 * where we manipulate the bits in the shadow copy, and then write 381 * the shadow copy to infinipath. 382 * 383 * We deliberately make most of these 32 bits, since they have 384 * restricted range. For any that we read, we won't to generate 32 385 * bit accesses, since Opteron will generate 2 separate 32 bit HT 386 * transactions for a 64 bit read, and we want to avoid unnecessary 387 * HT transactions. 388 */ 389 390 /* This is the 64 bit group */ 391 392 /* 393 * shadow of pioavail, check to be sure it's large enough at 394 * init time. 395 */ 396 unsigned long ipath_pioavailshadow[8]; 397 /* shadow of kr_gpio_out, for rmw ops */ 398 u64 ipath_gpio_out; 399 /* shadow the gpio mask register */ 400 u64 ipath_gpio_mask; 401 /* kr_revision shadow */ 402 u64 ipath_revision; 403 /* 404 * shadow of ibcctrl, for interrupt handling of link changes, 405 * etc. 406 */ 407 u64 ipath_ibcctrl; 408 /* 409 * last ibcstatus, to suppress "duplicate" status change messages, 410 * mostly from 2 to 3 411 */ 412 u64 ipath_lastibcstat; 413 /* hwerrmask shadow */ 414 ipath_err_t ipath_hwerrmask; 415 /* interrupt config reg shadow */ 416 u64 ipath_intconfig; 417 /* kr_sendpiobufbase value */ 418 u64 ipath_piobufbase; 419 420 /* these are the "32 bit" regs */ 421 422 /* 423 * number of GUIDs in the flash for this interface; may need some 424 * rethinking for setting on other ifaces 425 */ 426 u32 ipath_nguid; 427 /* 428 * the following two are 32-bit bitmasks, but {test,clear,set}_bit 429 * all expect bit fields to be "unsigned long" 430 */ 431 /* shadow kr_rcvctrl */ 432 unsigned long ipath_rcvctrl; 433 /* shadow kr_sendctrl */ 434 unsigned long ipath_sendctrl; 435 /* ports waiting for PIOavail intr */ 436 unsigned long ipath_portpiowait; 437 unsigned long ipath_lastcancel; /* to not count armlaunch after cancel */ 438 439 /* value we put in kr_rcvhdrcnt */ 440 u32 ipath_rcvhdrcnt; 441 /* value we put in kr_rcvhdrsize */ 442 u32 ipath_rcvhdrsize; 443 /* value we put in kr_rcvhdrentsize */ 444 u32 ipath_rcvhdrentsize; 445 /* offset of last entry in rcvhdrq */ 446 u32 ipath_hdrqlast; 447 /* kr_portcnt value */ 448 u32 ipath_portcnt; 449 /* kr_pagealign value */ 450 u32 ipath_palign; 451 /* number of "2KB" PIO buffers */ 452 u32 ipath_piobcnt2k; 453 /* size in bytes of "2KB" PIO buffers */ 454 u32 ipath_piosize2k; 455 /* number of "4KB" PIO buffers */ 456 u32 ipath_piobcnt4k; 457 /* size in bytes of "4KB" PIO buffers */ 458 u32 ipath_piosize4k; 459 /* kr_rcvegrbase value */ 460 u32 ipath_rcvegrbase; 461 /* kr_rcvegrcnt value */ 462 u32 ipath_rcvegrcnt; 463 /* kr_rcvtidbase value */ 464 u32 ipath_rcvtidbase; 465 /* kr_rcvtidcnt value */ 466 u32 ipath_rcvtidcnt; 467 /* kr_sendregbase */ 468 u32 ipath_sregbase; 469 /* kr_userregbase */ 470 u32 ipath_uregbase; 471 /* kr_counterregbase */ 472 u32 ipath_cregbase; 473 /* shadow the control register contents */ 474 u32 ipath_control; 475 /* shadow the gpio output contents */ 476 u32 ipath_extctrl; 477 /* PCI revision register (HTC rev on FPGA) */ 478 u32 ipath_pcirev; 479 480 /* chip address space used by 4k pio buffers */ 481 u32 ipath_4kalign; 482 /* The MTU programmed for this unit */ 483 u32 ipath_ibmtu; 484 /* 485 * The max size IB packet, included IB headers that we can send. 486 * Starts same as ipath_piosize, but is affected when ibmtu is 487 * changed, or by size of eager buffers 488 */ 489 u32 ipath_ibmaxlen; 490 /* 491 * ibmaxlen at init time, limited by chip and by receive buffer 492 * size. Not changed after init. 493 */ 494 u32 ipath_init_ibmaxlen; 495 /* size of each rcvegrbuffer */ 496 u32 ipath_rcvegrbufsize; 497 /* width (2,4,8,16,32) from HT config reg */ 498 u32 ipath_htwidth; 499 /* HT speed (200,400,800,1000) from HT config */ 500 u32 ipath_htspeed; 501 /* 502 * number of sequential ibcstatus change for polling active/quiet 503 * (i.e., link not coming up). 504 */ 505 u32 ipath_ibpollcnt; 506 /* low and high portions of MSI capability/vector */ 507 u32 ipath_msi_lo; 508 /* saved after PCIe init for restore after reset */ 509 u32 ipath_msi_hi; 510 /* MSI data (vector) saved for restore */ 511 u16 ipath_msi_data; 512 /* MLID programmed for this instance */ 513 u16 ipath_mlid; 514 /* LID programmed for this instance */ 515 u16 ipath_lid; 516 /* list of pkeys programmed; 0 if not set */ 517 u16 ipath_pkeys[4]; 518 /* 519 * ASCII serial number, from flash, large enough for original 520 * all digit strings, and longer QLogic serial number format 521 */ 522 u8 ipath_serial[16]; 523 /* human readable board version */ 524 u8 ipath_boardversion[80]; 525 /* chip major rev, from ipath_revision */ 526 u8 ipath_majrev; 527 /* chip minor rev, from ipath_revision */ 528 u8 ipath_minrev; 529 /* board rev, from ipath_revision */ 530 u8 ipath_boardrev; 531 /* unit # of this chip, if present */ 532 int ipath_unit; 533 /* saved for restore after reset */ 534 u8 ipath_pci_cacheline; 535 /* LID mask control */ 536 u8 ipath_lmc; 537 /* Rx Polarity inversion (compensate for ~tx on partner) */ 538 u8 ipath_rx_pol_inv; 539 540 /* local link integrity counter */ 541 u32 ipath_lli_counter; 542 /* local link integrity errors */ 543 u32 ipath_lli_errors; 544 /* 545 * Above counts only cases where _successive_ LocalLinkIntegrity 546 * errors were seen in the receive headers of kern-packets. 547 * Below are the three (monotonically increasing) counters 548 * maintained via GPIO interrupts on iba6120-rev2. 549 */ 550 u32 ipath_rxfc_unsupvl_errs; 551 u32 ipath_overrun_thresh_errs; 552 u32 ipath_lli_errs; 553 554 /* 555 * Not all devices managed by a driver instance are the same 556 * type, so these fields must be per-device. 557 */ 558 u64 ipath_i_bitsextant; 559 ipath_err_t ipath_e_bitsextant; 560 ipath_err_t ipath_hwe_bitsextant; 561 562 /* 563 * Below should be computable from number of ports, 564 * since they are never modified. 565 */ 566 u32 ipath_i_rcvavail_mask; 567 u32 ipath_i_rcvurg_mask; 568 569 /* 570 * Register bits for selecting i2c direction and values, used for 571 * I2C serial flash. 572 */ 573 u16 ipath_gpio_sda_num; 574 u16 ipath_gpio_scl_num; 575 u64 ipath_gpio_sda; 576 u64 ipath_gpio_scl; 577}; 578 579/* Private data for file operations */ 580struct ipath_filedata { 581 struct ipath_portdata *pd; 582 unsigned subport; 583 unsigned tidcursor; 584}; 585extern struct list_head ipath_dev_list; 586extern spinlock_t ipath_devs_lock; 587extern struct ipath_devdata *ipath_lookup(int unit); 588 589int ipath_init_chip(struct ipath_devdata *, int); 590int ipath_enable_wc(struct ipath_devdata *dd); 591void ipath_disable_wc(struct ipath_devdata *dd); 592int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp); 593void ipath_shutdown_device(struct ipath_devdata *); 594 595struct file_operations; 596int ipath_cdev_init(int minor, char *name, const struct file_operations *fops, 597 struct cdev **cdevp, struct class_device **class_devp); 598void ipath_cdev_cleanup(struct cdev **cdevp, 599 struct class_device **class_devp); 600 601int ipath_diag_add(struct ipath_devdata *); 602void ipath_diag_remove(struct ipath_devdata *); 603 604extern wait_queue_head_t ipath_state_wait; 605 606int ipath_user_add(struct ipath_devdata *dd); 607void ipath_user_remove(struct ipath_devdata *dd); 608 609struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t); 610 611extern int ipath_diag_inuse; 612 613irqreturn_t ipath_intr(int irq, void *devid); 614int ipath_decode_err(char *buf, size_t blen, ipath_err_t err); 615#if __IPATH_INFO || __IPATH_DBG 616extern const char *ipath_ibcstatus_str[]; 617#endif 618 619/* clean up any per-chip chip-specific stuff */ 620void ipath_chip_cleanup(struct ipath_devdata *); 621/* clean up any chip type-specific stuff */ 622void ipath_chip_done(void); 623 624/* check to see if we have to force ordering for write combining */ 625int ipath_unordered_wc(void); 626 627void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first, 628 unsigned cnt); 629 630int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *); 631void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *); 632 633int ipath_parse_ushort(const char *str, unsigned short *valp); 634 635void ipath_kreceive(struct ipath_devdata *); 636int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned); 637int ipath_reset_device(int); 638void ipath_get_faststats(unsigned long); 639int ipath_set_linkstate(struct ipath_devdata *, u8); 640int ipath_set_mtu(struct ipath_devdata *, u16); 641int ipath_set_lid(struct ipath_devdata *, u32, u8); 642int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv); 643 644/* for use in system calls, where we want to know device type, etc. */ 645#define port_fp(fp) ((struct ipath_filedata *)(fp)->private_data)->pd 646#define subport_fp(fp) \ 647 ((struct ipath_filedata *)(fp)->private_data)->subport 648#define tidcursor_fp(fp) \ 649 ((struct ipath_filedata *)(fp)->private_data)->tidcursor 650 651/* 652 * values for ipath_flags 653 */ 654/* The chip is up and initted */ 655#define IPATH_INITTED 0x2 656 /* set if any user code has set kr_rcvhdrsize */ 657#define IPATH_RCVHDRSZ_SET 0x4 658 /* The chip is present and valid for accesses */ 659#define IPATH_PRESENT 0x8 660 /* HT link0 is only 8 bits wide, ignore upper byte crc 661 * errors, etc. */ 662#define IPATH_8BIT_IN_HT0 0x10 663 /* HT link1 is only 8 bits wide, ignore upper byte crc 664 * errors, etc. */ 665#define IPATH_8BIT_IN_HT1 0x20 666 /* The link is down */ 667#define IPATH_LINKDOWN 0x40 668 /* The link level is up (0x11) */ 669#define IPATH_LINKINIT 0x80 670 /* The link is in the armed (0x21) state */ 671#define IPATH_LINKARMED 0x100 672 /* The link is in the active (0x31) state */ 673#define IPATH_LINKACTIVE 0x200 674 /* link current state is unknown */ 675#define IPATH_LINKUNK 0x400 676 /* no IB cable, or no device on IB cable */ 677#define IPATH_NOCABLE 0x4000 678 /* Supports port zero per packet receive interrupts via 679 * GPIO */ 680#define IPATH_GPIO_INTR 0x8000 681 /* uses the coded 4byte TID, not 8 byte */ 682#define IPATH_4BYTE_TID 0x10000 683 /* packet/word counters are 32 bit, else those 4 counters 684 * are 64bit */ 685#define IPATH_32BITCOUNTERS 0x20000 686 /* can miss port0 rx interrupts */ 687#define IPATH_POLL_RX_INTR 0x40000 688#define IPATH_DISABLED 0x80000 /* administratively disabled */ 689 /* Use GPIO interrupts for new counters */ 690#define IPATH_GPIO_ERRINTRS 0x100000 691 692/* Bits in GPIO for the added interrupts */ 693#define IPATH_GPIO_PORT0_BIT 2 694#define IPATH_GPIO_RXUVL_BIT 3 695#define IPATH_GPIO_OVRUN_BIT 4 696#define IPATH_GPIO_LLI_BIT 5 697#define IPATH_GPIO_ERRINTR_MASK 0x38 698 699/* portdata flag bit offsets */ 700 /* waiting for a packet to arrive */ 701#define IPATH_PORT_WAITING_RCV 2 702 /* waiting for a PIO buffer to be available */ 703#define IPATH_PORT_WAITING_PIO 3 704 /* master has not finished initializing */ 705#define IPATH_PORT_MASTER_UNINIT 4 706 707/* free up any allocated data at closes */ 708void ipath_free_data(struct ipath_portdata *dd); 709int ipath_waitfor_mdio_cmdready(struct ipath_devdata *); 710int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *); 711u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *); 712void ipath_init_iba6120_funcs(struct ipath_devdata *); 713void ipath_init_iba6110_funcs(struct ipath_devdata *); 714void ipath_get_eeprom_info(struct ipath_devdata *); 715u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg); 716void ipath_disarm_senderrbufs(struct ipath_devdata *, int); 717 718/* 719 * number of words used for protocol header if not set by ipath_userinit(); 720 */ 721#define IPATH_DFLT_RCVHDRSIZE 9 722 723#define IPATH_MDIO_CMD_WRITE 1 724#define IPATH_MDIO_CMD_READ 2 725#define IPATH_MDIO_CLD_DIV 25 /* to get 2.5 Mhz mdio clock */ 726#define IPATH_MDIO_CMDVALID 0x40000000 /* bit 30 */ 727#define IPATH_MDIO_DATAVALID 0x80000000 /* bit 31 */ 728#define IPATH_MDIO_CTRL_STD 0x0 729 730static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data) 731{ 732 return (((u64) IPATH_MDIO_CLD_DIV) << 32) | 733 (cmd << 26) | 734 (dev << 21) | 735 (reg << 16) | 736 (data & 0xFFFF); 737} 738 739 /* signal and fifo status, in bank 31 */ 740#define IPATH_MDIO_CTRL_XGXS_REG_8 0x8 741 /* controls loopback, redundancy */ 742#define IPATH_MDIO_CTRL_8355_REG_1 0x10 743 /* premph, encdec, etc. */ 744#define IPATH_MDIO_CTRL_8355_REG_2 0x11 745 /* Kchars, etc. */ 746#define IPATH_MDIO_CTRL_8355_REG_6 0x15 747#define IPATH_MDIO_CTRL_8355_REG_9 0x18 748#define IPATH_MDIO_CTRL_8355_REG_10 0x1D 749 750int ipath_get_user_pages(unsigned long, size_t, struct page **); 751int ipath_get_user_pages_nocopy(unsigned long, struct page **); 752void ipath_release_user_pages(struct page **, size_t); 753void ipath_release_user_pages_on_close(struct page **, size_t); 754int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int); 755int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int); 756 757/* these are used for the registers that vary with port */ 758void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg, 759 unsigned, u64); 760 761/* 762 * We could have a single register get/put routine, that takes a group type, 763 * but this is somewhat clearer and cleaner. It also gives us some error 764 * checking. 64 bit register reads should always work, but are inefficient 765 * on opteron (the northbridge always generates 2 separate HT 32 bit reads), 766 * so we use kreg32 wherever possible. User register and counter register 767 * reads are always 32 bit reads, so only one form of those routines. 768 */ 769 770/* 771 * At the moment, none of the s-registers are writable, so no 772 * ipath_write_sreg(), and none of the c-registers are writable, so no 773 * ipath_write_creg(). 774 */ 775 776/** 777 * ipath_read_ureg32 - read 32-bit virtualized per-port register 778 * @dd: device 779 * @regno: register number 780 * @port: port number 781 * 782 * Return the contents of a register that is virtualized to be per port. 783 * Returns -1 on errors (not distinguishable from valid contents at 784 * runtime; we may add a separate error variable at some point). 785 */ 786static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd, 787 ipath_ureg regno, int port) 788{ 789 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) 790 return 0; 791 792 return readl(regno + (u64 __iomem *) 793 (dd->ipath_uregbase + 794 (char __iomem *)dd->ipath_kregbase + 795 dd->ipath_palign * port)); 796} 797 798/** 799 * ipath_write_ureg - write 32-bit virtualized per-port register 800 * @dd: device 801 * @regno: register number 802 * @value: value 803 * @port: port 804 * 805 * Write the contents of a register that is virtualized to be per port. 806 */ 807static inline void ipath_write_ureg(const struct ipath_devdata *dd, 808 ipath_ureg regno, u64 value, int port) 809{ 810 u64 __iomem *ubase = (u64 __iomem *) 811 (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase + 812 dd->ipath_palign * port); 813 if (dd->ipath_kregbase) 814 writeq(value, &ubase[regno]); 815} 816 817static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd, 818 ipath_kreg regno) 819{ 820 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) 821 return -1; 822 return readl((u32 __iomem *) & dd->ipath_kregbase[regno]); 823} 824 825static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd, 826 ipath_kreg regno) 827{ 828 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) 829 return -1; 830 831 return readq(&dd->ipath_kregbase[regno]); 832} 833 834static inline void ipath_write_kreg(const struct ipath_devdata *dd, 835 ipath_kreg regno, u64 value) 836{ 837 if (dd->ipath_kregbase) 838 writeq(value, &dd->ipath_kregbase[regno]); 839} 840 841static inline u64 ipath_read_creg(const struct ipath_devdata *dd, 842 ipath_sreg regno) 843{ 844 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) 845 return 0; 846 847 return readq(regno + (u64 __iomem *) 848 (dd->ipath_cregbase + 849 (char __iomem *)dd->ipath_kregbase)); 850} 851 852static inline u32 ipath_read_creg32(const struct ipath_devdata *dd, 853 ipath_sreg regno) 854{ 855 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) 856 return 0; 857 return readl(regno + (u64 __iomem *) 858 (dd->ipath_cregbase + 859 (char __iomem *)dd->ipath_kregbase)); 860} 861 862/* 863 * sysfs interface. 864 */ 865 866struct device_driver; 867 868extern const char ib_ipath_version[]; 869 870int ipath_driver_create_group(struct device_driver *); 871void ipath_driver_remove_group(struct device_driver *); 872 873int ipath_device_create_group(struct device *, struct ipath_devdata *); 874void ipath_device_remove_group(struct device *, struct ipath_devdata *); 875int ipath_expose_reset(struct device *); 876 877int ipath_init_ipathfs(void); 878void ipath_exit_ipathfs(void); 879int ipathfs_add_device(struct ipath_devdata *); 880int ipathfs_remove_device(struct ipath_devdata *); 881 882/* 883 * dma_addr wrappers - all 0's invalid for hw 884 */ 885dma_addr_t ipath_map_page(struct pci_dev *, struct page *, unsigned long, 886 size_t, int); 887dma_addr_t ipath_map_single(struct pci_dev *, void *, size_t, int); 888 889/* 890 * Flush write combining store buffers (if present) and perform a write 891 * barrier. 892 */ 893#if defined(CONFIG_X86_64) 894#define ipath_flush_wc() asm volatile("sfence" ::: "memory") 895#else 896#define ipath_flush_wc() wmb() 897#endif 898 899extern unsigned ipath_debug; /* debugging bit mask */ 900 901#define IPATH_MAX_PARITY_ATTEMPTS 10000 /* max times to try recovery */ 902 903const char *ipath_get_unit_name(int unit); 904 905extern struct mutex ipath_mutex; 906 907#define IPATH_DRV_NAME "ib_ipath" 908#define IPATH_MAJOR 233 909#define IPATH_USER_MINOR_BASE 0 910#define IPATH_DIAGPKT_MINOR 127 911#define IPATH_DIAG_MINOR_BASE 129 912#define IPATH_NMINORS 255 913 914#define ipath_dev_err(dd,fmt,...) \ 915 do { \ 916 const struct ipath_devdata *__dd = (dd); \ 917 if (__dd->pcidev) \ 918 dev_err(&__dd->pcidev->dev, "%s: " fmt, \ 919 ipath_get_unit_name(__dd->ipath_unit), \ 920 ##__VA_ARGS__); \ 921 else \ 922 printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \ 923 ipath_get_unit_name(__dd->ipath_unit), \ 924 ##__VA_ARGS__); \ 925 } while (0) 926 927#if _IPATH_DEBUGGING 928 929# define __IPATH_DBG_WHICH(which,fmt,...) \ 930 do { \ 931 if(unlikely(ipath_debug&(which))) \ 932 printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \ 933 __func__,##__VA_ARGS__); \ 934 } while(0) 935 936# define ipath_dbg(fmt,...) \ 937 __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__) 938# define ipath_cdbg(which,fmt,...) \ 939 __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__) 940 941#else /* ! _IPATH_DEBUGGING */ 942 943# define ipath_dbg(fmt,...) 944# define ipath_cdbg(which,fmt,...) 945 946#endif /* _IPATH_DEBUGGING */ 947 948/* 949 * this is used for formatting hw error messages... 950 */ 951struct ipath_hwerror_msgs { 952 u64 mask; 953 const char *msg; 954}; 955 956#define INFINIPATH_HWE_MSG(a, b) { .mask = INFINIPATH_HWE_##a, .msg = b } 957 958/* in ipath_intr.c... */ 959void ipath_format_hwerrors(u64 hwerrs, 960 const struct ipath_hwerror_msgs *hwerrmsgs, 961 size_t nhwerrmsgs, 962 char *msg, size_t lmsg); 963 964#endif /* _IPATH_KERNEL_H */ 965