1/* 2 * IBM eServer eHCA Infiniband device driver for Linux on POWER 3 * 4 * QP functions 5 * 6 * Authors: Waleri Fomin <fomin@de.ibm.com> 7 * Hoang-Nam Nguyen <hnguyen@de.ibm.com> 8 * Reinhard Ernst <rernst@de.ibm.com> 9 * Heiko J Schick <schickhj@de.ibm.com> 10 * 11 * Copyright (c) 2005 IBM Corporation 12 * 13 * All rights reserved. 14 * 15 * This source code is distributed under a dual license of GPL v2.0 and OpenIB 16 * BSD. 17 * 18 * OpenIB BSD License 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions are met: 22 * 23 * Redistributions of source code must retain the above copyright notice, this 24 * list of conditions and the following disclaimer. 25 * 26 * Redistributions in binary form must reproduce the above copyright notice, 27 * this list of conditions and the following disclaimer in the documentation 28 * and/or other materials 29 * provided with the distribution. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 35 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 36 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 37 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 38 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 39 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 40 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGE. 42 */ 43 44 45#include <asm/current.h> 46 47#include "ehca_classes.h" 48#include "ehca_tools.h" 49#include "ehca_qes.h" 50#include "ehca_iverbs.h" 51#include "hcp_if.h" 52#include "hipz_fns.h" 53 54static struct kmem_cache *qp_cache; 55 56/* 57 * attributes not supported by query qp 58 */ 59#define QP_ATTR_QUERY_NOT_SUPPORTED (IB_QP_MAX_DEST_RD_ATOMIC | \ 60 IB_QP_MAX_QP_RD_ATOMIC | \ 61 IB_QP_ACCESS_FLAGS | \ 62 IB_QP_EN_SQD_ASYNC_NOTIFY) 63 64/* 65 * ehca (internal) qp state values 66 */ 67enum ehca_qp_state { 68 EHCA_QPS_RESET = 1, 69 EHCA_QPS_INIT = 2, 70 EHCA_QPS_RTR = 3, 71 EHCA_QPS_RTS = 5, 72 EHCA_QPS_SQD = 6, 73 EHCA_QPS_SQE = 8, 74 EHCA_QPS_ERR = 128 75}; 76 77/* 78 * qp state transitions as defined by IB Arch Rel 1.1 page 431 79 */ 80enum ib_qp_statetrans { 81 IB_QPST_ANY2RESET, 82 IB_QPST_ANY2ERR, 83 IB_QPST_RESET2INIT, 84 IB_QPST_INIT2RTR, 85 IB_QPST_INIT2INIT, 86 IB_QPST_RTR2RTS, 87 IB_QPST_RTS2SQD, 88 IB_QPST_RTS2RTS, 89 IB_QPST_SQD2RTS, 90 IB_QPST_SQE2RTS, 91 IB_QPST_SQD2SQD, 92 IB_QPST_MAX /* nr of transitions, this must be last!!! */ 93}; 94 95/* 96 * ib2ehca_qp_state maps IB to ehca qp_state 97 * returns ehca qp state corresponding to given ib qp state 98 */ 99static inline enum ehca_qp_state ib2ehca_qp_state(enum ib_qp_state ib_qp_state) 100{ 101 switch (ib_qp_state) { 102 case IB_QPS_RESET: 103 return EHCA_QPS_RESET; 104 case IB_QPS_INIT: 105 return EHCA_QPS_INIT; 106 case IB_QPS_RTR: 107 return EHCA_QPS_RTR; 108 case IB_QPS_RTS: 109 return EHCA_QPS_RTS; 110 case IB_QPS_SQD: 111 return EHCA_QPS_SQD; 112 case IB_QPS_SQE: 113 return EHCA_QPS_SQE; 114 case IB_QPS_ERR: 115 return EHCA_QPS_ERR; 116 default: 117 ehca_gen_err("invalid ib_qp_state=%x", ib_qp_state); 118 return -EINVAL; 119 } 120} 121 122/* 123 * ehca2ib_qp_state maps ehca to IB qp_state 124 * returns ib qp state corresponding to given ehca qp state 125 */ 126static inline enum ib_qp_state ehca2ib_qp_state(enum ehca_qp_state 127 ehca_qp_state) 128{ 129 switch (ehca_qp_state) { 130 case EHCA_QPS_RESET: 131 return IB_QPS_RESET; 132 case EHCA_QPS_INIT: 133 return IB_QPS_INIT; 134 case EHCA_QPS_RTR: 135 return IB_QPS_RTR; 136 case EHCA_QPS_RTS: 137 return IB_QPS_RTS; 138 case EHCA_QPS_SQD: 139 return IB_QPS_SQD; 140 case EHCA_QPS_SQE: 141 return IB_QPS_SQE; 142 case EHCA_QPS_ERR: 143 return IB_QPS_ERR; 144 default: 145 ehca_gen_err("invalid ehca_qp_state=%x", ehca_qp_state); 146 return -EINVAL; 147 } 148} 149 150/* 151 * ehca_qp_type used as index for req_attr and opt_attr of 152 * struct ehca_modqp_statetrans 153 */ 154enum ehca_qp_type { 155 QPT_RC = 0, 156 QPT_UC = 1, 157 QPT_UD = 2, 158 QPT_SQP = 3, 159 QPT_MAX 160}; 161 162/* 163 * ib2ehcaqptype maps Ib to ehca qp_type 164 * returns ehca qp type corresponding to ib qp type 165 */ 166static inline enum ehca_qp_type ib2ehcaqptype(enum ib_qp_type ibqptype) 167{ 168 switch (ibqptype) { 169 case IB_QPT_SMI: 170 case IB_QPT_GSI: 171 return QPT_SQP; 172 case IB_QPT_RC: 173 return QPT_RC; 174 case IB_QPT_UC: 175 return QPT_UC; 176 case IB_QPT_UD: 177 return QPT_UD; 178 default: 179 ehca_gen_err("Invalid ibqptype=%x", ibqptype); 180 return -EINVAL; 181 } 182} 183 184static inline enum ib_qp_statetrans get_modqp_statetrans(int ib_fromstate, 185 int ib_tostate) 186{ 187 int index = -EINVAL; 188 switch (ib_tostate) { 189 case IB_QPS_RESET: 190 index = IB_QPST_ANY2RESET; 191 break; 192 case IB_QPS_INIT: 193 switch (ib_fromstate) { 194 case IB_QPS_RESET: 195 index = IB_QPST_RESET2INIT; 196 break; 197 case IB_QPS_INIT: 198 index = IB_QPST_INIT2INIT; 199 break; 200 } 201 break; 202 case IB_QPS_RTR: 203 if (ib_fromstate == IB_QPS_INIT) 204 index = IB_QPST_INIT2RTR; 205 break; 206 case IB_QPS_RTS: 207 switch (ib_fromstate) { 208 case IB_QPS_RTR: 209 index = IB_QPST_RTR2RTS; 210 break; 211 case IB_QPS_RTS: 212 index = IB_QPST_RTS2RTS; 213 break; 214 case IB_QPS_SQD: 215 index = IB_QPST_SQD2RTS; 216 break; 217 case IB_QPS_SQE: 218 index = IB_QPST_SQE2RTS; 219 break; 220 } 221 break; 222 case IB_QPS_SQD: 223 if (ib_fromstate == IB_QPS_RTS) 224 index = IB_QPST_RTS2SQD; 225 break; 226 case IB_QPS_SQE: 227 break; 228 case IB_QPS_ERR: 229 index = IB_QPST_ANY2ERR; 230 break; 231 default: 232 break; 233 } 234 return index; 235} 236 237enum ehca_service_type { 238 ST_RC = 0, 239 ST_UC = 1, 240 ST_RD = 2, 241 ST_UD = 3 242}; 243 244/* 245 * ibqptype2servicetype returns hcp service type corresponding to given 246 * ib qp type used by create_qp() 247 */ 248static inline int ibqptype2servicetype(enum ib_qp_type ibqptype) 249{ 250 switch (ibqptype) { 251 case IB_QPT_SMI: 252 case IB_QPT_GSI: 253 return ST_UD; 254 case IB_QPT_RC: 255 return ST_RC; 256 case IB_QPT_UC: 257 return ST_UC; 258 case IB_QPT_UD: 259 return ST_UD; 260 case IB_QPT_RAW_IPV6: 261 return -EINVAL; 262 case IB_QPT_RAW_ETY: 263 return -EINVAL; 264 default: 265 ehca_gen_err("Invalid ibqptype=%x", ibqptype); 266 return -EINVAL; 267 } 268} 269 270/* 271 * init_qp_queues initializes/constructs r/squeue and registers queue pages. 272 */ 273static inline int init_qp_queues(struct ehca_shca *shca, 274 struct ehca_qp *my_qp, 275 int nr_sq_pages, 276 int nr_rq_pages, 277 int swqe_size, 278 int rwqe_size, 279 int nr_send_sges, int nr_receive_sges) 280{ 281 int ret, cnt, ipz_rc; 282 void *vpage; 283 u64 rpage, h_ret; 284 struct ib_device *ib_dev = &shca->ib_device; 285 struct ipz_adapter_handle ipz_hca_handle = shca->ipz_hca_handle; 286 287 ipz_rc = ipz_queue_ctor(&my_qp->ipz_squeue, 288 nr_sq_pages, 289 EHCA_PAGESIZE, swqe_size, nr_send_sges); 290 if (!ipz_rc) { 291 ehca_err(ib_dev,"Cannot allocate page for squeue. ipz_rc=%x", 292 ipz_rc); 293 return -EBUSY; 294 } 295 296 ipz_rc = ipz_queue_ctor(&my_qp->ipz_rqueue, 297 nr_rq_pages, 298 EHCA_PAGESIZE, rwqe_size, nr_receive_sges); 299 if (!ipz_rc) { 300 ehca_err(ib_dev, "Cannot allocate page for rqueue. ipz_rc=%x", 301 ipz_rc); 302 ret = -EBUSY; 303 goto init_qp_queues0; 304 } 305 /* register SQ pages */ 306 for (cnt = 0; cnt < nr_sq_pages; cnt++) { 307 vpage = ipz_qpageit_get_inc(&my_qp->ipz_squeue); 308 if (!vpage) { 309 ehca_err(ib_dev, "SQ ipz_qpageit_get_inc() " 310 "failed p_vpage= %p", vpage); 311 ret = -EINVAL; 312 goto init_qp_queues1; 313 } 314 rpage = virt_to_abs(vpage); 315 316 h_ret = hipz_h_register_rpage_qp(ipz_hca_handle, 317 my_qp->ipz_qp_handle, 318 &my_qp->pf, 0, 0, 319 rpage, 1, 320 my_qp->galpas.kernel); 321 if (h_ret < H_SUCCESS) { 322 ehca_err(ib_dev, "SQ hipz_qp_register_rpage()" 323 " failed rc=%lx", h_ret); 324 ret = ehca2ib_return_code(h_ret); 325 goto init_qp_queues1; 326 } 327 } 328 329 ipz_qeit_reset(&my_qp->ipz_squeue); 330 331 /* register RQ pages */ 332 for (cnt = 0; cnt < nr_rq_pages; cnt++) { 333 vpage = ipz_qpageit_get_inc(&my_qp->ipz_rqueue); 334 if (!vpage) { 335 ehca_err(ib_dev, "RQ ipz_qpageit_get_inc() " 336 "failed p_vpage = %p", vpage); 337 ret = -EINVAL; 338 goto init_qp_queues1; 339 } 340 341 rpage = virt_to_abs(vpage); 342 343 h_ret = hipz_h_register_rpage_qp(ipz_hca_handle, 344 my_qp->ipz_qp_handle, 345 &my_qp->pf, 0, 1, 346 rpage, 1,my_qp->galpas.kernel); 347 if (h_ret < H_SUCCESS) { 348 ehca_err(ib_dev, "RQ hipz_qp_register_rpage() failed " 349 "rc=%lx", h_ret); 350 ret = ehca2ib_return_code(h_ret); 351 goto init_qp_queues1; 352 } 353 if (cnt == (nr_rq_pages - 1)) { /* last page! */ 354 if (h_ret != H_SUCCESS) { 355 ehca_err(ib_dev, "RQ hipz_qp_register_rpage() " 356 "h_ret= %lx ", h_ret); 357 ret = ehca2ib_return_code(h_ret); 358 goto init_qp_queues1; 359 } 360 vpage = ipz_qpageit_get_inc(&my_qp->ipz_rqueue); 361 if (vpage) { 362 ehca_err(ib_dev, "ipz_qpageit_get_inc() " 363 "should not succeed vpage=%p", vpage); 364 ret = -EINVAL; 365 goto init_qp_queues1; 366 } 367 } else { 368 if (h_ret != H_PAGE_REGISTERED) { 369 ehca_err(ib_dev, "RQ hipz_qp_register_rpage() " 370 "h_ret= %lx ", h_ret); 371 ret = ehca2ib_return_code(h_ret); 372 goto init_qp_queues1; 373 } 374 } 375 } 376 377 ipz_qeit_reset(&my_qp->ipz_rqueue); 378 379 return 0; 380 381init_qp_queues1: 382 ipz_queue_dtor(&my_qp->ipz_rqueue); 383init_qp_queues0: 384 ipz_queue_dtor(&my_qp->ipz_squeue); 385 return ret; 386} 387 388struct ib_qp *ehca_create_qp(struct ib_pd *pd, 389 struct ib_qp_init_attr *init_attr, 390 struct ib_udata *udata) 391{ 392 static int da_rc_msg_size[]={ 128, 256, 512, 1024, 2048, 4096 }; 393 static int da_ud_sq_msg_size[]={ 128, 384, 896, 1920, 3968 }; 394 struct ehca_qp *my_qp; 395 struct ehca_pd *my_pd = container_of(pd, struct ehca_pd, ib_pd); 396 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca, 397 ib_device); 398 struct ib_ucontext *context = NULL; 399 u64 h_ret; 400 int max_send_sge, max_recv_sge, ret; 401 402 /* h_call's out parameters */ 403 struct ehca_alloc_qp_parms parms; 404 u32 swqe_size = 0, rwqe_size = 0; 405 u8 daqp_completion, isdaqp; 406 unsigned long flags; 407 408 if (init_attr->sq_sig_type != IB_SIGNAL_REQ_WR && 409 init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) { 410 ehca_err(pd->device, "init_attr->sg_sig_type=%x not allowed", 411 init_attr->sq_sig_type); 412 return ERR_PTR(-EINVAL); 413 } 414 415 /* save daqp completion bits */ 416 daqp_completion = init_attr->qp_type & 0x60; 417 /* save daqp bit */ 418 isdaqp = (init_attr->qp_type & 0x80) ? 1 : 0; 419 init_attr->qp_type = init_attr->qp_type & 0x1F; 420 421 if (init_attr->qp_type != IB_QPT_UD && 422 init_attr->qp_type != IB_QPT_SMI && 423 init_attr->qp_type != IB_QPT_GSI && 424 init_attr->qp_type != IB_QPT_UC && 425 init_attr->qp_type != IB_QPT_RC) { 426 ehca_err(pd->device, "wrong QP Type=%x", init_attr->qp_type); 427 return ERR_PTR(-EINVAL); 428 } 429 if ((init_attr->qp_type != IB_QPT_RC && init_attr->qp_type != IB_QPT_UD) 430 && isdaqp) { 431 ehca_err(pd->device, "unsupported LL QP Type=%x", 432 init_attr->qp_type); 433 return ERR_PTR(-EINVAL); 434 } else if (init_attr->qp_type == IB_QPT_RC && isdaqp && 435 (init_attr->cap.max_send_wr > 255 || 436 init_attr->cap.max_recv_wr > 255 )) { 437 ehca_err(pd->device, "Invalid Number of max_sq_wr =%x " 438 "or max_rq_wr=%x for QP Type=%x", 439 init_attr->cap.max_send_wr, 440 init_attr->cap.max_recv_wr,init_attr->qp_type); 441 return ERR_PTR(-EINVAL); 442 } else if (init_attr->qp_type == IB_QPT_UD && isdaqp && 443 init_attr->cap.max_send_wr > 255) { 444 ehca_err(pd->device, 445 "Invalid Number of max_send_wr=%x for UD QP_TYPE=%x", 446 init_attr->cap.max_send_wr, init_attr->qp_type); 447 return ERR_PTR(-EINVAL); 448 } 449 450 if (pd->uobject && udata) 451 context = pd->uobject->context; 452 453 my_qp = kmem_cache_zalloc(qp_cache, GFP_KERNEL); 454 if (!my_qp) { 455 ehca_err(pd->device, "pd=%p not enough memory to alloc qp", pd); 456 return ERR_PTR(-ENOMEM); 457 } 458 459 memset (&parms, 0, sizeof(struct ehca_alloc_qp_parms)); 460 spin_lock_init(&my_qp->spinlock_s); 461 spin_lock_init(&my_qp->spinlock_r); 462 463 my_qp->recv_cq = 464 container_of(init_attr->recv_cq, struct ehca_cq, ib_cq); 465 my_qp->send_cq = 466 container_of(init_attr->send_cq, struct ehca_cq, ib_cq); 467 468 my_qp->init_attr = *init_attr; 469 470 do { 471 if (!idr_pre_get(&ehca_qp_idr, GFP_KERNEL)) { 472 ret = -ENOMEM; 473 ehca_err(pd->device, "Can't reserve idr resources."); 474 goto create_qp_exit0; 475 } 476 477 spin_lock_irqsave(&ehca_qp_idr_lock, flags); 478 ret = idr_get_new(&ehca_qp_idr, my_qp, &my_qp->token); 479 spin_unlock_irqrestore(&ehca_qp_idr_lock, flags); 480 481 } while (ret == -EAGAIN); 482 483 if (ret) { 484 ret = -ENOMEM; 485 ehca_err(pd->device, "Can't allocate new idr entry."); 486 goto create_qp_exit0; 487 } 488 489 parms.servicetype = ibqptype2servicetype(init_attr->qp_type); 490 if (parms.servicetype < 0) { 491 ret = -EINVAL; 492 ehca_err(pd->device, "Invalid qp_type=%x", init_attr->qp_type); 493 goto create_qp_exit0; 494 } 495 496 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 497 parms.sigtype = HCALL_SIGT_EVERY; 498 else 499 parms.sigtype = HCALL_SIGT_BY_WQE; 500 501 /* UD_AV CIRCUMVENTION */ 502 max_send_sge = init_attr->cap.max_send_sge; 503 max_recv_sge = init_attr->cap.max_recv_sge; 504 if (IB_QPT_UD == init_attr->qp_type || 505 IB_QPT_GSI == init_attr->qp_type || 506 IB_QPT_SMI == init_attr->qp_type) { 507 max_send_sge += 2; 508 max_recv_sge += 2; 509 } 510 511 parms.ipz_eq_handle = shca->eq.ipz_eq_handle; 512 parms.daqp_ctrl = isdaqp | daqp_completion; 513 parms.pd = my_pd->fw_pd; 514 parms.max_recv_sge = max_recv_sge; 515 parms.max_send_sge = max_send_sge; 516 517 h_ret = hipz_h_alloc_resource_qp(shca->ipz_hca_handle, my_qp, &parms); 518 519 if (h_ret != H_SUCCESS) { 520 ehca_err(pd->device, "h_alloc_resource_qp() failed h_ret=%lx", 521 h_ret); 522 ret = ehca2ib_return_code(h_ret); 523 goto create_qp_exit1; 524 } 525 526 my_qp->ib_qp.qp_num = my_qp->real_qp_num; 527 528 switch (init_attr->qp_type) { 529 case IB_QPT_RC: 530 if (isdaqp == 0) { 531 swqe_size = offsetof(struct ehca_wqe, u.nud.sg_list[ 532 (parms.act_nr_send_sges)]); 533 rwqe_size = offsetof(struct ehca_wqe, u.nud.sg_list[ 534 (parms.act_nr_recv_sges)]); 535 } else { /* for daqp we need to use msg size, not wqe size */ 536 swqe_size = da_rc_msg_size[max_send_sge]; 537 rwqe_size = da_rc_msg_size[max_recv_sge]; 538 parms.act_nr_send_sges = 1; 539 parms.act_nr_recv_sges = 1; 540 } 541 break; 542 case IB_QPT_UC: 543 swqe_size = offsetof(struct ehca_wqe, 544 u.nud.sg_list[parms.act_nr_send_sges]); 545 rwqe_size = offsetof(struct ehca_wqe, 546 u.nud.sg_list[parms.act_nr_recv_sges]); 547 break; 548 549 case IB_QPT_UD: 550 case IB_QPT_GSI: 551 case IB_QPT_SMI: 552 /* UD circumvention */ 553 parms.act_nr_recv_sges -= 2; 554 parms.act_nr_send_sges -= 2; 555 if (isdaqp) { 556 swqe_size = da_ud_sq_msg_size[max_send_sge]; 557 rwqe_size = da_rc_msg_size[max_recv_sge]; 558 parms.act_nr_send_sges = 1; 559 parms.act_nr_recv_sges = 1; 560 } else { 561 swqe_size = offsetof(struct ehca_wqe, 562 u.ud_av.sg_list[parms.act_nr_send_sges]); 563 rwqe_size = offsetof(struct ehca_wqe, 564 u.ud_av.sg_list[parms.act_nr_recv_sges]); 565 } 566 567 if (IB_QPT_GSI == init_attr->qp_type || 568 IB_QPT_SMI == init_attr->qp_type) { 569 parms.act_nr_send_wqes = init_attr->cap.max_send_wr; 570 parms.act_nr_recv_wqes = init_attr->cap.max_recv_wr; 571 parms.act_nr_send_sges = init_attr->cap.max_send_sge; 572 parms.act_nr_recv_sges = init_attr->cap.max_recv_sge; 573 my_qp->ib_qp.qp_num = 574 (init_attr->qp_type == IB_QPT_SMI) ? 0 : 1; 575 } 576 577 break; 578 579 default: 580 break; 581 } 582 583 /* initializes r/squeue and registers queue pages */ 584 ret = init_qp_queues(shca, my_qp, 585 parms.nr_sq_pages, parms.nr_rq_pages, 586 swqe_size, rwqe_size, 587 parms.act_nr_send_sges, parms.act_nr_recv_sges); 588 if (ret) { 589 ehca_err(pd->device, 590 "Couldn't initialize r/squeue and pages ret=%x", ret); 591 goto create_qp_exit2; 592 } 593 594 my_qp->ib_qp.pd = &my_pd->ib_pd; 595 my_qp->ib_qp.device = my_pd->ib_pd.device; 596 597 my_qp->ib_qp.recv_cq = init_attr->recv_cq; 598 my_qp->ib_qp.send_cq = init_attr->send_cq; 599 600 my_qp->ib_qp.qp_type = init_attr->qp_type; 601 602 my_qp->qp_type = init_attr->qp_type; 603 my_qp->ib_qp.srq = init_attr->srq; 604 605 my_qp->ib_qp.qp_context = init_attr->qp_context; 606 my_qp->ib_qp.event_handler = init_attr->event_handler; 607 608 init_attr->cap.max_inline_data = 0; /* not supported yet */ 609 init_attr->cap.max_recv_sge = parms.act_nr_recv_sges; 610 init_attr->cap.max_recv_wr = parms.act_nr_recv_wqes; 611 init_attr->cap.max_send_sge = parms.act_nr_send_sges; 612 init_attr->cap.max_send_wr = parms.act_nr_send_wqes; 613 614 /* NOTE: define_apq0() not supported yet */ 615 if (init_attr->qp_type == IB_QPT_GSI) { 616 h_ret = ehca_define_sqp(shca, my_qp, init_attr); 617 if (h_ret != H_SUCCESS) { 618 ehca_err(pd->device, "ehca_define_sqp() failed rc=%lx", 619 h_ret); 620 ret = ehca2ib_return_code(h_ret); 621 goto create_qp_exit3; 622 } 623 } 624 if (init_attr->send_cq) { 625 struct ehca_cq *cq = container_of(init_attr->send_cq, 626 struct ehca_cq, ib_cq); 627 ret = ehca_cq_assign_qp(cq, my_qp); 628 if (ret) { 629 ehca_err(pd->device, "Couldn't assign qp to send_cq ret=%x", 630 ret); 631 goto create_qp_exit3; 632 } 633 my_qp->send_cq = cq; 634 } 635 /* copy queues, galpa data to user space */ 636 if (context && udata) { 637 struct ipz_queue *ipz_rqueue = &my_qp->ipz_rqueue; 638 struct ipz_queue *ipz_squeue = &my_qp->ipz_squeue; 639 struct ehca_create_qp_resp resp; 640 memset(&resp, 0, sizeof(resp)); 641 642 resp.qp_num = my_qp->real_qp_num; 643 resp.token = my_qp->token; 644 resp.qp_type = my_qp->qp_type; 645 resp.qkey = my_qp->qkey; 646 resp.real_qp_num = my_qp->real_qp_num; 647 /* rqueue properties */ 648 resp.ipz_rqueue.qe_size = ipz_rqueue->qe_size; 649 resp.ipz_rqueue.act_nr_of_sg = ipz_rqueue->act_nr_of_sg; 650 resp.ipz_rqueue.queue_length = ipz_rqueue->queue_length; 651 resp.ipz_rqueue.pagesize = ipz_rqueue->pagesize; 652 resp.ipz_rqueue.toggle_state = ipz_rqueue->toggle_state; 653 /* squeue properties */ 654 resp.ipz_squeue.qe_size = ipz_squeue->qe_size; 655 resp.ipz_squeue.act_nr_of_sg = ipz_squeue->act_nr_of_sg; 656 resp.ipz_squeue.queue_length = ipz_squeue->queue_length; 657 resp.ipz_squeue.pagesize = ipz_squeue->pagesize; 658 resp.ipz_squeue.toggle_state = ipz_squeue->toggle_state; 659 if (ib_copy_to_udata(udata, &resp, sizeof resp)) { 660 ehca_err(pd->device, "Copy to udata failed"); 661 ret = -EINVAL; 662 goto create_qp_exit3; 663 } 664 } 665 666 return &my_qp->ib_qp; 667 668create_qp_exit3: 669 ipz_queue_dtor(&my_qp->ipz_rqueue); 670 ipz_queue_dtor(&my_qp->ipz_squeue); 671 672create_qp_exit2: 673 hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp); 674 675create_qp_exit1: 676 spin_lock_irqsave(&ehca_qp_idr_lock, flags); 677 idr_remove(&ehca_qp_idr, my_qp->token); 678 spin_unlock_irqrestore(&ehca_qp_idr_lock, flags); 679 680create_qp_exit0: 681 kmem_cache_free(qp_cache, my_qp); 682 return ERR_PTR(ret); 683} 684 685/* 686 * prepare_sqe_rts called by internal_modify_qp() at trans sqe -> rts 687 * set purge bit of bad wqe and subsequent wqes to avoid reentering sqe 688 * returns total number of bad wqes in bad_wqe_cnt 689 */ 690static int prepare_sqe_rts(struct ehca_qp *my_qp, struct ehca_shca *shca, 691 int *bad_wqe_cnt) 692{ 693 u64 h_ret; 694 struct ipz_queue *squeue; 695 void *bad_send_wqe_p, *bad_send_wqe_v; 696 u64 q_ofs; 697 struct ehca_wqe *wqe; 698 int qp_num = my_qp->ib_qp.qp_num; 699 700 /* get send wqe pointer */ 701 h_ret = hipz_h_disable_and_get_wqe(shca->ipz_hca_handle, 702 my_qp->ipz_qp_handle, &my_qp->pf, 703 &bad_send_wqe_p, NULL, 2); 704 if (h_ret != H_SUCCESS) { 705 ehca_err(&shca->ib_device, "hipz_h_disable_and_get_wqe() failed" 706 " ehca_qp=%p qp_num=%x h_ret=%lx", 707 my_qp, qp_num, h_ret); 708 return ehca2ib_return_code(h_ret); 709 } 710 bad_send_wqe_p = (void*)((u64)bad_send_wqe_p & (~(1L<<63))); 711 ehca_dbg(&shca->ib_device, "qp_num=%x bad_send_wqe_p=%p", 712 qp_num, bad_send_wqe_p); 713 /* convert wqe pointer to vadr */ 714 bad_send_wqe_v = abs_to_virt((u64)bad_send_wqe_p); 715 if (ehca_debug_level) 716 ehca_dmp(bad_send_wqe_v, 32, "qp_num=%x bad_wqe", qp_num); 717 squeue = &my_qp->ipz_squeue; 718 if (ipz_queue_abs_to_offset(squeue, (u64)bad_send_wqe_p, &q_ofs)) { 719 ehca_err(&shca->ib_device, "failed to get wqe offset qp_num=%x" 720 " bad_send_wqe_p=%p", qp_num, bad_send_wqe_p); 721 return -EFAULT; 722 } 723 724 /* loop sets wqe's purge bit */ 725 wqe = (struct ehca_wqe*)ipz_qeit_calc(squeue, q_ofs); 726 *bad_wqe_cnt = 0; 727 while (wqe->optype != 0xff && wqe->wqef != 0xff) { 728 if (ehca_debug_level) 729 ehca_dmp(wqe, 32, "qp_num=%x wqe", qp_num); 730 wqe->nr_of_data_seg = 0; /* suppress data access */ 731 wqe->wqef = WQEF_PURGE; /* WQE to be purged */ 732 q_ofs = ipz_queue_advance_offset(squeue, q_ofs); 733 wqe = (struct ehca_wqe*)ipz_qeit_calc(squeue, q_ofs); 734 *bad_wqe_cnt = (*bad_wqe_cnt)+1; 735 } 736 /* 737 * bad wqe will be reprocessed and ignored when pol_cq() is called, 738 * i.e. nr of wqes with flush error status is one less 739 */ 740 ehca_dbg(&shca->ib_device, "qp_num=%x flusherr_wqe_cnt=%x", 741 qp_num, (*bad_wqe_cnt)-1); 742 wqe->wqef = 0; 743 744 return 0; 745} 746 747/* 748 * internal_modify_qp with circumvention to handle aqp0 properly 749 * smi_reset2init indicates if this is an internal reset-to-init-call for 750 * smi. This flag must always be zero if called from ehca_modify_qp()! 751 * This internal func was intorduced to avoid recursion of ehca_modify_qp()! 752 */ 753static int internal_modify_qp(struct ib_qp *ibqp, 754 struct ib_qp_attr *attr, 755 int attr_mask, int smi_reset2init) 756{ 757 enum ib_qp_state qp_cur_state, qp_new_state; 758 int cnt, qp_attr_idx, ret = 0; 759 enum ib_qp_statetrans statetrans; 760 struct hcp_modify_qp_control_block *mqpcb; 761 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp); 762 struct ehca_shca *shca = 763 container_of(ibqp->pd->device, struct ehca_shca, ib_device); 764 u64 update_mask; 765 u64 h_ret; 766 int bad_wqe_cnt = 0; 767 int squeue_locked = 0; 768 unsigned long spl_flags = 0; 769 770 /* do query_qp to obtain current attr values */ 771 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL); 772 if (!mqpcb) { 773 ehca_err(ibqp->device, "Could not get zeroed page for mqpcb " 774 "ehca_qp=%p qp_num=%x ", my_qp, ibqp->qp_num); 775 return -ENOMEM; 776 } 777 778 h_ret = hipz_h_query_qp(shca->ipz_hca_handle, 779 my_qp->ipz_qp_handle, 780 &my_qp->pf, 781 mqpcb, my_qp->galpas.kernel); 782 if (h_ret != H_SUCCESS) { 783 ehca_err(ibqp->device, "hipz_h_query_qp() failed " 784 "ehca_qp=%p qp_num=%x h_ret=%lx", 785 my_qp, ibqp->qp_num, h_ret); 786 ret = ehca2ib_return_code(h_ret); 787 goto modify_qp_exit1; 788 } 789 790 qp_cur_state = ehca2ib_qp_state(mqpcb->qp_state); 791 792 if (qp_cur_state == -EINVAL) { /* invalid qp state */ 793 ret = -EINVAL; 794 ehca_err(ibqp->device, "Invalid current ehca_qp_state=%x " 795 "ehca_qp=%p qp_num=%x", 796 mqpcb->qp_state, my_qp, ibqp->qp_num); 797 goto modify_qp_exit1; 798 } 799 /* 800 * circumvention to set aqp0 initial state to init 801 * as expected by IB spec 802 */ 803 if (smi_reset2init == 0 && 804 ibqp->qp_type == IB_QPT_SMI && 805 qp_cur_state == IB_QPS_RESET && 806 (attr_mask & IB_QP_STATE) && 807 attr->qp_state == IB_QPS_INIT) { /* RESET -> INIT */ 808 struct ib_qp_attr smiqp_attr = { 809 .qp_state = IB_QPS_INIT, 810 .port_num = my_qp->init_attr.port_num, 811 .pkey_index = 0, 812 .qkey = 0 813 }; 814 int smiqp_attr_mask = IB_QP_STATE | IB_QP_PORT | 815 IB_QP_PKEY_INDEX | IB_QP_QKEY; 816 int smirc = internal_modify_qp( 817 ibqp, &smiqp_attr, smiqp_attr_mask, 1); 818 if (smirc) { 819 ehca_err(ibqp->device, "SMI RESET -> INIT failed. " 820 "ehca_modify_qp() rc=%x", smirc); 821 ret = H_PARAMETER; 822 goto modify_qp_exit1; 823 } 824 qp_cur_state = IB_QPS_INIT; 825 ehca_dbg(ibqp->device, "SMI RESET -> INIT succeeded"); 826 } 827 /* is transmitted current state equal to "real" current state */ 828 if ((attr_mask & IB_QP_CUR_STATE) && 829 qp_cur_state != attr->cur_qp_state) { 830 ret = -EINVAL; 831 ehca_err(ibqp->device, 832 "Invalid IB_QP_CUR_STATE attr->curr_qp_state=%x <>" 833 " actual cur_qp_state=%x. ehca_qp=%p qp_num=%x", 834 attr->cur_qp_state, qp_cur_state, my_qp, ibqp->qp_num); 835 goto modify_qp_exit1; 836 } 837 838 ehca_dbg(ibqp->device,"ehca_qp=%p qp_num=%x current qp_state=%x " 839 "new qp_state=%x attribute_mask=%x", 840 my_qp, ibqp->qp_num, qp_cur_state, attr->qp_state, attr_mask); 841 842 qp_new_state = attr_mask & IB_QP_STATE ? attr->qp_state : qp_cur_state; 843 if (!smi_reset2init && 844 !ib_modify_qp_is_ok(qp_cur_state, qp_new_state, ibqp->qp_type, 845 attr_mask)) { 846 ret = -EINVAL; 847 ehca_err(ibqp->device, 848 "Invalid qp transition new_state=%x cur_state=%x " 849 "ehca_qp=%p qp_num=%x attr_mask=%x", qp_new_state, 850 qp_cur_state, my_qp, ibqp->qp_num, attr_mask); 851 goto modify_qp_exit1; 852 } 853 854 if ((mqpcb->qp_state = ib2ehca_qp_state(qp_new_state))) 855 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1); 856 else { 857 ret = -EINVAL; 858 ehca_err(ibqp->device, "Invalid new qp state=%x " 859 "ehca_qp=%p qp_num=%x", 860 qp_new_state, my_qp, ibqp->qp_num); 861 goto modify_qp_exit1; 862 } 863 864 /* retrieve state transition struct to get req and opt attrs */ 865 statetrans = get_modqp_statetrans(qp_cur_state, qp_new_state); 866 if (statetrans < 0) { 867 ret = -EINVAL; 868 ehca_err(ibqp->device, "<INVALID STATE CHANGE> qp_cur_state=%x " 869 "new_qp_state=%x State_xsition=%x ehca_qp=%p " 870 "qp_num=%x", qp_cur_state, qp_new_state, 871 statetrans, my_qp, ibqp->qp_num); 872 goto modify_qp_exit1; 873 } 874 875 qp_attr_idx = ib2ehcaqptype(ibqp->qp_type); 876 877 if (qp_attr_idx < 0) { 878 ret = qp_attr_idx; 879 ehca_err(ibqp->device, 880 "Invalid QP type=%x ehca_qp=%p qp_num=%x", 881 ibqp->qp_type, my_qp, ibqp->qp_num); 882 goto modify_qp_exit1; 883 } 884 885 ehca_dbg(ibqp->device, 886 "ehca_qp=%p qp_num=%x <VALID STATE CHANGE> qp_state_xsit=%x", 887 my_qp, ibqp->qp_num, statetrans); 888 889 /* sqe -> rts: set purge bit of bad wqe before actual trans */ 890 if ((my_qp->qp_type == IB_QPT_UD || 891 my_qp->qp_type == IB_QPT_GSI || 892 my_qp->qp_type == IB_QPT_SMI) && 893 statetrans == IB_QPST_SQE2RTS) { 894 /* mark next free wqe if kernel */ 895 if (!ibqp->uobject) { 896 struct ehca_wqe *wqe; 897 /* lock send queue */ 898 spin_lock_irqsave(&my_qp->spinlock_s, spl_flags); 899 squeue_locked = 1; 900 /* mark next free wqe */ 901 wqe = (struct ehca_wqe*) 902 ipz_qeit_get(&my_qp->ipz_squeue); 903 wqe->optype = wqe->wqef = 0xff; 904 ehca_dbg(ibqp->device, "qp_num=%x next_free_wqe=%p", 905 ibqp->qp_num, wqe); 906 } 907 ret = prepare_sqe_rts(my_qp, shca, &bad_wqe_cnt); 908 if (ret) { 909 ehca_err(ibqp->device, "prepare_sqe_rts() failed " 910 "ehca_qp=%p qp_num=%x ret=%x", 911 my_qp, ibqp->qp_num, ret); 912 goto modify_qp_exit2; 913 } 914 } 915 916 /* 917 * enable RDMA_Atomic_Control if reset->init und reliable con 918 * this is necessary since gen2 does not provide that flag, 919 * but pHyp requires it 920 */ 921 if (statetrans == IB_QPST_RESET2INIT && 922 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_UC)) { 923 mqpcb->rdma_atomic_ctrl = 3; 924 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RDMA_ATOMIC_CTRL, 1); 925 } 926 /* circ. pHyp requires #RDMA/Atomic Resp Res for UC INIT -> RTR */ 927 if (statetrans == IB_QPST_INIT2RTR && 928 (ibqp->qp_type == IB_QPT_UC) && 929 !(attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)) { 930 mqpcb->rdma_nr_atomic_resp_res = 1; /* default to 1 */ 931 update_mask |= 932 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1); 933 } 934 935 if (attr_mask & IB_QP_PKEY_INDEX) { 936 mqpcb->prim_p_key_idx = attr->pkey_index; 937 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_P_KEY_IDX, 1); 938 } 939 if (attr_mask & IB_QP_PORT) { 940 if (attr->port_num < 1 || attr->port_num > shca->num_ports) { 941 ret = -EINVAL; 942 ehca_err(ibqp->device, "Invalid port=%x. " 943 "ehca_qp=%p qp_num=%x num_ports=%x", 944 attr->port_num, my_qp, ibqp->qp_num, 945 shca->num_ports); 946 goto modify_qp_exit2; 947 } 948 mqpcb->prim_phys_port = attr->port_num; 949 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_PHYS_PORT, 1); 950 } 951 if (attr_mask & IB_QP_QKEY) { 952 mqpcb->qkey = attr->qkey; 953 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_QKEY, 1); 954 } 955 if (attr_mask & IB_QP_AV) { 956 int ah_mult = ib_rate_to_mult(attr->ah_attr.static_rate); 957 int ehca_mult = ib_rate_to_mult(shca->sport[my_qp-> 958 init_attr.port_num].rate); 959 960 mqpcb->dlid = attr->ah_attr.dlid; 961 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID, 1); 962 mqpcb->source_path_bits = attr->ah_attr.src_path_bits; 963 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS, 1); 964 mqpcb->service_level = attr->ah_attr.sl; 965 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL, 1); 966 967 if (ah_mult < ehca_mult) 968 mqpcb->max_static_rate = (ah_mult > 0) ? 969 ((ehca_mult - 1) / ah_mult) : 0; 970 else 971 mqpcb->max_static_rate = 0; 972 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE, 1); 973 974 /* 975 * Always supply the GRH flag, even if it's zero, to give the 976 * hypervisor a clear "yes" or "no" instead of a "perhaps" 977 */ 978 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1); 979 980 /* 981 * only if GRH is TRUE we might consider SOURCE_GID_IDX 982 * and DEST_GID otherwise phype will return H_ATTR_PARM!!! 983 */ 984 if (attr->ah_attr.ah_flags == IB_AH_GRH) { 985 mqpcb->send_grh_flag = 1; 986 987 mqpcb->source_gid_idx = attr->ah_attr.grh.sgid_index; 988 update_mask |= 989 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX, 1); 990 991 for (cnt = 0; cnt < 16; cnt++) 992 mqpcb->dest_gid.byte[cnt] = 993 attr->ah_attr.grh.dgid.raw[cnt]; 994 995 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_GID, 1); 996 mqpcb->flow_label = attr->ah_attr.grh.flow_label; 997 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL, 1); 998 mqpcb->hop_limit = attr->ah_attr.grh.hop_limit; 999 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT, 1); 1000 mqpcb->traffic_class = attr->ah_attr.grh.traffic_class; 1001 update_mask |= 1002 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS, 1); 1003 } 1004 } 1005 1006 if (attr_mask & IB_QP_PATH_MTU) { 1007 mqpcb->path_mtu = attr->path_mtu; 1008 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PATH_MTU, 1); 1009 } 1010 if (attr_mask & IB_QP_TIMEOUT) { 1011 mqpcb->timeout = attr->timeout; 1012 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT, 1); 1013 } 1014 if (attr_mask & IB_QP_RETRY_CNT) { 1015 mqpcb->retry_count = attr->retry_cnt; 1016 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT, 1); 1017 } 1018 if (attr_mask & IB_QP_RNR_RETRY) { 1019 mqpcb->rnr_retry_count = attr->rnr_retry; 1020 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT, 1); 1021 } 1022 if (attr_mask & IB_QP_RQ_PSN) { 1023 mqpcb->receive_psn = attr->rq_psn; 1024 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RECEIVE_PSN, 1); 1025 } 1026 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1027 mqpcb->rdma_nr_atomic_resp_res = attr->max_dest_rd_atomic < 3 ? 1028 attr->max_dest_rd_atomic : 2; 1029 update_mask |= 1030 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1); 1031 } 1032 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1033 mqpcb->rdma_atomic_outst_dest_qp = attr->max_rd_atomic < 3 ? 1034 attr->max_rd_atomic : 2; 1035 update_mask |= 1036 EHCA_BMASK_SET 1037 (MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP, 1); 1038 } 1039 if (attr_mask & IB_QP_ALT_PATH) { 1040 int ah_mult = ib_rate_to_mult(attr->alt_ah_attr.static_rate); 1041 int ehca_mult = ib_rate_to_mult( 1042 shca->sport[my_qp->init_attr.port_num].rate); 1043 1044 mqpcb->dlid_al = attr->alt_ah_attr.dlid; 1045 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID_AL, 1); 1046 mqpcb->source_path_bits_al = attr->alt_ah_attr.src_path_bits; 1047 update_mask |= 1048 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS_AL, 1); 1049 mqpcb->service_level_al = attr->alt_ah_attr.sl; 1050 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL_AL, 1); 1051 1052 if (ah_mult < ehca_mult) 1053 mqpcb->max_static_rate = (ah_mult > 0) ? 1054 ((ehca_mult - 1) / ah_mult) : 0; 1055 else 1056 mqpcb->max_static_rate_al = 0; 1057 1058 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE_AL, 1); 1059 1060 /* 1061 * only if GRH is TRUE we might consider SOURCE_GID_IDX 1062 * and DEST_GID otherwise phype will return H_ATTR_PARM!!! 1063 */ 1064 if (attr->alt_ah_attr.ah_flags == IB_AH_GRH) { 1065 mqpcb->send_grh_flag_al = 1 << 31; 1066 update_mask |= 1067 EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG_AL, 1); 1068 mqpcb->source_gid_idx_al = 1069 attr->alt_ah_attr.grh.sgid_index; 1070 update_mask |= 1071 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX_AL, 1); 1072 1073 for (cnt = 0; cnt < 16; cnt++) 1074 mqpcb->dest_gid_al.byte[cnt] = 1075 attr->alt_ah_attr.grh.dgid.raw[cnt]; 1076 1077 update_mask |= 1078 EHCA_BMASK_SET(MQPCB_MASK_DEST_GID_AL, 1); 1079 mqpcb->flow_label_al = attr->alt_ah_attr.grh.flow_label; 1080 update_mask |= 1081 EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL_AL, 1); 1082 mqpcb->hop_limit_al = attr->alt_ah_attr.grh.hop_limit; 1083 update_mask |= 1084 EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT_AL, 1); 1085 mqpcb->traffic_class_al = 1086 attr->alt_ah_attr.grh.traffic_class; 1087 update_mask |= 1088 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS_AL, 1); 1089 } 1090 } 1091 1092 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 1093 mqpcb->min_rnr_nak_timer_field = attr->min_rnr_timer; 1094 update_mask |= 1095 EHCA_BMASK_SET(MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD, 1); 1096 } 1097 1098 if (attr_mask & IB_QP_SQ_PSN) { 1099 mqpcb->send_psn = attr->sq_psn; 1100 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_PSN, 1); 1101 } 1102 1103 if (attr_mask & IB_QP_DEST_QPN) { 1104 mqpcb->dest_qp_nr = attr->dest_qp_num; 1105 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_QP_NR, 1); 1106 } 1107 1108 if (attr_mask & IB_QP_PATH_MIG_STATE) { 1109 mqpcb->path_migration_state = attr->path_mig_state; 1110 update_mask |= 1111 EHCA_BMASK_SET(MQPCB_MASK_PATH_MIGRATION_STATE, 1); 1112 } 1113 1114 if (attr_mask & IB_QP_CAP) { 1115 mqpcb->max_nr_outst_send_wr = attr->cap.max_send_wr+1; 1116 update_mask |= 1117 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_SEND_WR, 1); 1118 mqpcb->max_nr_outst_recv_wr = attr->cap.max_recv_wr+1; 1119 update_mask |= 1120 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_RECV_WR, 1); 1121 /* no support for max_send/recv_sge yet */ 1122 } 1123 1124 if (ehca_debug_level) 1125 ehca_dmp(mqpcb, 4*70, "qp_num=%x", ibqp->qp_num); 1126 1127 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle, 1128 my_qp->ipz_qp_handle, 1129 &my_qp->pf, 1130 update_mask, 1131 mqpcb, my_qp->galpas.kernel); 1132 1133 if (h_ret != H_SUCCESS) { 1134 ret = ehca2ib_return_code(h_ret); 1135 ehca_err(ibqp->device, "hipz_h_modify_qp() failed rc=%lx " 1136 "ehca_qp=%p qp_num=%x",h_ret, my_qp, ibqp->qp_num); 1137 goto modify_qp_exit2; 1138 } 1139 1140 if ((my_qp->qp_type == IB_QPT_UD || 1141 my_qp->qp_type == IB_QPT_GSI || 1142 my_qp->qp_type == IB_QPT_SMI) && 1143 statetrans == IB_QPST_SQE2RTS) { 1144 /* doorbell to reprocessing wqes */ 1145 iosync(); /* serialize GAL register access */ 1146 hipz_update_sqa(my_qp, bad_wqe_cnt-1); 1147 ehca_gen_dbg("doorbell for %x wqes", bad_wqe_cnt); 1148 } 1149 1150 if (statetrans == IB_QPST_RESET2INIT || 1151 statetrans == IB_QPST_INIT2INIT) { 1152 mqpcb->qp_enable = 1; 1153 mqpcb->qp_state = EHCA_QPS_INIT; 1154 update_mask = 0; 1155 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1); 1156 1157 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle, 1158 my_qp->ipz_qp_handle, 1159 &my_qp->pf, 1160 update_mask, 1161 mqpcb, 1162 my_qp->galpas.kernel); 1163 1164 if (h_ret != H_SUCCESS) { 1165 ret = ehca2ib_return_code(h_ret); 1166 ehca_err(ibqp->device, "ENABLE in context of " 1167 "RESET_2_INIT failed! Maybe you didn't get " 1168 "a LID h_ret=%lx ehca_qp=%p qp_num=%x", 1169 h_ret, my_qp, ibqp->qp_num); 1170 goto modify_qp_exit2; 1171 } 1172 } 1173 1174 if (statetrans == IB_QPST_ANY2RESET) { 1175 ipz_qeit_reset(&my_qp->ipz_rqueue); 1176 ipz_qeit_reset(&my_qp->ipz_squeue); 1177 } 1178 1179 if (attr_mask & IB_QP_QKEY) 1180 my_qp->qkey = attr->qkey; 1181 1182modify_qp_exit2: 1183 if (squeue_locked) { /* this means: sqe -> rts */ 1184 spin_unlock_irqrestore(&my_qp->spinlock_s, spl_flags); 1185 my_qp->sqerr_purgeflag = 1; 1186 } 1187 1188modify_qp_exit1: 1189 ehca_free_fw_ctrlblock(mqpcb); 1190 1191 return ret; 1192} 1193 1194int ehca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, 1195 struct ib_udata *udata) 1196{ 1197 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp); 1198 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd, 1199 ib_pd); 1200 u32 cur_pid = current->tgid; 1201 1202 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context && 1203 my_pd->ownpid != cur_pid) { 1204 ehca_err(ibqp->pd->device, "Invalid caller pid=%x ownpid=%x", 1205 cur_pid, my_pd->ownpid); 1206 return -EINVAL; 1207 } 1208 1209 return internal_modify_qp(ibqp, attr, attr_mask, 0); 1210} 1211 1212int ehca_query_qp(struct ib_qp *qp, 1213 struct ib_qp_attr *qp_attr, 1214 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 1215{ 1216 struct ehca_qp *my_qp = container_of(qp, struct ehca_qp, ib_qp); 1217 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd, 1218 ib_pd); 1219 struct ehca_shca *shca = container_of(qp->device, struct ehca_shca, 1220 ib_device); 1221 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle; 1222 struct hcp_modify_qp_control_block *qpcb; 1223 u32 cur_pid = current->tgid; 1224 int cnt, ret = 0; 1225 u64 h_ret; 1226 1227 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context && 1228 my_pd->ownpid != cur_pid) { 1229 ehca_err(qp->device, "Invalid caller pid=%x ownpid=%x", 1230 cur_pid, my_pd->ownpid); 1231 return -EINVAL; 1232 } 1233 1234 if (qp_attr_mask & QP_ATTR_QUERY_NOT_SUPPORTED) { 1235 ehca_err(qp->device,"Invalid attribute mask " 1236 "ehca_qp=%p qp_num=%x qp_attr_mask=%x ", 1237 my_qp, qp->qp_num, qp_attr_mask); 1238 return -EINVAL; 1239 } 1240 1241 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL); 1242 if (!qpcb) { 1243 ehca_err(qp->device,"Out of memory for qpcb " 1244 "ehca_qp=%p qp_num=%x", my_qp, qp->qp_num); 1245 return -ENOMEM; 1246 } 1247 1248 h_ret = hipz_h_query_qp(adapter_handle, 1249 my_qp->ipz_qp_handle, 1250 &my_qp->pf, 1251 qpcb, my_qp->galpas.kernel); 1252 1253 if (h_ret != H_SUCCESS) { 1254 ret = ehca2ib_return_code(h_ret); 1255 ehca_err(qp->device,"hipz_h_query_qp() failed " 1256 "ehca_qp=%p qp_num=%x h_ret=%lx", 1257 my_qp, qp->qp_num, h_ret); 1258 goto query_qp_exit1; 1259 } 1260 1261 qp_attr->cur_qp_state = ehca2ib_qp_state(qpcb->qp_state); 1262 qp_attr->qp_state = qp_attr->cur_qp_state; 1263 1264 if (qp_attr->cur_qp_state == -EINVAL) { 1265 ret = -EINVAL; 1266 ehca_err(qp->device,"Got invalid ehca_qp_state=%x " 1267 "ehca_qp=%p qp_num=%x", 1268 qpcb->qp_state, my_qp, qp->qp_num); 1269 goto query_qp_exit1; 1270 } 1271 1272 if (qp_attr->qp_state == IB_QPS_SQD) 1273 qp_attr->sq_draining = 1; 1274 1275 qp_attr->qkey = qpcb->qkey; 1276 qp_attr->path_mtu = qpcb->path_mtu; 1277 qp_attr->path_mig_state = qpcb->path_migration_state; 1278 qp_attr->rq_psn = qpcb->receive_psn; 1279 qp_attr->sq_psn = qpcb->send_psn; 1280 qp_attr->min_rnr_timer = qpcb->min_rnr_nak_timer_field; 1281 qp_attr->cap.max_send_wr = qpcb->max_nr_outst_send_wr-1; 1282 qp_attr->cap.max_recv_wr = qpcb->max_nr_outst_recv_wr-1; 1283 /* UD_AV CIRCUMVENTION */ 1284 if (my_qp->qp_type == IB_QPT_UD) { 1285 qp_attr->cap.max_send_sge = 1286 qpcb->actual_nr_sges_in_sq_wqe - 2; 1287 qp_attr->cap.max_recv_sge = 1288 qpcb->actual_nr_sges_in_rq_wqe - 2; 1289 } else { 1290 qp_attr->cap.max_send_sge = 1291 qpcb->actual_nr_sges_in_sq_wqe; 1292 qp_attr->cap.max_recv_sge = 1293 qpcb->actual_nr_sges_in_rq_wqe; 1294 } 1295 1296 qp_attr->cap.max_inline_data = my_qp->sq_max_inline_data_size; 1297 qp_attr->dest_qp_num = qpcb->dest_qp_nr; 1298 1299 qp_attr->pkey_index = 1300 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->prim_p_key_idx); 1301 1302 qp_attr->port_num = 1303 EHCA_BMASK_GET(MQPCB_PRIM_PHYS_PORT, qpcb->prim_phys_port); 1304 1305 qp_attr->timeout = qpcb->timeout; 1306 qp_attr->retry_cnt = qpcb->retry_count; 1307 qp_attr->rnr_retry = qpcb->rnr_retry_count; 1308 1309 qp_attr->alt_pkey_index = 1310 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->alt_p_key_idx); 1311 1312 qp_attr->alt_port_num = qpcb->alt_phys_port; 1313 qp_attr->alt_timeout = qpcb->timeout_al; 1314 1315 /* primary av */ 1316 qp_attr->ah_attr.sl = qpcb->service_level; 1317 1318 if (qpcb->send_grh_flag) { 1319 qp_attr->ah_attr.ah_flags = IB_AH_GRH; 1320 } 1321 1322 qp_attr->ah_attr.static_rate = qpcb->max_static_rate; 1323 qp_attr->ah_attr.dlid = qpcb->dlid; 1324 qp_attr->ah_attr.src_path_bits = qpcb->source_path_bits; 1325 qp_attr->ah_attr.port_num = qp_attr->port_num; 1326 1327 /* primary GRH */ 1328 qp_attr->ah_attr.grh.traffic_class = qpcb->traffic_class; 1329 qp_attr->ah_attr.grh.hop_limit = qpcb->hop_limit; 1330 qp_attr->ah_attr.grh.sgid_index = qpcb->source_gid_idx; 1331 qp_attr->ah_attr.grh.flow_label = qpcb->flow_label; 1332 1333 for (cnt = 0; cnt < 16; cnt++) 1334 qp_attr->ah_attr.grh.dgid.raw[cnt] = 1335 qpcb->dest_gid.byte[cnt]; 1336 1337 /* alternate AV */ 1338 qp_attr->alt_ah_attr.sl = qpcb->service_level_al; 1339 if (qpcb->send_grh_flag_al) { 1340 qp_attr->alt_ah_attr.ah_flags = IB_AH_GRH; 1341 } 1342 1343 qp_attr->alt_ah_attr.static_rate = qpcb->max_static_rate_al; 1344 qp_attr->alt_ah_attr.dlid = qpcb->dlid_al; 1345 qp_attr->alt_ah_attr.src_path_bits = qpcb->source_path_bits_al; 1346 1347 /* alternate GRH */ 1348 qp_attr->alt_ah_attr.grh.traffic_class = qpcb->traffic_class_al; 1349 qp_attr->alt_ah_attr.grh.hop_limit = qpcb->hop_limit_al; 1350 qp_attr->alt_ah_attr.grh.sgid_index = qpcb->source_gid_idx_al; 1351 qp_attr->alt_ah_attr.grh.flow_label = qpcb->flow_label_al; 1352 1353 for (cnt = 0; cnt < 16; cnt++) 1354 qp_attr->alt_ah_attr.grh.dgid.raw[cnt] = 1355 qpcb->dest_gid_al.byte[cnt]; 1356 1357 /* return init attributes given in ehca_create_qp */ 1358 if (qp_init_attr) 1359 *qp_init_attr = my_qp->init_attr; 1360 1361 if (ehca_debug_level) 1362 ehca_dmp(qpcb, 4*70, "qp_num=%x", qp->qp_num); 1363 1364query_qp_exit1: 1365 ehca_free_fw_ctrlblock(qpcb); 1366 1367 return ret; 1368} 1369 1370int ehca_destroy_qp(struct ib_qp *ibqp) 1371{ 1372 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp); 1373 struct ehca_shca *shca = container_of(ibqp->device, struct ehca_shca, 1374 ib_device); 1375 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd, 1376 ib_pd); 1377 u32 cur_pid = current->tgid; 1378 u32 qp_num = ibqp->qp_num; 1379 int ret; 1380 u64 h_ret; 1381 u8 port_num; 1382 enum ib_qp_type qp_type; 1383 unsigned long flags; 1384 1385 if (ibqp->uobject) { 1386 if (my_qp->mm_count_galpa || 1387 my_qp->mm_count_rqueue || my_qp->mm_count_squeue) { 1388 ehca_err(ibqp->device, "Resources still referenced in " 1389 "user space qp_num=%x", ibqp->qp_num); 1390 return -EINVAL; 1391 } 1392 if (my_pd->ownpid != cur_pid) { 1393 ehca_err(ibqp->device, "Invalid caller pid=%x ownpid=%x", 1394 cur_pid, my_pd->ownpid); 1395 return -EINVAL; 1396 } 1397 } 1398 1399 if (my_qp->send_cq) { 1400 ret = ehca_cq_unassign_qp(my_qp->send_cq, 1401 my_qp->real_qp_num); 1402 if (ret) { 1403 ehca_err(ibqp->device, "Couldn't unassign qp from " 1404 "send_cq ret=%x qp_num=%x cq_num=%x", ret, 1405 my_qp->ib_qp.qp_num, my_qp->send_cq->cq_number); 1406 return ret; 1407 } 1408 } 1409 1410 spin_lock_irqsave(&ehca_qp_idr_lock, flags); 1411 idr_remove(&ehca_qp_idr, my_qp->token); 1412 spin_unlock_irqrestore(&ehca_qp_idr_lock, flags); 1413 1414 h_ret = hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp); 1415 if (h_ret != H_SUCCESS) { 1416 ehca_err(ibqp->device, "hipz_h_destroy_qp() failed rc=%lx " 1417 "ehca_qp=%p qp_num=%x", h_ret, my_qp, qp_num); 1418 return ehca2ib_return_code(h_ret); 1419 } 1420 1421 port_num = my_qp->init_attr.port_num; 1422 qp_type = my_qp->init_attr.qp_type; 1423 1424 /* no support for IB_QPT_SMI yet */ 1425 if (qp_type == IB_QPT_GSI) { 1426 struct ib_event event; 1427 ehca_info(ibqp->device, "device %s: port %x is inactive.", 1428 shca->ib_device.name, port_num); 1429 event.device = &shca->ib_device; 1430 event.event = IB_EVENT_PORT_ERR; 1431 event.element.port_num = port_num; 1432 shca->sport[port_num - 1].port_state = IB_PORT_DOWN; 1433 ib_dispatch_event(&event); 1434 } 1435 1436 ipz_queue_dtor(&my_qp->ipz_rqueue); 1437 ipz_queue_dtor(&my_qp->ipz_squeue); 1438 kmem_cache_free(qp_cache, my_qp); 1439 return 0; 1440} 1441 1442int ehca_init_qp_cache(void) 1443{ 1444 qp_cache = kmem_cache_create("ehca_cache_qp", 1445 sizeof(struct ehca_qp), 0, 1446 SLAB_HWCACHE_ALIGN, 1447 NULL, NULL); 1448 if (!qp_cache) 1449 return -ENOMEM; 1450 return 0; 1451} 1452 1453void ehca_cleanup_qp_cache(void) 1454{ 1455 if (qp_cache) 1456 kmem_cache_destroy(qp_cache); 1457} 1458