1/* 2 * video1394.c - video driver for OHCI 1394 boards 3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au> 4 * Peter Schlaile <udbz@rz.uni-karlsruhe.de> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 * 20 * NOTES: 21 * 22 * ioctl return codes: 23 * EFAULT is only for invalid address for the argp 24 * EINVAL for out of range values 25 * EBUSY when trying to use an already used resource 26 * ESRCH when trying to free/stop a not used resource 27 * EAGAIN for resource allocation failure that could perhaps succeed later 28 * ENOTTY for unsupported ioctl request 29 * 30 */ 31#include <linux/kernel.h> 32#include <linux/list.h> 33#include <linux/slab.h> 34#include <linux/interrupt.h> 35#include <linux/wait.h> 36#include <linux/errno.h> 37#include <linux/module.h> 38#include <linux/init.h> 39#include <linux/pci.h> 40#include <linux/fs.h> 41#include <linux/poll.h> 42#include <linux/delay.h> 43#include <linux/bitops.h> 44#include <linux/types.h> 45#include <linux/vmalloc.h> 46#include <linux/timex.h> 47#include <linux/mm.h> 48#include <linux/compat.h> 49#include <linux/cdev.h> 50 51#include "dma.h" 52#include "highlevel.h" 53#include "hosts.h" 54#include "ieee1394.h" 55#include "ieee1394_core.h" 56#include "ieee1394_hotplug.h" 57#include "ieee1394_types.h" 58#include "nodemgr.h" 59#include "ohci1394.h" 60#include "video1394.h" 61 62#define ISO_CHANNELS 64 63 64struct it_dma_prg { 65 struct dma_cmd begin; 66 quadlet_t data[4]; 67 struct dma_cmd end; 68 quadlet_t pad[4]; 69}; 70 71struct dma_iso_ctx { 72 struct ti_ohci *ohci; 73 int type; /* OHCI_ISO_TRANSMIT or OHCI_ISO_RECEIVE */ 74 struct ohci1394_iso_tasklet iso_tasklet; 75 int channel; 76 int ctx; 77 int last_buffer; 78 int * next_buffer; /* For ISO Transmit of video packets 79 to write the correct SYT field 80 into the next block */ 81 unsigned int num_desc; 82 unsigned int buf_size; 83 unsigned int frame_size; 84 unsigned int packet_size; 85 unsigned int left_size; 86 unsigned int nb_cmd; 87 88 struct dma_region dma; 89 90 struct dma_prog_region *prg_reg; 91 92 struct dma_cmd **ir_prg; 93 struct it_dma_prg **it_prg; 94 95 unsigned int *buffer_status; 96 unsigned int *buffer_prg_assignment; 97 struct timeval *buffer_time; /* time when the buffer was received */ 98 unsigned int *last_used_cmd; /* For ISO Transmit with 99 variable sized packets only ! */ 100 int ctrlClear; 101 int ctrlSet; 102 int cmdPtr; 103 int ctxMatch; 104 wait_queue_head_t waitq; 105 spinlock_t lock; 106 unsigned int syt_offset; 107 int flags; 108 109 struct list_head link; 110}; 111 112 113struct file_ctx { 114 struct ti_ohci *ohci; 115 struct list_head context_list; 116 struct dma_iso_ctx *current_ctx; 117}; 118 119#ifdef CONFIG_IEEE1394_VERBOSEDEBUG 120#define VIDEO1394_DEBUG 121#endif 122 123#ifdef DBGMSG 124#undef DBGMSG 125#endif 126 127#ifdef VIDEO1394_DEBUG 128#define DBGMSG(card, fmt, args...) \ 129printk(KERN_INFO "video1394_%d: " fmt "\n" , card , ## args) 130#else 131#define DBGMSG(card, fmt, args...) do {} while (0) 132#endif 133 134/* print general (card independent) information */ 135#define PRINT_G(level, fmt, args...) \ 136printk(level "video1394: " fmt "\n" , ## args) 137 138/* print card specific information */ 139#define PRINT(level, card, fmt, args...) \ 140printk(level "video1394_%d: " fmt "\n" , card , ## args) 141 142static void wakeup_dma_ir_ctx(unsigned long l); 143static void wakeup_dma_it_ctx(unsigned long l); 144 145static struct hpsb_highlevel video1394_highlevel; 146 147static int free_dma_iso_ctx(struct dma_iso_ctx *d) 148{ 149 int i; 150 151 DBGMSG(d->ohci->host->id, "Freeing dma_iso_ctx %d", d->ctx); 152 153 ohci1394_stop_context(d->ohci, d->ctrlClear, NULL); 154 if (d->iso_tasklet.link.next != NULL) 155 ohci1394_unregister_iso_tasklet(d->ohci, &d->iso_tasklet); 156 157 dma_region_free(&d->dma); 158 159 if (d->prg_reg) { 160 for (i = 0; i < d->num_desc; i++) 161 dma_prog_region_free(&d->prg_reg[i]); 162 kfree(d->prg_reg); 163 } 164 165 kfree(d->ir_prg); 166 kfree(d->it_prg); 167 kfree(d->buffer_status); 168 kfree(d->buffer_prg_assignment); 169 kfree(d->buffer_time); 170 kfree(d->last_used_cmd); 171 kfree(d->next_buffer); 172 list_del(&d->link); 173 kfree(d); 174 175 return 0; 176} 177 178static struct dma_iso_ctx * 179alloc_dma_iso_ctx(struct ti_ohci *ohci, int type, int num_desc, 180 int buf_size, int channel, unsigned int packet_size) 181{ 182 struct dma_iso_ctx *d; 183 int i; 184 185 d = kzalloc(sizeof(*d), GFP_KERNEL); 186 if (!d) { 187 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma_iso_ctx"); 188 return NULL; 189 } 190 191 d->ohci = ohci; 192 d->type = type; 193 d->channel = channel; 194 d->num_desc = num_desc; 195 d->frame_size = buf_size; 196 d->buf_size = PAGE_ALIGN(buf_size); 197 d->last_buffer = -1; 198 INIT_LIST_HEAD(&d->link); 199 init_waitqueue_head(&d->waitq); 200 201 /* Init the regions for easy cleanup */ 202 dma_region_init(&d->dma); 203 204 if (dma_region_alloc(&d->dma, (d->num_desc - 1) * d->buf_size, ohci->dev, 205 PCI_DMA_BIDIRECTIONAL)) { 206 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma buffer"); 207 free_dma_iso_ctx(d); 208 return NULL; 209 } 210 211 if (type == OHCI_ISO_RECEIVE) 212 ohci1394_init_iso_tasklet(&d->iso_tasklet, type, 213 wakeup_dma_ir_ctx, 214 (unsigned long) d); 215 else 216 ohci1394_init_iso_tasklet(&d->iso_tasklet, type, 217 wakeup_dma_it_ctx, 218 (unsigned long) d); 219 220 if (ohci1394_register_iso_tasklet(ohci, &d->iso_tasklet) < 0) { 221 PRINT(KERN_ERR, ohci->host->id, "no free iso %s contexts", 222 type == OHCI_ISO_RECEIVE ? "receive" : "transmit"); 223 free_dma_iso_ctx(d); 224 return NULL; 225 } 226 d->ctx = d->iso_tasklet.context; 227 228 d->prg_reg = kmalloc(d->num_desc * sizeof(*d->prg_reg), GFP_KERNEL); 229 if (!d->prg_reg) { 230 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate ir prg regs"); 231 free_dma_iso_ctx(d); 232 return NULL; 233 } 234 /* Makes for easier cleanup */ 235 for (i = 0; i < d->num_desc; i++) 236 dma_prog_region_init(&d->prg_reg[i]); 237 238 if (type == OHCI_ISO_RECEIVE) { 239 d->ctrlSet = OHCI1394_IsoRcvContextControlSet+32*d->ctx; 240 d->ctrlClear = OHCI1394_IsoRcvContextControlClear+32*d->ctx; 241 d->cmdPtr = OHCI1394_IsoRcvCommandPtr+32*d->ctx; 242 d->ctxMatch = OHCI1394_IsoRcvContextMatch+32*d->ctx; 243 244 d->ir_prg = kzalloc(d->num_desc * sizeof(*d->ir_prg), 245 GFP_KERNEL); 246 247 if (!d->ir_prg) { 248 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg"); 249 free_dma_iso_ctx(d); 250 return NULL; 251 } 252 253 d->nb_cmd = d->buf_size / PAGE_SIZE + 1; 254 d->left_size = (d->frame_size % PAGE_SIZE) ? 255 d->frame_size % PAGE_SIZE : PAGE_SIZE; 256 257 for (i = 0;i < d->num_desc; i++) { 258 if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd * 259 sizeof(struct dma_cmd), ohci->dev)) { 260 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg"); 261 free_dma_iso_ctx(d); 262 return NULL; 263 } 264 d->ir_prg[i] = (struct dma_cmd *)d->prg_reg[i].kvirt; 265 } 266 267 } else { /* OHCI_ISO_TRANSMIT */ 268 d->ctrlSet = OHCI1394_IsoXmitContextControlSet+16*d->ctx; 269 d->ctrlClear = OHCI1394_IsoXmitContextControlClear+16*d->ctx; 270 d->cmdPtr = OHCI1394_IsoXmitCommandPtr+16*d->ctx; 271 272 d->it_prg = kzalloc(d->num_desc * sizeof(*d->it_prg), 273 GFP_KERNEL); 274 275 if (!d->it_prg) { 276 PRINT(KERN_ERR, ohci->host->id, 277 "Failed to allocate dma it prg"); 278 free_dma_iso_ctx(d); 279 return NULL; 280 } 281 282 d->packet_size = packet_size; 283 284 if (PAGE_SIZE % packet_size || packet_size>4096) { 285 PRINT(KERN_ERR, ohci->host->id, 286 "Packet size %d (page_size: %ld) " 287 "not yet supported\n", 288 packet_size, PAGE_SIZE); 289 free_dma_iso_ctx(d); 290 return NULL; 291 } 292 293 d->nb_cmd = d->frame_size / d->packet_size; 294 if (d->frame_size % d->packet_size) { 295 d->nb_cmd++; 296 d->left_size = d->frame_size % d->packet_size; 297 } else 298 d->left_size = d->packet_size; 299 300 for (i = 0; i < d->num_desc; i++) { 301 if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd * 302 sizeof(struct it_dma_prg), ohci->dev)) { 303 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma it prg"); 304 free_dma_iso_ctx(d); 305 return NULL; 306 } 307 d->it_prg[i] = (struct it_dma_prg *)d->prg_reg[i].kvirt; 308 } 309 } 310 311 d->buffer_status = 312 kzalloc(d->num_desc * sizeof(*d->buffer_status), GFP_KERNEL); 313 d->buffer_prg_assignment = 314 kzalloc(d->num_desc * sizeof(*d->buffer_prg_assignment), GFP_KERNEL); 315 d->buffer_time = 316 kzalloc(d->num_desc * sizeof(*d->buffer_time), GFP_KERNEL); 317 d->last_used_cmd = 318 kzalloc(d->num_desc * sizeof(*d->last_used_cmd), GFP_KERNEL); 319 d->next_buffer = 320 kzalloc(d->num_desc * sizeof(*d->next_buffer), GFP_KERNEL); 321 322 if (!d->buffer_status || !d->buffer_prg_assignment || !d->buffer_time || 323 !d->last_used_cmd || !d->next_buffer) { 324 PRINT(KERN_ERR, ohci->host->id, 325 "Failed to allocate dma_iso_ctx member"); 326 free_dma_iso_ctx(d); 327 return NULL; 328 } 329 330 spin_lock_init(&d->lock); 331 332 DBGMSG(ohci->host->id, "Iso %s DMA: %d buffers " 333 "of size %d allocated for a frame size %d, each with %d prgs", 334 (type == OHCI_ISO_RECEIVE) ? "receive" : "transmit", 335 d->num_desc - 1, d->buf_size, d->frame_size, d->nb_cmd); 336 337 return d; 338} 339 340static void reset_ir_status(struct dma_iso_ctx *d, int n) 341{ 342 int i; 343 d->ir_prg[n][0].status = cpu_to_le32(4); 344 d->ir_prg[n][1].status = cpu_to_le32(PAGE_SIZE-4); 345 for (i = 2; i < d->nb_cmd - 1; i++) 346 d->ir_prg[n][i].status = cpu_to_le32(PAGE_SIZE); 347 d->ir_prg[n][i].status = cpu_to_le32(d->left_size); 348} 349 350static void reprogram_dma_ir_prg(struct dma_iso_ctx *d, int n, int buffer, int flags) 351{ 352 struct dma_cmd *ir_prg = d->ir_prg[n]; 353 unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size; 354 int i; 355 356 d->buffer_prg_assignment[n] = buffer; 357 358 ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf - 359 (unsigned long)d->dma.kvirt)); 360 ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, 361 (buf + 4) - (unsigned long)d->dma.kvirt)); 362 363 for (i=2;i<d->nb_cmd-1;i++) { 364 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, 365 (buf+(i-1)*PAGE_SIZE) - 366 (unsigned long)d->dma.kvirt)); 367 } 368 369 ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | 370 DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size); 371 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, 372 (buf+(i-1)*PAGE_SIZE) - (unsigned long)d->dma.kvirt)); 373} 374 375static void initialize_dma_ir_prg(struct dma_iso_ctx *d, int n, int flags) 376{ 377 struct dma_cmd *ir_prg = d->ir_prg[n]; 378 struct dma_prog_region *ir_reg = &d->prg_reg[n]; 379 unsigned long buf = (unsigned long)d->dma.kvirt; 380 int i; 381 382 /* the first descriptor will read only 4 bytes */ 383 ir_prg[0].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | 384 DMA_CTL_BRANCH | 4); 385 386 /* set the sync flag */ 387 if (flags & VIDEO1394_SYNC_FRAMES) 388 ir_prg[0].control |= cpu_to_le32(DMA_CTL_WAIT); 389 390 ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf - 391 (unsigned long)d->dma.kvirt)); 392 ir_prg[0].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg, 393 1 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1); 394 395 /* If there is *not* only one DMA page per frame (hence, d->nb_cmd==2) */ 396 if (d->nb_cmd > 2) { 397 /* The second descriptor will read PAGE_SIZE-4 bytes */ 398 ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | 399 DMA_CTL_BRANCH | (PAGE_SIZE-4)); 400 ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf + 4) - 401 (unsigned long)d->dma.kvirt)); 402 ir_prg[1].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg, 403 2 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1); 404 405 for (i = 2; i < d->nb_cmd - 1; i++) { 406 ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | 407 DMA_CTL_BRANCH | PAGE_SIZE); 408 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, 409 (buf+(i-1)*PAGE_SIZE) - 410 (unsigned long)d->dma.kvirt)); 411 412 ir_prg[i].branchAddress = 413 cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg, 414 (i + 1) * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1); 415 } 416 417 /* The last descriptor will generate an interrupt */ 418 ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | 419 DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size); 420 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, 421 (buf+(i-1)*PAGE_SIZE) - 422 (unsigned long)d->dma.kvirt)); 423 } else { 424 /* Only one DMA page is used. Read d->left_size immediately and */ 425 /* generate an interrupt as this is also the last page. */ 426 ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | 427 DMA_CTL_IRQ | DMA_CTL_BRANCH | (d->left_size-4)); 428 ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, 429 (buf + 4) - (unsigned long)d->dma.kvirt)); 430 } 431} 432 433static void initialize_dma_ir_ctx(struct dma_iso_ctx *d, int tag, int flags) 434{ 435 struct ti_ohci *ohci = (struct ti_ohci *)d->ohci; 436 int i; 437 438 d->flags = flags; 439 440 ohci1394_stop_context(ohci, d->ctrlClear, NULL); 441 442 for (i=0;i<d->num_desc;i++) { 443 initialize_dma_ir_prg(d, i, flags); 444 reset_ir_status(d, i); 445 } 446 447 /* reset the ctrl register */ 448 reg_write(ohci, d->ctrlClear, 0xf0000000); 449 450 /* Set bufferFill */ 451 reg_write(ohci, d->ctrlSet, 0x80000000); 452 453 /* Set isoch header */ 454 if (flags & VIDEO1394_INCLUDE_ISO_HEADERS) 455 reg_write(ohci, d->ctrlSet, 0x40000000); 456 457 /* Set the context match register to match on all tags, 458 sync for sync tag, and listen to d->channel */ 459 reg_write(ohci, d->ctxMatch, 0xf0000000|((tag&0xf)<<8)|d->channel); 460 461 /* Set up isoRecvIntMask to generate interrupts */ 462 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1<<d->ctx); 463} 464 465/* find which context is listening to this channel */ 466static struct dma_iso_ctx * 467find_ctx(struct list_head *list, int type, int channel) 468{ 469 struct dma_iso_ctx *ctx; 470 471 list_for_each_entry(ctx, list, link) { 472 if (ctx->type == type && ctx->channel == channel) 473 return ctx; 474 } 475 476 return NULL; 477} 478 479static void wakeup_dma_ir_ctx(unsigned long l) 480{ 481 struct dma_iso_ctx *d = (struct dma_iso_ctx *) l; 482 int i; 483 484 spin_lock(&d->lock); 485 486 for (i = 0; i < d->num_desc; i++) { 487 if (d->ir_prg[i][d->nb_cmd-1].status & cpu_to_le32(0xFFFF0000)) { 488 reset_ir_status(d, i); 489 d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY; 490 do_gettimeofday(&d->buffer_time[d->buffer_prg_assignment[i]]); 491 dma_region_sync_for_cpu(&d->dma, 492 d->buffer_prg_assignment[i] * d->buf_size, 493 d->buf_size); 494 } 495 } 496 497 spin_unlock(&d->lock); 498 499 if (waitqueue_active(&d->waitq)) 500 wake_up_interruptible(&d->waitq); 501} 502 503static inline void put_timestamp(struct ti_ohci *ohci, struct dma_iso_ctx * d, 504 int n) 505{ 506 unsigned char* buf = d->dma.kvirt + n * d->buf_size; 507 u32 cycleTimer; 508 u32 timeStamp; 509 510 if (n == -1) { 511 return; 512 } 513 514 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 515 516 timeStamp = ((cycleTimer & 0x0fff) + d->syt_offset); /* 11059 = 450 us */ 517 timeStamp = (timeStamp % 3072 + ((timeStamp / 3072) << 12) 518 + (cycleTimer & 0xf000)) & 0xffff; 519 520 buf[6] = timeStamp >> 8; 521 buf[7] = timeStamp & 0xff; 522 523 /* if first packet is empty packet, then put timestamp into the next full one too */ 524 if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) { 525 buf += d->packet_size; 526 buf[6] = timeStamp >> 8; 527 buf[7] = timeStamp & 0xff; 528 } 529 530 /* do the next buffer frame too in case of irq latency */ 531 n = d->next_buffer[n]; 532 if (n == -1) { 533 return; 534 } 535 buf = d->dma.kvirt + n * d->buf_size; 536 537 timeStamp += (d->last_used_cmd[n] << 12) & 0xffff; 538 539 buf[6] = timeStamp >> 8; 540 buf[7] = timeStamp & 0xff; 541 542 /* if first packet is empty packet, then put timestamp into the next full one too */ 543 if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) { 544 buf += d->packet_size; 545 buf[6] = timeStamp >> 8; 546 buf[7] = timeStamp & 0xff; 547 } 548 549} 550 551static void wakeup_dma_it_ctx(unsigned long l) 552{ 553 struct dma_iso_ctx *d = (struct dma_iso_ctx *) l; 554 struct ti_ohci *ohci = d->ohci; 555 int i; 556 557 spin_lock(&d->lock); 558 559 for (i = 0; i < d->num_desc; i++) { 560 if (d->it_prg[i][d->last_used_cmd[i]].end.status & 561 cpu_to_le32(0xFFFF0000)) { 562 int next = d->next_buffer[i]; 563 put_timestamp(ohci, d, next); 564 d->it_prg[i][d->last_used_cmd[i]].end.status = 0; 565 d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY; 566 } 567 } 568 569 spin_unlock(&d->lock); 570 571 if (waitqueue_active(&d->waitq)) 572 wake_up_interruptible(&d->waitq); 573} 574 575static void reprogram_dma_it_prg(struct dma_iso_ctx *d, int n, int buffer) 576{ 577 struct it_dma_prg *it_prg = d->it_prg[n]; 578 unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size; 579 int i; 580 581 d->buffer_prg_assignment[n] = buffer; 582 for (i=0;i<d->nb_cmd;i++) { 583 it_prg[i].end.address = 584 cpu_to_le32(dma_region_offset_to_bus(&d->dma, 585 (buf+i*d->packet_size) - (unsigned long)d->dma.kvirt)); 586 } 587} 588 589static void initialize_dma_it_prg(struct dma_iso_ctx *d, int n, int sync_tag) 590{ 591 struct it_dma_prg *it_prg = d->it_prg[n]; 592 struct dma_prog_region *it_reg = &d->prg_reg[n]; 593 unsigned long buf = (unsigned long)d->dma.kvirt; 594 int i; 595 d->last_used_cmd[n] = d->nb_cmd - 1; 596 for (i=0;i<d->nb_cmd;i++) { 597 598 it_prg[i].begin.control = cpu_to_le32(DMA_CTL_OUTPUT_MORE | 599 DMA_CTL_IMMEDIATE | 8) ; 600 it_prg[i].begin.address = 0; 601 602 it_prg[i].begin.status = 0; 603 604 it_prg[i].data[0] = cpu_to_le32( 605 (IEEE1394_SPEED_100 << 16) 606 | (/* tag */ 1 << 14) 607 | (d->channel << 8) 608 | (TCODE_ISO_DATA << 4)); 609 if (i==0) it_prg[i].data[0] |= cpu_to_le32(sync_tag); 610 it_prg[i].data[1] = cpu_to_le32(d->packet_size << 16); 611 it_prg[i].data[2] = 0; 612 it_prg[i].data[3] = 0; 613 614 it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | 615 DMA_CTL_BRANCH); 616 it_prg[i].end.address = 617 cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf+i*d->packet_size) - 618 (unsigned long)d->dma.kvirt)); 619 620 if (i<d->nb_cmd-1) { 621 it_prg[i].end.control |= cpu_to_le32(d->packet_size); 622 it_prg[i].begin.branchAddress = 623 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) * 624 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3); 625 it_prg[i].end.branchAddress = 626 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) * 627 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3); 628 } else { 629 /* the last prg generates an interrupt */ 630 it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE | 631 DMA_CTL_IRQ | d->left_size); 632 /* the last prg doesn't branch */ 633 it_prg[i].begin.branchAddress = 0; 634 it_prg[i].end.branchAddress = 0; 635 } 636 it_prg[i].end.status = 0; 637 } 638} 639 640static void initialize_dma_it_prg_var_packet_queue( 641 struct dma_iso_ctx *d, int n, unsigned int * packet_sizes, 642 struct ti_ohci *ohci) 643{ 644 struct it_dma_prg *it_prg = d->it_prg[n]; 645 struct dma_prog_region *it_reg = &d->prg_reg[n]; 646 int i; 647 648 d->last_used_cmd[n] = d->nb_cmd - 1; 649 650 for (i = 0; i < d->nb_cmd; i++) { 651 unsigned int size; 652 if (packet_sizes[i] > d->packet_size) { 653 size = d->packet_size; 654 } else { 655 size = packet_sizes[i]; 656 } 657 it_prg[i].data[1] = cpu_to_le32(size << 16); 658 it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH); 659 660 if (i < d->nb_cmd-1 && packet_sizes[i+1] != 0) { 661 it_prg[i].end.control |= cpu_to_le32(size); 662 it_prg[i].begin.branchAddress = 663 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) * 664 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3); 665 it_prg[i].end.branchAddress = 666 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) * 667 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3); 668 } else { 669 /* the last prg generates an interrupt */ 670 it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE | 671 DMA_CTL_IRQ | size); 672 /* the last prg doesn't branch */ 673 it_prg[i].begin.branchAddress = 0; 674 it_prg[i].end.branchAddress = 0; 675 d->last_used_cmd[n] = i; 676 break; 677 } 678 } 679} 680 681static void initialize_dma_it_ctx(struct dma_iso_ctx *d, int sync_tag, 682 unsigned int syt_offset, int flags) 683{ 684 struct ti_ohci *ohci = (struct ti_ohci *)d->ohci; 685 int i; 686 687 d->flags = flags; 688 d->syt_offset = (syt_offset == 0 ? 11000 : syt_offset); 689 690 ohci1394_stop_context(ohci, d->ctrlClear, NULL); 691 692 for (i=0;i<d->num_desc;i++) 693 initialize_dma_it_prg(d, i, sync_tag); 694 695 /* Set up isoRecvIntMask to generate interrupts */ 696 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1<<d->ctx); 697} 698 699static inline unsigned video1394_buffer_state(struct dma_iso_ctx *d, 700 unsigned int buffer) 701{ 702 unsigned long flags; 703 unsigned int ret; 704 spin_lock_irqsave(&d->lock, flags); 705 ret = d->buffer_status[buffer]; 706 spin_unlock_irqrestore(&d->lock, flags); 707 return ret; 708} 709 710static long video1394_ioctl(struct file *file, 711 unsigned int cmd, unsigned long arg) 712{ 713 struct file_ctx *ctx = (struct file_ctx *)file->private_data; 714 struct ti_ohci *ohci = ctx->ohci; 715 unsigned long flags; 716 void __user *argp = (void __user *)arg; 717 718 switch(cmd) 719 { 720 case VIDEO1394_IOC_LISTEN_CHANNEL: 721 case VIDEO1394_IOC_TALK_CHANNEL: 722 { 723 struct video1394_mmap v; 724 u64 mask; 725 struct dma_iso_ctx *d; 726 int i; 727 728 if (copy_from_user(&v, argp, sizeof(v))) 729 return -EFAULT; 730 731 /* if channel < 0, find lowest available one */ 732 if (v.channel < 0) { 733 mask = (u64)0x1; 734 for (i=0; ; i++) { 735 if (i == ISO_CHANNELS) { 736 PRINT(KERN_ERR, ohci->host->id, 737 "No free channel found"); 738 return -EAGAIN; 739 } 740 if (!(ohci->ISO_channel_usage & mask)) { 741 v.channel = i; 742 PRINT(KERN_INFO, ohci->host->id, "Found free channel %d", i); 743 break; 744 } 745 mask = mask << 1; 746 } 747 } else if (v.channel >= ISO_CHANNELS) { 748 PRINT(KERN_ERR, ohci->host->id, 749 "Iso channel %d out of bounds", v.channel); 750 return -EINVAL; 751 } else { 752 mask = (u64)0x1<<v.channel; 753 } 754 DBGMSG(ohci->host->id, "mask: %08X%08X usage: %08X%08X\n", 755 (u32)(mask>>32),(u32)(mask&0xffffffff), 756 (u32)(ohci->ISO_channel_usage>>32), 757 (u32)(ohci->ISO_channel_usage&0xffffffff)); 758 if (ohci->ISO_channel_usage & mask) { 759 PRINT(KERN_ERR, ohci->host->id, 760 "Channel %d is already taken", v.channel); 761 return -EBUSY; 762 } 763 764 if (v.buf_size == 0 || v.buf_size > VIDEO1394_MAX_SIZE) { 765 PRINT(KERN_ERR, ohci->host->id, 766 "Invalid %d length buffer requested",v.buf_size); 767 return -EINVAL; 768 } 769 770 if (v.nb_buffers == 0 || v.nb_buffers > VIDEO1394_MAX_SIZE) { 771 PRINT(KERN_ERR, ohci->host->id, 772 "Invalid %d buffers requested",v.nb_buffers); 773 return -EINVAL; 774 } 775 776 if (v.nb_buffers * v.buf_size > VIDEO1394_MAX_SIZE) { 777 PRINT(KERN_ERR, ohci->host->id, 778 "%d buffers of size %d bytes is too big", 779 v.nb_buffers, v.buf_size); 780 return -EINVAL; 781 } 782 783 if (cmd == VIDEO1394_IOC_LISTEN_CHANNEL) { 784 d = alloc_dma_iso_ctx(ohci, OHCI_ISO_RECEIVE, 785 v.nb_buffers + 1, v.buf_size, 786 v.channel, 0); 787 788 if (d == NULL) { 789 PRINT(KERN_ERR, ohci->host->id, 790 "Couldn't allocate ir context"); 791 return -EAGAIN; 792 } 793 initialize_dma_ir_ctx(d, v.sync_tag, v.flags); 794 795 ctx->current_ctx = d; 796 797 v.buf_size = d->buf_size; 798 list_add_tail(&d->link, &ctx->context_list); 799 800 DBGMSG(ohci->host->id, 801 "iso context %d listen on channel %d", 802 d->ctx, v.channel); 803 } 804 else { 805 d = alloc_dma_iso_ctx(ohci, OHCI_ISO_TRANSMIT, 806 v.nb_buffers + 1, v.buf_size, 807 v.channel, v.packet_size); 808 809 if (d == NULL) { 810 PRINT(KERN_ERR, ohci->host->id, 811 "Couldn't allocate it context"); 812 return -EAGAIN; 813 } 814 initialize_dma_it_ctx(d, v.sync_tag, 815 v.syt_offset, v.flags); 816 817 ctx->current_ctx = d; 818 819 v.buf_size = d->buf_size; 820 821 list_add_tail(&d->link, &ctx->context_list); 822 823 DBGMSG(ohci->host->id, 824 "Iso context %d talk on channel %d", d->ctx, 825 v.channel); 826 } 827 828 if (copy_to_user(argp, &v, sizeof(v))) { 829 return -EFAULT; 830 } 831 832 ohci->ISO_channel_usage |= mask; 833 834 return 0; 835 } 836 case VIDEO1394_IOC_UNLISTEN_CHANNEL: 837 case VIDEO1394_IOC_UNTALK_CHANNEL: 838 { 839 int channel; 840 u64 mask; 841 struct dma_iso_ctx *d; 842 843 if (copy_from_user(&channel, argp, sizeof(int))) 844 return -EFAULT; 845 846 if (channel < 0 || channel >= ISO_CHANNELS) { 847 PRINT(KERN_ERR, ohci->host->id, 848 "Iso channel %d out of bound", channel); 849 return -EINVAL; 850 } 851 mask = (u64)0x1<<channel; 852 if (!(ohci->ISO_channel_usage & mask)) { 853 PRINT(KERN_ERR, ohci->host->id, 854 "Channel %d is not being used", channel); 855 return -ESRCH; 856 } 857 858 /* Mark this channel as unused */ 859 ohci->ISO_channel_usage &= ~mask; 860 861 if (cmd == VIDEO1394_IOC_UNLISTEN_CHANNEL) 862 d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, channel); 863 else 864 d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, channel); 865 866 if (d == NULL) return -ESRCH; 867 DBGMSG(ohci->host->id, "Iso context %d " 868 "stop talking on channel %d", d->ctx, channel); 869 free_dma_iso_ctx(d); 870 871 return 0; 872 } 873 case VIDEO1394_IOC_LISTEN_QUEUE_BUFFER: 874 { 875 struct video1394_wait v; 876 struct dma_iso_ctx *d; 877 int next_prg; 878 879 if (unlikely(copy_from_user(&v, argp, sizeof(v)))) 880 return -EFAULT; 881 882 d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel); 883 if (unlikely(d == NULL)) 884 return -EFAULT; 885 886 if (unlikely((v.buffer<0) || (v.buffer>=d->num_desc - 1))) { 887 PRINT(KERN_ERR, ohci->host->id, 888 "Buffer %d out of range",v.buffer); 889 return -EINVAL; 890 } 891 892 spin_lock_irqsave(&d->lock,flags); 893 894 if (unlikely(d->buffer_status[v.buffer]==VIDEO1394_BUFFER_QUEUED)) { 895 PRINT(KERN_ERR, ohci->host->id, 896 "Buffer %d is already used",v.buffer); 897 spin_unlock_irqrestore(&d->lock,flags); 898 return -EBUSY; 899 } 900 901 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED; 902 903 next_prg = (d->last_buffer + 1) % d->num_desc; 904 if (d->last_buffer>=0) 905 d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 906 cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0) 907 & 0xfffffff0) | 0x1); 908 909 d->last_buffer = next_prg; 910 reprogram_dma_ir_prg(d, d->last_buffer, v.buffer, d->flags); 911 912 d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 0; 913 914 spin_unlock_irqrestore(&d->lock,flags); 915 916 if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) 917 { 918 DBGMSG(ohci->host->id, "Starting iso DMA ctx=%d",d->ctx); 919 920 /* Tell the controller where the first program is */ 921 reg_write(ohci, d->cmdPtr, 922 dma_prog_region_offset_to_bus(&d->prg_reg[d->last_buffer], 0) | 0x1); 923 924 /* Run IR context */ 925 reg_write(ohci, d->ctrlSet, 0x8000); 926 } 927 else { 928 /* Wake up dma context if necessary */ 929 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) { 930 DBGMSG(ohci->host->id, 931 "Waking up iso dma ctx=%d", d->ctx); 932 reg_write(ohci, d->ctrlSet, 0x1000); 933 } 934 } 935 return 0; 936 937 } 938 case VIDEO1394_IOC_LISTEN_WAIT_BUFFER: 939 case VIDEO1394_IOC_LISTEN_POLL_BUFFER: 940 { 941 struct video1394_wait v; 942 struct dma_iso_ctx *d; 943 int i = 0; 944 945 if (unlikely(copy_from_user(&v, argp, sizeof(v)))) 946 return -EFAULT; 947 948 d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel); 949 if (unlikely(d == NULL)) 950 return -EFAULT; 951 952 if (unlikely((v.buffer<0) || (v.buffer>d->num_desc - 1))) { 953 PRINT(KERN_ERR, ohci->host->id, 954 "Buffer %d out of range",v.buffer); 955 return -EINVAL; 956 } 957 958 /* 959 * I change the way it works so that it returns 960 * the last received frame. 961 */ 962 spin_lock_irqsave(&d->lock, flags); 963 switch(d->buffer_status[v.buffer]) { 964 case VIDEO1394_BUFFER_READY: 965 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE; 966 break; 967 case VIDEO1394_BUFFER_QUEUED: 968 if (cmd == VIDEO1394_IOC_LISTEN_POLL_BUFFER) { 969 /* for polling, return error code EINTR */ 970 spin_unlock_irqrestore(&d->lock, flags); 971 return -EINTR; 972 } 973 974 spin_unlock_irqrestore(&d->lock, flags); 975 wait_event_interruptible(d->waitq, 976 video1394_buffer_state(d, v.buffer) == 977 VIDEO1394_BUFFER_READY); 978 if (signal_pending(current)) 979 return -EINTR; 980 spin_lock_irqsave(&d->lock, flags); 981 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE; 982 break; 983 default: 984 PRINT(KERN_ERR, ohci->host->id, 985 "Buffer %d is not queued",v.buffer); 986 spin_unlock_irqrestore(&d->lock, flags); 987 return -ESRCH; 988 } 989 990 /* set time of buffer */ 991 v.filltime = d->buffer_time[v.buffer]; 992 993 /* 994 * Look ahead to see how many more buffers have been received 995 */ 996 i=0; 997 while (d->buffer_status[(v.buffer+1)%(d->num_desc - 1)]== 998 VIDEO1394_BUFFER_READY) { 999 v.buffer=(v.buffer+1)%(d->num_desc - 1); 1000 i++; 1001 } 1002 spin_unlock_irqrestore(&d->lock, flags); 1003 1004 v.buffer=i; 1005 if (unlikely(copy_to_user(argp, &v, sizeof(v)))) 1006 return -EFAULT; 1007 1008 return 0; 1009 } 1010 case VIDEO1394_IOC_TALK_QUEUE_BUFFER: 1011 { 1012 struct video1394_wait v; 1013 unsigned int *psizes = NULL; 1014 struct dma_iso_ctx *d; 1015 int next_prg; 1016 1017 if (copy_from_user(&v, argp, sizeof(v))) 1018 return -EFAULT; 1019 1020 d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel); 1021 if (d == NULL) return -EFAULT; 1022 1023 if ((v.buffer<0) || (v.buffer>=d->num_desc - 1)) { 1024 PRINT(KERN_ERR, ohci->host->id, 1025 "Buffer %d out of range",v.buffer); 1026 return -EINVAL; 1027 } 1028 1029 if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) { 1030 int buf_size = d->nb_cmd * sizeof(*psizes); 1031 struct video1394_queue_variable __user *p = argp; 1032 unsigned int __user *qv; 1033 1034 if (get_user(qv, &p->packet_sizes)) 1035 return -EFAULT; 1036 1037 psizes = kmalloc(buf_size, GFP_KERNEL); 1038 if (!psizes) 1039 return -ENOMEM; 1040 1041 if (copy_from_user(psizes, qv, buf_size)) { 1042 kfree(psizes); 1043 return -EFAULT; 1044 } 1045 } 1046 1047 spin_lock_irqsave(&d->lock,flags); 1048 1049 /* last_buffer is last_prg */ 1050 next_prg = (d->last_buffer + 1) % d->num_desc; 1051 if (d->buffer_status[v.buffer]!=VIDEO1394_BUFFER_FREE) { 1052 PRINT(KERN_ERR, ohci->host->id, 1053 "Buffer %d is already used",v.buffer); 1054 spin_unlock_irqrestore(&d->lock,flags); 1055 kfree(psizes); 1056 return -EBUSY; 1057 } 1058 1059 if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) { 1060 initialize_dma_it_prg_var_packet_queue( 1061 d, next_prg, psizes, ohci); 1062 } 1063 1064 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED; 1065 1066 if (d->last_buffer >= 0) { 1067 d->it_prg[d->last_buffer] 1068 [ d->last_used_cmd[d->last_buffer] ].end.branchAddress = 1069 cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 1070 0) & 0xfffffff0) | 0x3); 1071 1072 d->it_prg[d->last_buffer] 1073 [ d->last_used_cmd[d->last_buffer] ].begin.branchAddress = 1074 cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 1075 0) & 0xfffffff0) | 0x3); 1076 d->next_buffer[d->last_buffer] = (v.buffer + 1) % (d->num_desc - 1); 1077 } 1078 d->last_buffer = next_prg; 1079 reprogram_dma_it_prg(d, d->last_buffer, v.buffer); 1080 d->next_buffer[d->last_buffer] = -1; 1081 1082 d->it_prg[d->last_buffer][d->last_used_cmd[d->last_buffer]].end.branchAddress = 0; 1083 1084 spin_unlock_irqrestore(&d->lock,flags); 1085 1086 if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) 1087 { 1088 DBGMSG(ohci->host->id, "Starting iso transmit DMA ctx=%d", 1089 d->ctx); 1090 put_timestamp(ohci, d, d->last_buffer); 1091 dma_region_sync_for_device(&d->dma, 1092 v.buffer * d->buf_size, d->buf_size); 1093 1094 /* Tell the controller where the first program is */ 1095 reg_write(ohci, d->cmdPtr, 1096 dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0) | 0x3); 1097 1098 /* Run IT context */ 1099 reg_write(ohci, d->ctrlSet, 0x8000); 1100 } 1101 else { 1102 /* Wake up dma context if necessary */ 1103 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) { 1104 DBGMSG(ohci->host->id, 1105 "Waking up iso transmit dma ctx=%d", 1106 d->ctx); 1107 put_timestamp(ohci, d, d->last_buffer); 1108 dma_region_sync_for_device(&d->dma, 1109 v.buffer * d->buf_size, d->buf_size); 1110 1111 reg_write(ohci, d->ctrlSet, 0x1000); 1112 } 1113 } 1114 1115 kfree(psizes); 1116 return 0; 1117 1118 } 1119 case VIDEO1394_IOC_TALK_WAIT_BUFFER: 1120 { 1121 struct video1394_wait v; 1122 struct dma_iso_ctx *d; 1123 1124 if (copy_from_user(&v, argp, sizeof(v))) 1125 return -EFAULT; 1126 1127 d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel); 1128 if (d == NULL) return -EFAULT; 1129 1130 if ((v.buffer<0) || (v.buffer>=d->num_desc-1)) { 1131 PRINT(KERN_ERR, ohci->host->id, 1132 "Buffer %d out of range",v.buffer); 1133 return -EINVAL; 1134 } 1135 1136 switch(d->buffer_status[v.buffer]) { 1137 case VIDEO1394_BUFFER_READY: 1138 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE; 1139 return 0; 1140 case VIDEO1394_BUFFER_QUEUED: 1141 wait_event_interruptible(d->waitq, 1142 (d->buffer_status[v.buffer] == VIDEO1394_BUFFER_READY)); 1143 if (signal_pending(current)) 1144 return -EINTR; 1145 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE; 1146 return 0; 1147 default: 1148 PRINT(KERN_ERR, ohci->host->id, 1149 "Buffer %d is not queued",v.buffer); 1150 return -ESRCH; 1151 } 1152 } 1153 default: 1154 return -ENOTTY; 1155 } 1156} 1157 1158 1159static int video1394_mmap(struct file *file, struct vm_area_struct *vma) 1160{ 1161 struct file_ctx *ctx = (struct file_ctx *)file->private_data; 1162 1163 if (ctx->current_ctx == NULL) { 1164 PRINT(KERN_ERR, ctx->ohci->host->id, 1165 "Current iso context not set"); 1166 return -EINVAL; 1167 } 1168 1169 return dma_region_mmap(&ctx->current_ctx->dma, file, vma); 1170} 1171 1172static unsigned int video1394_poll(struct file *file, poll_table *pt) 1173{ 1174 struct file_ctx *ctx; 1175 unsigned int mask = 0; 1176 unsigned long flags; 1177 struct dma_iso_ctx *d; 1178 int i; 1179 1180 ctx = file->private_data; 1181 d = ctx->current_ctx; 1182 if (d == NULL) { 1183 PRINT(KERN_ERR, ctx->ohci->host->id, 1184 "Current iso context not set"); 1185 return POLLERR; 1186 } 1187 1188 poll_wait(file, &d->waitq, pt); 1189 1190 spin_lock_irqsave(&d->lock, flags); 1191 for (i = 0; i < d->num_desc; i++) { 1192 if (d->buffer_status[i] == VIDEO1394_BUFFER_READY) { 1193 mask |= POLLIN | POLLRDNORM; 1194 break; 1195 } 1196 } 1197 spin_unlock_irqrestore(&d->lock, flags); 1198 1199 return mask; 1200} 1201 1202static int video1394_open(struct inode *inode, struct file *file) 1203{ 1204 int i = ieee1394_file_to_instance(file); 1205 struct ti_ohci *ohci; 1206 struct file_ctx *ctx; 1207 1208 ohci = hpsb_get_hostinfo_bykey(&video1394_highlevel, i); 1209 if (ohci == NULL) 1210 return -EIO; 1211 1212 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 1213 if (!ctx) { 1214 PRINT(KERN_ERR, ohci->host->id, "Cannot malloc file_ctx"); 1215 return -ENOMEM; 1216 } 1217 1218 ctx->ohci = ohci; 1219 INIT_LIST_HEAD(&ctx->context_list); 1220 ctx->current_ctx = NULL; 1221 file->private_data = ctx; 1222 1223 return 0; 1224} 1225 1226static int video1394_release(struct inode *inode, struct file *file) 1227{ 1228 struct file_ctx *ctx = (struct file_ctx *)file->private_data; 1229 struct ti_ohci *ohci = ctx->ohci; 1230 struct list_head *lh, *next; 1231 u64 mask; 1232 1233 list_for_each_safe(lh, next, &ctx->context_list) { 1234 struct dma_iso_ctx *d; 1235 d = list_entry(lh, struct dma_iso_ctx, link); 1236 mask = (u64) 1 << d->channel; 1237 1238 if (!(ohci->ISO_channel_usage & mask)) 1239 PRINT(KERN_ERR, ohci->host->id, "On release: Channel %d " 1240 "is not being used", d->channel); 1241 else 1242 ohci->ISO_channel_usage &= ~mask; 1243 DBGMSG(ohci->host->id, "On release: Iso %s context " 1244 "%d stop listening on channel %d", 1245 d->type == OHCI_ISO_RECEIVE ? "receive" : "transmit", 1246 d->ctx, d->channel); 1247 free_dma_iso_ctx(d); 1248 } 1249 1250 kfree(ctx); 1251 file->private_data = NULL; 1252 1253 return 0; 1254} 1255 1256#ifdef CONFIG_COMPAT 1257static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg); 1258#endif 1259 1260static struct cdev video1394_cdev; 1261static const struct file_operations video1394_fops= 1262{ 1263 .owner = THIS_MODULE, 1264 .unlocked_ioctl = video1394_ioctl, 1265#ifdef CONFIG_COMPAT 1266 .compat_ioctl = video1394_compat_ioctl, 1267#endif 1268 .poll = video1394_poll, 1269 .mmap = video1394_mmap, 1270 .open = video1394_open, 1271 .release = video1394_release 1272}; 1273 1274/*** HOTPLUG STUFF **********************************************************/ 1275/* 1276 * Export information about protocols/devices supported by this driver. 1277 */ 1278static struct ieee1394_device_id video1394_id_table[] = { 1279 { 1280 .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION, 1281 .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff, 1282 .version = CAMERA_SW_VERSION_ENTRY & 0xffffff 1283 }, 1284 { 1285 .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION, 1286 .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff, 1287 .version = (CAMERA_SW_VERSION_ENTRY + 1) & 0xffffff 1288 }, 1289 { 1290 .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION, 1291 .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff, 1292 .version = (CAMERA_SW_VERSION_ENTRY + 2) & 0xffffff 1293 }, 1294 { } 1295}; 1296 1297MODULE_DEVICE_TABLE(ieee1394, video1394_id_table); 1298 1299static struct hpsb_protocol_driver video1394_driver = { 1300 .name = VIDEO1394_DRIVER_NAME, 1301 .id_table = video1394_id_table, 1302}; 1303 1304 1305static void video1394_add_host (struct hpsb_host *host) 1306{ 1307 struct ti_ohci *ohci; 1308 int minor; 1309 1310 /* We only work with the OHCI-1394 driver */ 1311 if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME)) 1312 return; 1313 1314 ohci = (struct ti_ohci *)host->hostdata; 1315 1316 if (!hpsb_create_hostinfo(&video1394_highlevel, host, 0)) { 1317 PRINT(KERN_ERR, ohci->host->id, "Cannot allocate hostinfo"); 1318 return; 1319 } 1320 1321 hpsb_set_hostinfo(&video1394_highlevel, host, ohci); 1322 hpsb_set_hostinfo_key(&video1394_highlevel, host, ohci->host->id); 1323 1324 minor = IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id; 1325 class_device_create(hpsb_protocol_class, NULL, MKDEV( 1326 IEEE1394_MAJOR, minor), 1327 NULL, "%s-%d", VIDEO1394_DRIVER_NAME, ohci->host->id); 1328} 1329 1330 1331static void video1394_remove_host (struct hpsb_host *host) 1332{ 1333 struct ti_ohci *ohci = hpsb_get_hostinfo(&video1394_highlevel, host); 1334 1335 if (ohci) 1336 class_device_destroy(hpsb_protocol_class, MKDEV(IEEE1394_MAJOR, 1337 IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id)); 1338 return; 1339} 1340 1341 1342static struct hpsb_highlevel video1394_highlevel = { 1343 .name = VIDEO1394_DRIVER_NAME, 1344 .add_host = video1394_add_host, 1345 .remove_host = video1394_remove_host, 1346}; 1347 1348MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>"); 1349MODULE_DESCRIPTION("driver for digital video on OHCI board"); 1350MODULE_SUPPORTED_DEVICE(VIDEO1394_DRIVER_NAME); 1351MODULE_LICENSE("GPL"); 1352 1353#ifdef CONFIG_COMPAT 1354 1355#define VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER \ 1356 _IOW ('#', 0x12, struct video1394_wait32) 1357#define VIDEO1394_IOC32_LISTEN_WAIT_BUFFER \ 1358 _IOWR('#', 0x13, struct video1394_wait32) 1359#define VIDEO1394_IOC32_TALK_WAIT_BUFFER \ 1360 _IOW ('#', 0x17, struct video1394_wait32) 1361#define VIDEO1394_IOC32_LISTEN_POLL_BUFFER \ 1362 _IOWR('#', 0x18, struct video1394_wait32) 1363 1364struct video1394_wait32 { 1365 u32 channel; 1366 u32 buffer; 1367 struct compat_timeval filltime; 1368}; 1369 1370static int video1394_wr_wait32(struct file *file, unsigned int cmd, unsigned long arg) 1371{ 1372 struct video1394_wait32 __user *argp = (void __user *)arg; 1373 struct video1394_wait32 wait32; 1374 struct video1394_wait wait; 1375 mm_segment_t old_fs; 1376 int ret; 1377 1378 if (copy_from_user(&wait32, argp, sizeof(wait32))) 1379 return -EFAULT; 1380 1381 wait.channel = wait32.channel; 1382 wait.buffer = wait32.buffer; 1383 wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec; 1384 wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec; 1385 1386 old_fs = get_fs(); 1387 set_fs(KERNEL_DS); 1388 if (cmd == VIDEO1394_IOC32_LISTEN_WAIT_BUFFER) 1389 ret = video1394_ioctl(file, 1390 VIDEO1394_IOC_LISTEN_WAIT_BUFFER, 1391 (unsigned long) &wait); 1392 else 1393 ret = video1394_ioctl(file, 1394 VIDEO1394_IOC_LISTEN_POLL_BUFFER, 1395 (unsigned long) &wait); 1396 set_fs(old_fs); 1397 1398 if (!ret) { 1399 wait32.channel = wait.channel; 1400 wait32.buffer = wait.buffer; 1401 wait32.filltime.tv_sec = (int)wait.filltime.tv_sec; 1402 wait32.filltime.tv_usec = (int)wait.filltime.tv_usec; 1403 1404 if (copy_to_user(argp, &wait32, sizeof(wait32))) 1405 ret = -EFAULT; 1406 } 1407 1408 return ret; 1409} 1410 1411static int video1394_w_wait32(struct file *file, unsigned int cmd, unsigned long arg) 1412{ 1413 struct video1394_wait32 wait32; 1414 struct video1394_wait wait; 1415 mm_segment_t old_fs; 1416 int ret; 1417 1418 if (copy_from_user(&wait32, (void __user *)arg, sizeof(wait32))) 1419 return -EFAULT; 1420 1421 wait.channel = wait32.channel; 1422 wait.buffer = wait32.buffer; 1423 wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec; 1424 wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec; 1425 1426 old_fs = get_fs(); 1427 set_fs(KERNEL_DS); 1428 if (cmd == VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER) 1429 ret = video1394_ioctl(file, 1430 VIDEO1394_IOC_LISTEN_QUEUE_BUFFER, 1431 (unsigned long) &wait); 1432 else 1433 ret = video1394_ioctl(file, 1434 VIDEO1394_IOC_TALK_WAIT_BUFFER, 1435 (unsigned long) &wait); 1436 set_fs(old_fs); 1437 1438 return ret; 1439} 1440 1441static int video1394_queue_buf32(struct file *file, unsigned int cmd, unsigned long arg) 1442{ 1443 return -EFAULT; /* ??? was there before. */ 1444 1445 return video1394_ioctl(file, 1446 VIDEO1394_IOC_TALK_QUEUE_BUFFER, arg); 1447} 1448 1449static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg) 1450{ 1451 switch (cmd) { 1452 case VIDEO1394_IOC_LISTEN_CHANNEL: 1453 case VIDEO1394_IOC_UNLISTEN_CHANNEL: 1454 case VIDEO1394_IOC_TALK_CHANNEL: 1455 case VIDEO1394_IOC_UNTALK_CHANNEL: 1456 return video1394_ioctl(f, cmd, arg); 1457 1458 case VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER: 1459 return video1394_w_wait32(f, cmd, arg); 1460 case VIDEO1394_IOC32_LISTEN_WAIT_BUFFER: 1461 return video1394_wr_wait32(f, cmd, arg); 1462 case VIDEO1394_IOC_TALK_QUEUE_BUFFER: 1463 return video1394_queue_buf32(f, cmd, arg); 1464 case VIDEO1394_IOC32_TALK_WAIT_BUFFER: 1465 return video1394_w_wait32(f, cmd, arg); 1466 case VIDEO1394_IOC32_LISTEN_POLL_BUFFER: 1467 return video1394_wr_wait32(f, cmd, arg); 1468 default: 1469 return -ENOIOCTLCMD; 1470 } 1471} 1472 1473#endif /* CONFIG_COMPAT */ 1474 1475static void __exit video1394_exit_module (void) 1476{ 1477 hpsb_unregister_protocol(&video1394_driver); 1478 hpsb_unregister_highlevel(&video1394_highlevel); 1479 cdev_del(&video1394_cdev); 1480 PRINT_G(KERN_INFO, "Removed " VIDEO1394_DRIVER_NAME " module"); 1481} 1482 1483static int __init video1394_init_module (void) 1484{ 1485 int ret; 1486 1487 cdev_init(&video1394_cdev, &video1394_fops); 1488 video1394_cdev.owner = THIS_MODULE; 1489 kobject_set_name(&video1394_cdev.kobj, VIDEO1394_DRIVER_NAME); 1490 ret = cdev_add(&video1394_cdev, IEEE1394_VIDEO1394_DEV, 16); 1491 if (ret) { 1492 PRINT_G(KERN_ERR, "video1394: unable to get minor device block"); 1493 return ret; 1494 } 1495 1496 hpsb_register_highlevel(&video1394_highlevel); 1497 1498 ret = hpsb_register_protocol(&video1394_driver); 1499 if (ret) { 1500 PRINT_G(KERN_ERR, "video1394: failed to register protocol"); 1501 hpsb_unregister_highlevel(&video1394_highlevel); 1502 cdev_del(&video1394_cdev); 1503 return ret; 1504 } 1505 1506 PRINT_G(KERN_INFO, "Installed " VIDEO1394_DRIVER_NAME " module"); 1507 return 0; 1508} 1509 1510 1511module_init(video1394_init_module); 1512module_exit(video1394_exit_module); 1513