1/* 2 * linux/drivers/ide/pci/siimage.c Version 1.12 Mar 10 2007 3 * 4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> 5 * Copyright (C) 2003 Red Hat <alan@redhat.com> 6 * Copyright (C) 2007 MontaVista Software, Inc. 7 * 8 * May be copied or modified under the terms of the GNU General Public License 9 * 10 * Documentation for CMD680: 11 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 12 * 13 * Documentation for SiI 3112: 14 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 15 * 16 * Errata and other documentation only available under NDA. 17 * 18 * 19 * FAQ Items: 20 * If you are using Marvell SATA-IDE adapters with Maxtor drives 21 * ensure the system is set up for ATA100/UDMA5 not UDMA6. 22 * 23 * If you are using WD drives with SATA bridges you must set the 24 * drive to "Single". "Master" will hang 25 * 26 * If you have strange problems with nVidia chipset systems please 27 * see the SI support documentation and update your system BIOS 28 * if neccessary 29 * 30 * The Dell DRAC4 has some interesting features including effectively hot 31 * unplugging/replugging the virtual CD interface when the DRAC is reset. 32 * This often causes drivers/ide/siimage to panic but is ok with the rather 33 * smarter code in libata. 34 */ 35 36#include <linux/types.h> 37#include <linux/module.h> 38#include <linux/pci.h> 39#include <linux/delay.h> 40#include <linux/hdreg.h> 41#include <linux/ide.h> 42#include <linux/init.h> 43 44#include <asm/io.h> 45 46/** 47 * pdev_is_sata - check if device is SATA 48 * @pdev: PCI device to check 49 * 50 * Returns true if this is a SATA controller 51 */ 52 53static int pdev_is_sata(struct pci_dev *pdev) 54{ 55 switch(pdev->device) 56 { 57 case PCI_DEVICE_ID_SII_3112: 58 case PCI_DEVICE_ID_SII_1210SA: 59 return 1; 60 case PCI_DEVICE_ID_SII_680: 61 return 0; 62 } 63 BUG(); 64 return 0; 65} 66 67/** 68 * is_sata - check if hwif is SATA 69 * @hwif: interface to check 70 * 71 * Returns true if this is a SATA controller 72 */ 73 74static inline int is_sata(ide_hwif_t *hwif) 75{ 76 return pdev_is_sata(hwif->pci_dev); 77} 78 79/** 80 * siimage_selreg - return register base 81 * @hwif: interface 82 * @r: config offset 83 * 84 * Turn a config register offset into the right address in either 85 * PCI space or MMIO space to access the control register in question 86 * Thankfully this is a configuration operation so isnt performance 87 * criticial. 88 */ 89 90static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) 91{ 92 unsigned long base = (unsigned long)hwif->hwif_data; 93 base += 0xA0 + r; 94 if(hwif->mmio) 95 base += (hwif->channel << 6); 96 else 97 base += (hwif->channel << 4); 98 return base; 99} 100 101/** 102 * siimage_seldev - return register base 103 * @hwif: interface 104 * @r: config offset 105 * 106 * Turn a config register offset into the right address in either 107 * PCI space or MMIO space to access the control register in question 108 * including accounting for the unit shift. 109 */ 110 111static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) 112{ 113 ide_hwif_t *hwif = HWIF(drive); 114 unsigned long base = (unsigned long)hwif->hwif_data; 115 base += 0xA0 + r; 116 if(hwif->mmio) 117 base += (hwif->channel << 6); 118 else 119 base += (hwif->channel << 4); 120 base |= drive->select.b.unit << drive->select.b.unit; 121 return base; 122} 123 124/** 125 * sil_udma_filter - compute UDMA mask 126 * @drive: IDE device 127 * 128 * Compute the available UDMA speeds for the device on the interface. 129 * 130 * For the CMD680 this depends on the clocking mode (scsc), for the 131 * SI3112 SATA controller life is a bit simpler. 132 */ 133 134static u8 sil_udma_filter(ide_drive_t *drive) 135{ 136 ide_hwif_t *hwif = drive->hwif; 137 unsigned long base = (unsigned long) hwif->hwif_data; 138 u8 mask = 0, scsc = 0; 139 140 if (hwif->mmio) 141 scsc = hwif->INB(base + 0x4A); 142 else 143 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc); 144 145 if (is_sata(hwif)) { 146 mask = strstr(drive->id->model, "Maxtor") ? 0x3f : 0x7f; 147 goto out; 148 } 149 150 if ((scsc & 0x30) == 0x10) /* 133 */ 151 mask = 0x7f; 152 else if ((scsc & 0x30) == 0x20) /* 2xPCI */ 153 mask = 0x7f; 154 else if ((scsc & 0x30) == 0x00) /* 100 */ 155 mask = 0x3f; 156 else /* Disabled ? */ 157 BUG(); 158out: 159 return mask; 160} 161 162/** 163 * siimage_taskfile_timing - turn timing data to a mode 164 * @hwif: interface to query 165 * 166 * Read the timing data for the interface and return the 167 * mode that is being used. 168 */ 169 170static byte siimage_taskfile_timing (ide_hwif_t *hwif) 171{ 172 u16 timing = 0x328a; 173 unsigned long addr = siimage_selreg(hwif, 2); 174 175 if (hwif->mmio) 176 timing = hwif->INW(addr); 177 else 178 pci_read_config_word(hwif->pci_dev, addr, &timing); 179 180 switch (timing) { 181 case 0x10c1: return 4; 182 case 0x10c3: return 3; 183 case 0x1104: 184 case 0x1281: return 2; 185 case 0x2283: return 1; 186 case 0x328a: 187 default: return 0; 188 } 189} 190 191/** 192 * simmage_tuneproc - tune a drive 193 * @drive: drive to tune 194 * @mode_wanted: the target operating mode 195 * 196 * Load the timing settings for this device mode into the 197 * controller. If we are in PIO mode 3 or 4 turn on IORDY 198 * monitoring (bit 9). The TF timing is bits 31:16 199 */ 200 201static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted) 202{ 203 ide_hwif_t *hwif = HWIF(drive); 204 u32 speedt = 0; 205 u16 speedp = 0; 206 unsigned long addr = siimage_seldev(drive, 0x04); 207 unsigned long tfaddr = siimage_selreg(hwif, 0x02); 208 209 /* cheat for now and use the docs */ 210 switch (mode_wanted) { 211 case 4: 212 speedp = 0x10c1; 213 speedt = 0x10c1; 214 break; 215 case 3: 216 speedp = 0x10c3; 217 speedt = 0x10c3; 218 break; 219 case 2: 220 speedp = 0x1104; 221 speedt = 0x1281; 222 break; 223 case 1: 224 speedp = 0x2283; 225 speedt = 0x2283; 226 break; 227 case 0: 228 default: 229 speedp = 0x328a; 230 speedt = 0x328a; 231 break; 232 } 233 234 if (hwif->mmio) { 235 hwif->OUTW(speedp, addr); 236 hwif->OUTW(speedt, tfaddr); 237 /* Now set up IORDY */ 238 if(mode_wanted == 3 || mode_wanted == 4) 239 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2); 240 else 241 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2); 242 } else { 243 pci_write_config_word(hwif->pci_dev, addr, speedp); 244 pci_write_config_word(hwif->pci_dev, tfaddr, speedt); 245 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp); 246 speedp &= ~0x200; 247 /* Set IORDY for mode 3 or 4 */ 248 if(mode_wanted == 3 || mode_wanted == 4) 249 speedp |= 0x200; 250 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp); 251 } 252} 253 254 255static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed) 256{ 257 u8 channel_timings = siimage_taskfile_timing(HWIF(drive)); 258 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL); 259 260 /* WARNING PIO timing mess is going to happen b/w devices, argh */ 261 if ((channel_timings != set_pio) && (set_pio > channel_timings)) 262 set_pio = channel_timings; 263 264 siimage_tuneproc(drive, set_pio); 265 speed = XFER_PIO_0 + set_pio; 266 if (set_speed) 267 (void) ide_config_drive_speed(drive, speed); 268} 269 270/** 271 * siimage_tune_chipset - set controller timings 272 * @drive: Drive to set up 273 * @xferspeed: speed we want to achieve 274 * 275 * Tune the SII chipset for the desired mode. If we can't achieve 276 * the desired mode then tune for a lower one, but ultimately 277 * make the thing work. 278 */ 279 280static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed) 281{ 282 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; 283 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; 284 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; 285 286 ide_hwif_t *hwif = HWIF(drive); 287 u16 ultra = 0, multi = 0; 288 u8 mode = 0, unit = drive->select.b.unit; 289 u8 speed = ide_rate_filter(drive, xferspeed); 290 unsigned long base = (unsigned long)hwif->hwif_data; 291 u8 scsc = 0, addr_mask = ((hwif->channel) ? 292 ((hwif->mmio) ? 0xF4 : 0x84) : 293 ((hwif->mmio) ? 0xB4 : 0x80)); 294 295 unsigned long ma = siimage_seldev(drive, 0x08); 296 unsigned long ua = siimage_seldev(drive, 0x0C); 297 298 if (hwif->mmio) { 299 scsc = hwif->INB(base + 0x4A); 300 mode = hwif->INB(base + addr_mask); 301 multi = hwif->INW(ma); 302 ultra = hwif->INW(ua); 303 } else { 304 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc); 305 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode); 306 pci_read_config_word(hwif->pci_dev, ma, &multi); 307 pci_read_config_word(hwif->pci_dev, ua, &ultra); 308 } 309 310 mode &= ~((unit) ? 0x30 : 0x03); 311 ultra &= ~0x3F; 312 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; 313 314 scsc = is_sata(hwif) ? 1 : scsc; 315 316 switch(speed) { 317 case XFER_PIO_4: 318 case XFER_PIO_3: 319 case XFER_PIO_2: 320 case XFER_PIO_1: 321 case XFER_PIO_0: 322 siimage_tuneproc(drive, (speed - XFER_PIO_0)); 323 mode |= ((unit) ? 0x10 : 0x01); 324 break; 325 case XFER_MW_DMA_2: 326 case XFER_MW_DMA_1: 327 case XFER_MW_DMA_0: 328 multi = dma[speed - XFER_MW_DMA_0]; 329 mode |= ((unit) ? 0x20 : 0x02); 330 config_siimage_chipset_for_pio(drive, 0); 331 break; 332 case XFER_UDMA_6: 333 case XFER_UDMA_5: 334 case XFER_UDMA_4: 335 case XFER_UDMA_3: 336 case XFER_UDMA_2: 337 case XFER_UDMA_1: 338 case XFER_UDMA_0: 339 multi = dma[2]; 340 ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) : 341 (ultra5[speed - XFER_UDMA_0])); 342 mode |= ((unit) ? 0x30 : 0x03); 343 config_siimage_chipset_for_pio(drive, 0); 344 break; 345 default: 346 return 1; 347 } 348 349 if (hwif->mmio) { 350 hwif->OUTB(mode, base + addr_mask); 351 hwif->OUTW(multi, ma); 352 hwif->OUTW(ultra, ua); 353 } else { 354 pci_write_config_byte(hwif->pci_dev, addr_mask, mode); 355 pci_write_config_word(hwif->pci_dev, ma, multi); 356 pci_write_config_word(hwif->pci_dev, ua, ultra); 357 } 358 return (ide_config_drive_speed(drive, speed)); 359} 360 361/** 362 * siimage_configure_drive_for_dma - set up for DMA transfers 363 * @drive: drive we are going to set up 364 * 365 * Set up the drive for DMA, tune the controller and drive as 366 * required. If the drive isn't suitable for DMA or we hit 367 * other problems then we will drop down to PIO and set up 368 * PIO appropriately 369 */ 370 371static int siimage_config_drive_for_dma (ide_drive_t *drive) 372{ 373 if (ide_tune_dma(drive)) 374 return 0; 375 376 if (ide_use_fast_pio(drive)) 377 config_siimage_chipset_for_pio(drive, 1); 378 379 return -1; 380} 381 382/* returns 1 if dma irq issued, 0 otherwise */ 383static int siimage_io_ide_dma_test_irq (ide_drive_t *drive) 384{ 385 ide_hwif_t *hwif = HWIF(drive); 386 u8 dma_altstat = 0; 387 unsigned long addr = siimage_selreg(hwif, 1); 388 389 /* return 1 if INTR asserted */ 390 if ((hwif->INB(hwif->dma_status) & 4) == 4) 391 return 1; 392 393 /* return 1 if Device INTR asserted */ 394 pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat); 395 if (dma_altstat & 8) 396 return 0; //return 1; 397 return 0; 398} 399 400/** 401 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ 402 * @drive: drive we are testing 403 * 404 * Check if we caused an IDE DMA interrupt. We may also have caused 405 * SATA status interrupts, if so we clean them up and continue. 406 */ 407 408static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive) 409{ 410 ide_hwif_t *hwif = HWIF(drive); 411 unsigned long base = (unsigned long)hwif->hwif_data; 412 unsigned long addr = siimage_selreg(hwif, 0x1); 413 414 if (SATA_ERROR_REG) { 415 u32 ext_stat = readl((void __iomem *)(base + 0x10)); 416 u8 watchdog = 0; 417 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { 418 u32 sata_error = readl((void __iomem *)SATA_ERROR_REG); 419 writel(sata_error, (void __iomem *)SATA_ERROR_REG); 420 watchdog = (sata_error & 0x00680000) ? 1 : 0; 421 printk(KERN_WARNING "%s: sata_error = 0x%08x, " 422 "watchdog = %d, %s\n", 423 drive->name, sata_error, watchdog, 424 __FUNCTION__); 425 426 } else { 427 watchdog = (ext_stat & 0x8000) ? 1 : 0; 428 } 429 ext_stat >>= 16; 430 431 if (!(ext_stat & 0x0404) && !watchdog) 432 return 0; 433 } 434 435 /* return 1 if INTR asserted */ 436 if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04) 437 return 1; 438 439 /* return 1 if Device INTR asserted */ 440 if ((readb((void __iomem *)addr) & 8) == 8) 441 return 0; //return 1; 442 443 return 0; 444} 445 446/** 447 * siimage_busproc - bus isolation ioctl 448 * @drive: drive to isolate/restore 449 * @state: bus state to set 450 * 451 * Used by the SII3112 to handle bus isolation. As this is a 452 * SATA controller the work required is quite limited, we 453 * just have to clean up the statistics 454 */ 455 456static int siimage_busproc (ide_drive_t * drive, int state) 457{ 458 ide_hwif_t *hwif = HWIF(drive); 459 u32 stat_config = 0; 460 unsigned long addr = siimage_selreg(hwif, 0); 461 462 if (hwif->mmio) 463 stat_config = readl((void __iomem *)addr); 464 else 465 pci_read_config_dword(hwif->pci_dev, addr, &stat_config); 466 467 switch (state) { 468 case BUSSTATE_ON: 469 hwif->drives[0].failures = 0; 470 hwif->drives[1].failures = 0; 471 break; 472 case BUSSTATE_OFF: 473 hwif->drives[0].failures = hwif->drives[0].max_failures + 1; 474 hwif->drives[1].failures = hwif->drives[1].max_failures + 1; 475 break; 476 case BUSSTATE_TRISTATE: 477 hwif->drives[0].failures = hwif->drives[0].max_failures + 1; 478 hwif->drives[1].failures = hwif->drives[1].max_failures + 1; 479 break; 480 default: 481 return -EINVAL; 482 } 483 hwif->bus_state = state; 484 return 0; 485} 486 487/** 488 * siimage_reset_poll - wait for sata reset 489 * @drive: drive we are resetting 490 * 491 * Poll the SATA phy and see whether it has come back from the dead 492 * yet. 493 */ 494 495static int siimage_reset_poll (ide_drive_t *drive) 496{ 497 if (SATA_STATUS_REG) { 498 ide_hwif_t *hwif = HWIF(drive); 499 500 /* SATA_STATUS_REG is valid only when in MMIO mode */ 501 if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) { 502 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", 503 hwif->name, readl((void __iomem *)SATA_STATUS_REG)); 504 HWGROUP(drive)->polling = 0; 505 return ide_started; 506 } 507 return 0; 508 } else { 509 return 0; 510 } 511} 512 513/** 514 * siimage_pre_reset - reset hook 515 * @drive: IDE device being reset 516 * 517 * For the SATA devices we need to handle recalibration/geometry 518 * differently 519 */ 520 521static void siimage_pre_reset (ide_drive_t *drive) 522{ 523 if (drive->media != ide_disk) 524 return; 525 526 if (is_sata(HWIF(drive))) 527 { 528 drive->special.b.set_geometry = 0; 529 drive->special.b.recalibrate = 0; 530 } 531} 532 533/** 534 * siimage_reset - reset a device on an siimage controller 535 * @drive: drive to reset 536 * 537 * Perform a controller level reset fo the device. For 538 * SATA we must also check the PHY. 539 */ 540 541static void siimage_reset (ide_drive_t *drive) 542{ 543 ide_hwif_t *hwif = HWIF(drive); 544 u8 reset = 0; 545 unsigned long addr = siimage_selreg(hwif, 0); 546 547 if (hwif->mmio) { 548 reset = hwif->INB(addr); 549 hwif->OUTB((reset|0x03), addr); 550 udelay(25); 551 hwif->OUTB(reset, addr); 552 (void) hwif->INB(addr); 553 } else { 554 pci_read_config_byte(hwif->pci_dev, addr, &reset); 555 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03); 556 udelay(25); 557 pci_write_config_byte(hwif->pci_dev, addr, reset); 558 pci_read_config_byte(hwif->pci_dev, addr, &reset); 559 } 560 561 if (SATA_STATUS_REG) { 562 /* SATA_STATUS_REG is valid only when in MMIO mode */ 563 u32 sata_stat = readl((void __iomem *)SATA_STATUS_REG); 564 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n", 565 hwif->name, sata_stat, __FUNCTION__); 566 if (!(sata_stat)) { 567 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", 568 hwif->name, sata_stat); 569 drive->failures++; 570 } 571 } 572 573} 574 575/** 576 * proc_reports_siimage - add siimage controller to proc 577 * @dev: PCI device 578 * @clocking: SCSC value 579 * @name: controller name 580 * 581 * Report the clocking mode of the controller and add it to 582 * the /proc interface layer 583 */ 584 585static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name) 586{ 587 if (!pdev_is_sata(dev)) { 588 printk(KERN_INFO "%s: BASE CLOCK ", name); 589 clocking &= 0x03; 590 switch (clocking) { 591 case 0x03: printk("DISABLED!\n"); break; 592 case 0x02: printk("== 2X PCI\n"); break; 593 case 0x01: printk("== 133\n"); break; 594 case 0x00: printk("== 100\n"); break; 595 } 596 } 597} 598 599/** 600 * setup_mmio_siimage - switch an SI controller into MMIO 601 * @dev: PCI device we are configuring 602 * @name: device name 603 * 604 * Attempt to put the device into mmio mode. There are some slight 605 * complications here with certain systems where the mmio bar isnt 606 * mapped so we have to be sure we can fall back to I/O. 607 */ 608 609static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name) 610{ 611 unsigned long bar5 = pci_resource_start(dev, 5); 612 unsigned long barsize = pci_resource_len(dev, 5); 613 u8 tmpbyte = 0; 614 void __iomem *ioaddr; 615 u32 tmp, irq_mask; 616 617 /* 618 * Drop back to PIO if we can't map the mmio. Some 619 * systems seem to get terminally confused in the PCI 620 * spaces. 621 */ 622 623 if(!request_mem_region(bar5, barsize, name)) 624 { 625 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n"); 626 return 0; 627 } 628 629 ioaddr = ioremap(bar5, barsize); 630 631 if (ioaddr == NULL) 632 { 633 release_mem_region(bar5, barsize); 634 return 0; 635 } 636 637 pci_set_master(dev); 638 pci_set_drvdata(dev, (void *) ioaddr); 639 640 if (pdev_is_sata(dev)) { 641 /* make sure IDE0/1 interrupts are not masked */ 642 irq_mask = (1 << 22) | (1 << 23); 643 tmp = readl(ioaddr + 0x48); 644 if (tmp & irq_mask) { 645 tmp &= ~irq_mask; 646 writel(tmp, ioaddr + 0x48); 647 readl(ioaddr + 0x48); /* flush */ 648 } 649 writel(0, ioaddr + 0x148); 650 writel(0, ioaddr + 0x1C8); 651 } 652 653 writeb(0, ioaddr + 0xB4); 654 writeb(0, ioaddr + 0xF4); 655 tmpbyte = readb(ioaddr + 0x4A); 656 657 switch(tmpbyte & 0x30) { 658 case 0x00: 659 /* In 100 MHz clocking, try and switch to 133 */ 660 writeb(tmpbyte|0x10, ioaddr + 0x4A); 661 break; 662 case 0x10: 663 /* On 133Mhz clocking */ 664 break; 665 case 0x20: 666 /* On PCIx2 clocking */ 667 break; 668 case 0x30: 669 /* Clocking is disabled */ 670 /* 133 clock attempt to force it on */ 671 writeb(tmpbyte & ~0x20, ioaddr + 0x4A); 672 break; 673 } 674 675 writeb( 0x72, ioaddr + 0xA1); 676 writew( 0x328A, ioaddr + 0xA2); 677 writel(0x62DD62DD, ioaddr + 0xA4); 678 writel(0x43924392, ioaddr + 0xA8); 679 writel(0x40094009, ioaddr + 0xAC); 680 writeb( 0x72, ioaddr + 0xE1); 681 writew( 0x328A, ioaddr + 0xE2); 682 writel(0x62DD62DD, ioaddr + 0xE4); 683 writel(0x43924392, ioaddr + 0xE8); 684 writel(0x40094009, ioaddr + 0xEC); 685 686 if (pdev_is_sata(dev)) { 687 writel(0xFFFF0000, ioaddr + 0x108); 688 writel(0xFFFF0000, ioaddr + 0x188); 689 writel(0x00680000, ioaddr + 0x148); 690 writel(0x00680000, ioaddr + 0x1C8); 691 } 692 693 tmpbyte = readb(ioaddr + 0x4A); 694 695 proc_reports_siimage(dev, (tmpbyte>>4), name); 696 return 1; 697} 698 699/** 700 * init_chipset_siimage - set up an SI device 701 * @dev: PCI device 702 * @name: device name 703 * 704 * Perform the initial PCI set up for this device. Attempt to switch 705 * to 133MHz clocking if the system isn't already set up to do it. 706 */ 707 708static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name) 709{ 710 u32 class_rev = 0; 711 u8 tmpbyte = 0; 712 u8 BA5_EN = 0; 713 714 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 715 class_rev &= 0xff; 716 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255); 717 718 pci_read_config_byte(dev, 0x8A, &BA5_EN); 719 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) { 720 if (setup_mmio_siimage(dev, name)) { 721 return 0; 722 } 723 } 724 725 pci_write_config_byte(dev, 0x80, 0x00); 726 pci_write_config_byte(dev, 0x84, 0x00); 727 pci_read_config_byte(dev, 0x8A, &tmpbyte); 728 switch(tmpbyte & 0x30) { 729 case 0x00: 730 /* 133 clock attempt to force it on */ 731 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10); 732 case 0x30: 733 /* if clocking is disabled */ 734 /* 133 clock attempt to force it on */ 735 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20); 736 case 0x10: 737 /* 133 already */ 738 break; 739 case 0x20: 740 /* BIOS set PCI x2 clocking */ 741 break; 742 } 743 744 pci_read_config_byte(dev, 0x8A, &tmpbyte); 745 746 pci_write_config_byte(dev, 0xA1, 0x72); 747 pci_write_config_word(dev, 0xA2, 0x328A); 748 pci_write_config_dword(dev, 0xA4, 0x62DD62DD); 749 pci_write_config_dword(dev, 0xA8, 0x43924392); 750 pci_write_config_dword(dev, 0xAC, 0x40094009); 751 pci_write_config_byte(dev, 0xB1, 0x72); 752 pci_write_config_word(dev, 0xB2, 0x328A); 753 pci_write_config_dword(dev, 0xB4, 0x62DD62DD); 754 pci_write_config_dword(dev, 0xB8, 0x43924392); 755 pci_write_config_dword(dev, 0xBC, 0x40094009); 756 757 proc_reports_siimage(dev, (tmpbyte>>4), name); 758 return 0; 759} 760 761/** 762 * init_mmio_iops_siimage - set up the iops for MMIO 763 * @hwif: interface to set up 764 * 765 * The basic setup here is fairly simple, we can use standard MMIO 766 * operations. However we do have to set the taskfile register offsets 767 * by hand as there isnt a standard defined layout for them this 768 * time. 769 * 770 * The hardware supports buffered taskfiles and also some rather nice 771 * extended PRD tables. For better SI3112 support use the libata driver 772 */ 773 774static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) 775{ 776 struct pci_dev *dev = hwif->pci_dev; 777 void *addr = pci_get_drvdata(dev); 778 u8 ch = hwif->channel; 779 hw_regs_t hw; 780 unsigned long base; 781 782 /* 783 * Fill in the basic HWIF bits 784 */ 785 786 default_hwif_mmiops(hwif); 787 hwif->hwif_data = addr; 788 789 /* 790 * Now set up the hw. We have to do this ourselves as 791 * the MMIO layout isnt the same as the standard port 792 * based I/O 793 */ 794 795 memset(&hw, 0, sizeof(hw_regs_t)); 796 797 base = (unsigned long)addr; 798 if (ch) 799 base += 0xC0; 800 else 801 base += 0x80; 802 803 /* 804 * The buffered task file doesn't have status/control 805 * so we can't currently use it sanely since we want to 806 * use LBA48 mode. 807 */ 808 hw.io_ports[IDE_DATA_OFFSET] = base; 809 hw.io_ports[IDE_ERROR_OFFSET] = base + 1; 810 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2; 811 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3; 812 hw.io_ports[IDE_LCYL_OFFSET] = base + 4; 813 hw.io_ports[IDE_HCYL_OFFSET] = base + 5; 814 hw.io_ports[IDE_SELECT_OFFSET] = base + 6; 815 hw.io_ports[IDE_STATUS_OFFSET] = base + 7; 816 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10; 817 818 hw.io_ports[IDE_IRQ_OFFSET] = 0; 819 820 if (pdev_is_sata(dev)) { 821 base = (unsigned long)addr; 822 if (ch) 823 base += 0x80; 824 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; 825 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; 826 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; 827 hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140; 828 hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144; 829 hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148; 830 } 831 832 hw.irq = hwif->pci_dev->irq; 833 834 memcpy(&hwif->hw, &hw, sizeof(hw)); 835 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports)); 836 837 hwif->irq = hw.irq; 838 839 base = (unsigned long) addr; 840 841 hwif->dma_base = base + (ch ? 0x08 : 0x00); 842 843 hwif->mmio = 1; 844} 845 846static int is_dev_seagate_sata(ide_drive_t *drive) 847{ 848 const char *s = &drive->id->model[0]; 849 unsigned len; 850 851 if (!drive->present) 852 return 0; 853 854 len = strnlen(s, sizeof(drive->id->model)); 855 856 if ((len > 4) && (!memcmp(s, "ST", 2))) { 857 if ((!memcmp(s + len - 2, "AS", 2)) || 858 (!memcmp(s + len - 3, "ASL", 3))) { 859 printk(KERN_INFO "%s: applying pessimistic Seagate " 860 "errata fix\n", drive->name); 861 return 1; 862 } 863 } 864 return 0; 865} 866 867/** 868 * siimage_fixup - post probe fixups 869 * @hwif: interface to fix up 870 * 871 * Called after drive probe we use this to decide whether the 872 * Seagate fixup must be applied. This used to be in init_iops but 873 * that can occur before we know what drives are present. 874 */ 875 876static void __devinit siimage_fixup(ide_hwif_t *hwif) 877{ 878 /* Try and raise the rqsize */ 879 if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0])) 880 hwif->rqsize = 128; 881} 882 883/** 884 * init_iops_siimage - set up iops 885 * @hwif: interface to set up 886 * 887 * Do the basic setup for the SIIMAGE hardware interface 888 * and then do the MMIO setup if we can. This is the first 889 * look in we get for setting up the hwif so that we 890 * can get the iops right before using them. 891 */ 892 893static void __devinit init_iops_siimage(ide_hwif_t *hwif) 894{ 895 struct pci_dev *dev = hwif->pci_dev; 896 u32 class_rev = 0; 897 898 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 899 class_rev &= 0xff; 900 901 hwif->hwif_data = NULL; 902 903 /* Pessimal until we finish probing */ 904 hwif->rqsize = 15; 905 906 if (pci_get_drvdata(dev) == NULL) 907 return; 908 init_mmio_iops_siimage(hwif); 909} 910 911/** 912 * ata66_siimage - check for 80 pin cable 913 * @hwif: interface to check 914 * 915 * Check for the presence of an ATA66 capable cable on the 916 * interface. 917 */ 918 919static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif) 920{ 921 unsigned long addr = siimage_selreg(hwif, 0); 922 if (pci_get_drvdata(hwif->pci_dev) == NULL) { 923 u8 ata66 = 0; 924 pci_read_config_byte(hwif->pci_dev, addr, &ata66); 925 return (ata66 & 0x01) ? 1 : 0; 926 } 927 928 return (hwif->INB(addr) & 0x01) ? 1 : 0; 929} 930 931/** 932 * init_hwif_siimage - set up hwif structs 933 * @hwif: interface to set up 934 * 935 * We do the basic set up of the interface structure. The SIIMAGE 936 * requires several custom handlers so we override the default 937 * ide DMA handlers appropriately 938 */ 939 940static void __devinit init_hwif_siimage(ide_hwif_t *hwif) 941{ 942 hwif->autodma = 0; 943 944 hwif->resetproc = &siimage_reset; 945 hwif->speedproc = &siimage_tune_chipset; 946 hwif->tuneproc = &siimage_tuneproc; 947 hwif->reset_poll = &siimage_reset_poll; 948 hwif->pre_reset = &siimage_pre_reset; 949 hwif->udma_filter = &sil_udma_filter; 950 951 if(is_sata(hwif)) { 952 static int first = 1; 953 954 hwif->busproc = &siimage_busproc; 955 956 if (first) { 957 printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n"); 958 first = 0; 959 } 960 } 961 if (!hwif->dma_base) { 962 hwif->drives[0].autotune = 1; 963 hwif->drives[1].autotune = 1; 964 return; 965 } 966 967 hwif->ultra_mask = 0x7f; 968 hwif->mwdma_mask = 0x07; 969 970 if (!is_sata(hwif)) 971 hwif->atapi_dma = 1; 972 973 hwif->ide_dma_check = &siimage_config_drive_for_dma; 974 if (!(hwif->udma_four)) 975 hwif->udma_four = ata66_siimage(hwif); 976 977 if (hwif->mmio) { 978 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq; 979 } else { 980 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq; 981 } 982 983 /* 984 * The BIOS often doesn't set up DMA on this controller 985 * so we always do it. 986 */ 987 988 hwif->autodma = 1; 989 hwif->drives[0].autodma = hwif->autodma; 990 hwif->drives[1].autodma = hwif->autodma; 991} 992 993#define DECLARE_SII_DEV(name_str) \ 994 { \ 995 .name = name_str, \ 996 .init_chipset = init_chipset_siimage, \ 997 .init_iops = init_iops_siimage, \ 998 .init_hwif = init_hwif_siimage, \ 999 .fixup = siimage_fixup, \ 1000 .channels = 2, \ 1001 .autodma = AUTODMA, \ 1002 .bootable = ON_BOARD, \ 1003 } 1004 1005static ide_pci_device_t siimage_chipsets[] __devinitdata = { 1006 /* 0 */ DECLARE_SII_DEV("SiI680"), 1007 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"), 1008 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA") 1009}; 1010 1011/** 1012 * siimage_init_one - pci layer discovery entry 1013 * @dev: PCI device 1014 * @id: ident table entry 1015 * 1016 * Called by the PCI code when it finds an SI680 or SI3112 controller. 1017 * We then use the IDE PCI generic helper to do most of the work. 1018 */ 1019 1020static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id) 1021{ 1022 return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]); 1023} 1024 1025static struct pci_device_id siimage_pci_tbl[] = { 1026 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1027#ifdef CONFIG_BLK_DEV_IDE_SATA 1028 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, 1029 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, 1030#endif 1031 { 0, }, 1032}; 1033MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); 1034 1035static struct pci_driver driver = { 1036 .name = "SiI_IDE", 1037 .id_table = siimage_pci_tbl, 1038 .probe = siimage_init_one, 1039}; 1040 1041static int __init siimage_ide_init(void) 1042{ 1043 return ide_pci_register_driver(&driver); 1044} 1045 1046module_init(siimage_ide_init); 1047 1048MODULE_AUTHOR("Andre Hedrick, Alan Cox"); 1049MODULE_DESCRIPTION("PCI driver module for SiI IDE"); 1050MODULE_LICENSE("GPL"); 1051