1/*
2 *  linux/drivers/ide/legacy/q40ide.c -- Q40 I/O port IDE Driver
3 *
4 *     (c) Richard Zidlicky
5 *
6 *  This file is subject to the terms and conditions of the GNU General Public
7 *  License.  See the file COPYING in the main directory of this archive for
8 *  more details.
9 *
10 *
11 */
12
13#include <linux/types.h>
14#include <linux/mm.h>
15#include <linux/interrupt.h>
16#include <linux/blkdev.h>
17#include <linux/hdreg.h>
18
19#include <linux/ide.h>
20
21    /*
22     *  Bases of the IDE interfaces
23     */
24
25#define Q40IDE_NUM_HWIFS	2
26
27#define PCIDE_BASE1	0x1f0
28#define PCIDE_BASE2	0x170
29#define PCIDE_BASE3	0x1e8
30#define PCIDE_BASE4	0x168
31#define PCIDE_BASE5	0x1e0
32#define PCIDE_BASE6	0x160
33
34static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
35    PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4  , PCIDE_BASE5,
36    PCIDE_BASE6 */
37};
38
39
40    /*
41     *  Offsets from one of the above bases
42     */
43
44/* used to do addr translation here but it is easier to do in setup ports */
45/*#define IDE_OFF_B(x)	((unsigned long)Q40_ISA_IO_B((IDE_##x##_OFFSET)))*/
46
47#define IDE_OFF_B(x)	((unsigned long)((IDE_##x##_OFFSET)))
48#define IDE_OFF_W(x)	((unsigned long)((IDE_##x##_OFFSET)))
49
50static const int pcide_offsets[IDE_NR_PORTS] = {
51    IDE_OFF_W(DATA), IDE_OFF_B(ERROR), IDE_OFF_B(NSECTOR), IDE_OFF_B(SECTOR),
52    IDE_OFF_B(LCYL), IDE_OFF_B(HCYL), 6 /*IDE_OFF_B(CURRENT)*/, IDE_OFF_B(STATUS),
53    518/*IDE_OFF(CMD)*/
54};
55
56static int q40ide_default_irq(unsigned long base)
57{
58           switch (base) {
59	            case 0x1f0: return 14;
60		    case 0x170: return 15;
61		    case 0x1e8: return 11;
62		    default:
63			return 0;
64	   }
65}
66
67
68/*
69 * This is very similar to ide_setup_ports except that addresses
70 * are pretranslated for q40 ISA access
71 */
72void q40_ide_setup_ports ( hw_regs_t *hw,
73			unsigned long base, int *offsets,
74			unsigned long ctrl, unsigned long intr,
75			ide_ack_intr_t *ack_intr,
76/*
77 *			ide_io_ops_t *iops,
78 */
79			int irq)
80{
81	int i;
82
83	memset(hw, 0, sizeof(hw_regs_t));
84	for (i = 0; i < IDE_NR_PORTS; i++) {
85		/* BIG FAT WARNING:
86		   assumption: only DATA port is ever used in 16 bit mode */
87		if ( i==0 )
88			hw->io_ports[i] = Q40_ISA_IO_W(base + offsets[i]);
89		else
90			hw->io_ports[i] = Q40_ISA_IO_B(base + offsets[i]);
91	}
92
93	hw->irq = irq;
94	hw->dma = NO_DMA;
95	hw->ack_intr = ack_intr;
96/*
97 *	hw->iops = iops;
98 */
99}
100
101
102
103/*
104 * the static array is needed to have the name reported in /proc/ioports,
105 * hwif->name unfortunately isn�t available yet
106 */
107static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
108	"ide0", "ide1"
109};
110
111/*
112 *  Probe for Q40 IDE interfaces
113 */
114
115void q40ide_init(void)
116{
117    int i;
118    ide_hwif_t *hwif;
119    int index;
120    const char *name;
121
122    if (!MACH_IS_Q40)
123      return ;
124
125    for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
126	hw_regs_t hw;
127
128	name = q40_ide_names[i];
129	if (!request_region(pcide_bases[i], 8, name)) {
130		printk("could not reserve ports %lx-%lx for %s\n",
131		       pcide_bases[i],pcide_bases[i]+8,name);
132		continue;
133	}
134	if (!request_region(pcide_bases[i]+0x206, 1, name)) {
135		printk("could not reserve port %lx for %s\n",
136		       pcide_bases[i]+0x206,name);
137		release_region(pcide_bases[i], 8);
138		continue;
139	}
140	q40_ide_setup_ports(&hw,(unsigned long) pcide_bases[i], (int *)pcide_offsets,
141			pcide_bases[i]+0x206,
142			0, NULL,
143//			m68kide_iops,
144			q40ide_default_irq(pcide_bases[i]));
145	index = ide_register_hw(&hw, 1, &hwif);
146	if (index != -1)
147		hwif->mmio = 1;
148    }
149}
150