1/* 2 * Intel e752x Memory Controller kernel module 3 * (C) 2004 Linux Networx (http://lnxi.com) 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * See "enum e752x_chips" below for supported chipsets 8 * 9 * Written by Tom Zimmerman 10 * 11 * Contributors: 12 * Thayne Harbaugh at realmsys.com (?) 13 * Wang Zhenyu at intel.com 14 * Dave Jiang at mvista.com 15 * 16 * $Id: e752x_edac.c,v 1.1.1.1 2007/08/03 18:52:30 Exp $ 17 * 18 */ 19 20#include <linux/module.h> 21#include <linux/init.h> 22#include <linux/pci.h> 23#include <linux/pci_ids.h> 24#include <linux/slab.h> 25#include "edac_mc.h" 26 27#define E752X_REVISION " Ver: 2.0.1 " __DATE__ 28#define EDAC_MOD_STR "e752x_edac" 29 30static int force_function_unhide; 31 32#define e752x_printk(level, fmt, arg...) \ 33 edac_printk(level, "e752x", fmt, ##arg) 34 35#define e752x_mc_printk(mci, level, fmt, arg...) \ 36 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg) 37 38#ifndef PCI_DEVICE_ID_INTEL_7520_0 39#define PCI_DEVICE_ID_INTEL_7520_0 0x3590 40#endif /* PCI_DEVICE_ID_INTEL_7520_0 */ 41 42#ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR 43#define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591 44#endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */ 45 46#ifndef PCI_DEVICE_ID_INTEL_7525_0 47#define PCI_DEVICE_ID_INTEL_7525_0 0x359E 48#endif /* PCI_DEVICE_ID_INTEL_7525_0 */ 49 50#ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR 51#define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593 52#endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */ 53 54#ifndef PCI_DEVICE_ID_INTEL_7320_0 55#define PCI_DEVICE_ID_INTEL_7320_0 0x3592 56#endif /* PCI_DEVICE_ID_INTEL_7320_0 */ 57 58#ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR 59#define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593 60#endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */ 61 62#define E752X_NR_CSROWS 8 /* number of csrows */ 63 64/* E752X register addresses - device 0 function 0 */ 65#define E752X_DRB 0x60 /* DRAM row boundary register (8b) */ 66#define E752X_DRA 0x70 /* DRAM row attribute register (8b) */ 67 /* 68 * 31:30 Device width row 7 69 * 01=x8 10=x4 11=x8 DDR2 70 * 27:26 Device width row 6 71 * 23:22 Device width row 5 72 * 19:20 Device width row 4 73 * 15:14 Device width row 3 74 * 11:10 Device width row 2 75 * 7:6 Device width row 1 76 * 3:2 Device width row 0 77 */ 78#define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */ 79 /* 80 * 22 Number channels 0=1,1=2 81 * 19:18 DRB Granularity 32/64MB 82 */ 83#define E752X_DRM 0x80 /* Dimm mapping register */ 84#define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */ 85 /* 86 * 14:12 1 single A, 2 single B, 3 dual 87 */ 88#define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ 89#define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ 90#define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ 91#define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */ 92 93/* E752X register addresses - device 0 function 1 */ 94#define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */ 95#define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */ 96#define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */ 97#define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */ 98#define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */ 99#define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */ 100#define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */ 101#define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */ 102#define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */ 103#define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */ 104#define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */ 105#define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */ 106#define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */ 107#define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */ 108#define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */ 109#define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */ 110#define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */ 111#define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */ 112#define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */ 113#define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */ 114 /* error address register (32b) */ 115 /* 116 * 31 Reserved 117 * 30:2 CE address (64 byte block 34:6) 118 * 1 Reserved 119 * 0 HiLoCS 120 */ 121#define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */ 122 /* error address register (32b) */ 123 /* 124 * 31 Reserved 125 * 30:2 CE address (64 byte block 34:6) 126 * 1 Reserved 127 * 0 HiLoCS 128 */ 129#define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */ 130 /* error address register (32b) */ 131 /* 132 * 31 Reserved 133 * 30:2 CE address (64 byte block 34:6) 134 * 1 Reserved 135 * 0 HiLoCS 136 */ 137#define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */ 138 /* error address register (32b) */ 139 /* 140 * 31 Reserved 141 * 30:2 CE address (64 byte block 34:6) 142 * 1 Reserved 143 * 0 HiLoCS 144 */ 145#define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */ 146 /* error syndrome register (16b) */ 147#define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */ 148 /* error syndrome register (16b) */ 149#define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */ 150 151/* ICH5R register addresses - device 30 function 0 */ 152#define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */ 153#define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */ 154#define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */ 155 156enum e752x_chips { 157 E7520 = 0, 158 E7525 = 1, 159 E7320 = 2 160}; 161 162struct e752x_pvt { 163 struct pci_dev *bridge_ck; 164 struct pci_dev *dev_d0f0; 165 struct pci_dev *dev_d0f1; 166 u32 tolm; 167 u32 remapbase; 168 u32 remaplimit; 169 int mc_symmetric; 170 u8 map[8]; 171 int map_type; 172 const struct e752x_dev_info *dev_info; 173}; 174 175struct e752x_dev_info { 176 u16 err_dev; 177 u16 ctl_dev; 178 const char *ctl_name; 179}; 180 181struct e752x_error_info { 182 u32 ferr_global; 183 u32 nerr_global; 184 u8 hi_ferr; 185 u8 hi_nerr; 186 u16 sysbus_ferr; 187 u16 sysbus_nerr; 188 u8 buf_ferr; 189 u8 buf_nerr; 190 u16 dram_ferr; 191 u16 dram_nerr; 192 u32 dram_sec1_add; 193 u32 dram_sec2_add; 194 u16 dram_sec1_syndrome; 195 u16 dram_sec2_syndrome; 196 u32 dram_ded_add; 197 u32 dram_scrb_add; 198 u32 dram_retr_add; 199}; 200 201static const struct e752x_dev_info e752x_devs[] = { 202 [E7520] = { 203 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR, 204 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0, 205 .ctl_name = "E7520" 206 }, 207 [E7525] = { 208 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR, 209 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0, 210 .ctl_name = "E7525" 211 }, 212 [E7320] = { 213 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR, 214 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0, 215 .ctl_name = "E7320" 216 }, 217}; 218 219static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, 220 unsigned long page) 221{ 222 u32 remap; 223 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; 224 225 debugf3("%s()\n", __func__); 226 227 if (page < pvt->tolm) 228 return page; 229 230 if ((page >= 0x100000) && (page < pvt->remapbase)) 231 return page; 232 233 remap = (page - pvt->tolm) + pvt->remapbase; 234 235 if (remap < pvt->remaplimit) 236 return remap; 237 238 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page); 239 return pvt->tolm - 1; 240} 241 242static void do_process_ce(struct mem_ctl_info *mci, u16 error_one, 243 u32 sec1_add, u16 sec1_syndrome) 244{ 245 u32 page; 246 int row; 247 int channel; 248 int i; 249 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; 250 251 debugf3("%s()\n", __func__); 252 253 /* convert the addr to 4k page */ 254 page = sec1_add >> (PAGE_SHIFT - 4); 255 256 if (pvt->mc_symmetric) { 257 /* chip select are bits 14 & 13 */ 258 row = ((page >> 1) & 3); 259 e752x_printk(KERN_WARNING, 260 "Test row %d Table %d %d %d %d %d %d %d %d\n", row, 261 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3], 262 pvt->map[4], pvt->map[5], pvt->map[6], pvt->map[7]); 263 264 /* test for channel remapping */ 265 for (i = 0; i < 8; i++) { 266 if (pvt->map[i] == row) 267 break; 268 } 269 270 e752x_printk(KERN_WARNING, "Test computed row %d\n", i); 271 272 if (i < 8) 273 row = i; 274 else 275 e752x_mc_printk(mci, KERN_WARNING, 276 "row %d not found in remap table\n", row); 277 } else 278 row = edac_mc_find_csrow_by_page(mci, page); 279 280 /* 0 = channel A, 1 = channel B */ 281 channel = !(error_one & 1); 282 283 if (!pvt->map_type) 284 row = 7 - row; 285 286 /* e752x mc reads 34:6 of the DRAM linear address */ 287 edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4), 288 sec1_syndrome, row, channel, "e752x CE"); 289} 290 291static inline void process_ce(struct mem_ctl_info *mci, u16 error_one, 292 u32 sec1_add, u16 sec1_syndrome, int *error_found, 293 int handle_error) 294{ 295 *error_found = 1; 296 297 if (handle_error) 298 do_process_ce(mci, error_one, sec1_add, sec1_syndrome); 299} 300 301static void do_process_ue(struct mem_ctl_info *mci, u16 error_one, 302 u32 ded_add, u32 scrb_add) 303{ 304 u32 error_2b, block_page; 305 int row; 306 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; 307 308 debugf3("%s()\n", __func__); 309 310 if (error_one & 0x0202) { 311 error_2b = ded_add; 312 313 /* convert to 4k address */ 314 block_page = error_2b >> (PAGE_SHIFT - 4); 315 316 row = pvt->mc_symmetric ? 317 /* chip select are bits 14 & 13 */ 318 ((block_page >> 1) & 3) : 319 edac_mc_find_csrow_by_page(mci, block_page); 320 321 /* e752x mc reads 34:6 of the DRAM linear address */ 322 edac_mc_handle_ue(mci, block_page, 323 offset_in_page(error_2b << 4), 324 row, "e752x UE from Read"); 325 } 326 if (error_one & 0x0404) { 327 error_2b = scrb_add; 328 329 /* convert to 4k address */ 330 block_page = error_2b >> (PAGE_SHIFT - 4); 331 332 row = pvt->mc_symmetric ? 333 /* chip select are bits 14 & 13 */ 334 ((block_page >> 1) & 3) : 335 edac_mc_find_csrow_by_page(mci, block_page); 336 337 /* e752x mc reads 34:6 of the DRAM linear address */ 338 edac_mc_handle_ue(mci, block_page, 339 offset_in_page(error_2b << 4), 340 row, "e752x UE from Scruber"); 341 } 342} 343 344static inline void process_ue(struct mem_ctl_info *mci, u16 error_one, 345 u32 ded_add, u32 scrb_add, int *error_found, int handle_error) 346{ 347 *error_found = 1; 348 349 if (handle_error) 350 do_process_ue(mci, error_one, ded_add, scrb_add); 351} 352 353static inline void process_ue_no_info_wr(struct mem_ctl_info *mci, 354 int *error_found, int handle_error) 355{ 356 *error_found = 1; 357 358 if (!handle_error) 359 return; 360 361 debugf3("%s()\n", __func__); 362 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write"); 363} 364 365static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error, 366 u32 retry_add) 367{ 368 u32 error_1b, page; 369 int row; 370 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; 371 372 error_1b = retry_add; 373 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */ 374 row = pvt->mc_symmetric ? 375 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */ 376 edac_mc_find_csrow_by_page(mci, page); 377 e752x_mc_printk(mci, KERN_WARNING, 378 "CE page 0x%lx, row %d : Memory read retry\n", 379 (long unsigned int) page, row); 380} 381 382static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error, 383 u32 retry_add, int *error_found, int handle_error) 384{ 385 *error_found = 1; 386 387 if (handle_error) 388 do_process_ded_retry(mci, error, retry_add); 389} 390 391static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error, 392 int *error_found, int handle_error) 393{ 394 *error_found = 1; 395 396 if (handle_error) 397 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n"); 398} 399 400static char *global_message[11] = { 401 "PCI Express C1", "PCI Express C", "PCI Express B1", 402 "PCI Express B", "PCI Express A1", "PCI Express A", 403 "DMA Controler", "HUB Interface", "System Bus", 404 "DRAM Controler", "Internal Buffer" 405}; 406 407static char *fatal_message[2] = { "Non-Fatal ", "Fatal " }; 408 409static void do_global_error(int fatal, u32 errors) 410{ 411 int i; 412 413 for (i = 0; i < 11; i++) { 414 if (errors & (1 << i)) 415 e752x_printk(KERN_WARNING, "%sError %s\n", 416 fatal_message[fatal], global_message[i]); 417 } 418} 419 420static inline void global_error(int fatal, u32 errors, int *error_found, 421 int handle_error) 422{ 423 *error_found = 1; 424 425 if (handle_error) 426 do_global_error(fatal, errors); 427} 428 429static char *hub_message[7] = { 430 "HI Address or Command Parity", "HI Illegal Access", 431 "HI Internal Parity", "Out of Range Access", 432 "HI Data Parity", "Enhanced Config Access", 433 "Hub Interface Target Abort" 434}; 435 436static void do_hub_error(int fatal, u8 errors) 437{ 438 int i; 439 440 for (i = 0; i < 7; i++) { 441 if (errors & (1 << i)) 442 e752x_printk(KERN_WARNING, "%sError %s\n", 443 fatal_message[fatal], hub_message[i]); 444 } 445} 446 447static inline void hub_error(int fatal, u8 errors, int *error_found, 448 int handle_error) 449{ 450 *error_found = 1; 451 452 if (handle_error) 453 do_hub_error(fatal, errors); 454} 455 456static char *membuf_message[4] = { 457 "Internal PMWB to DRAM parity", 458 "Internal PMWB to System Bus Parity", 459 "Internal System Bus or IO to PMWB Parity", 460 "Internal DRAM to PMWB Parity" 461}; 462 463static void do_membuf_error(u8 errors) 464{ 465 int i; 466 467 for (i = 0; i < 4; i++) { 468 if (errors & (1 << i)) 469 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n", 470 membuf_message[i]); 471 } 472} 473 474static inline void membuf_error(u8 errors, int *error_found, int handle_error) 475{ 476 *error_found = 1; 477 478 if (handle_error) 479 do_membuf_error(errors); 480} 481 482static char *sysbus_message[10] = { 483 "Addr or Request Parity", 484 "Data Strobe Glitch", 485 "Addr Strobe Glitch", 486 "Data Parity", 487 "Addr Above TOM", 488 "Non DRAM Lock Error", 489 "MCERR", "BINIT", 490 "Memory Parity", 491 "IO Subsystem Parity" 492}; 493 494static void do_sysbus_error(int fatal, u32 errors) 495{ 496 int i; 497 498 for (i = 0; i < 10; i++) { 499 if (errors & (1 << i)) 500 e752x_printk(KERN_WARNING, "%sError System Bus %s\n", 501 fatal_message[fatal], sysbus_message[i]); 502 } 503} 504 505static inline void sysbus_error(int fatal, u32 errors, int *error_found, 506 int handle_error) 507{ 508 *error_found = 1; 509 510 if (handle_error) 511 do_sysbus_error(fatal, errors); 512} 513 514static void e752x_check_hub_interface(struct e752x_error_info *info, 515 int *error_found, int handle_error) 516{ 517 u8 stat8; 518 519 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8); 520 521 stat8 = info->hi_ferr; 522 523 if(stat8 & 0x7f) { /* Error, so process */ 524 stat8 &= 0x7f; 525 526 if(stat8 & 0x2b) 527 hub_error(1, stat8 & 0x2b, error_found, handle_error); 528 529 if(stat8 & 0x54) 530 hub_error(0, stat8 & 0x54, error_found, handle_error); 531 } 532 533 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8); 534 535 stat8 = info->hi_nerr; 536 537 if(stat8 & 0x7f) { /* Error, so process */ 538 stat8 &= 0x7f; 539 540 if (stat8 & 0x2b) 541 hub_error(1, stat8 & 0x2b, error_found, handle_error); 542 543 if(stat8 & 0x54) 544 hub_error(0, stat8 & 0x54, error_found, handle_error); 545 } 546} 547 548static void e752x_check_sysbus(struct e752x_error_info *info, 549 int *error_found, int handle_error) 550{ 551 u32 stat32, error32; 552 553 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32); 554 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16); 555 556 if (stat32 == 0) 557 return; /* no errors */ 558 559 error32 = (stat32 >> 16) & 0x3ff; 560 stat32 = stat32 & 0x3ff; 561 562 if(stat32 & 0x087) 563 sysbus_error(1, stat32 & 0x087, error_found, handle_error); 564 565 if(stat32 & 0x378) 566 sysbus_error(0, stat32 & 0x378, error_found, handle_error); 567 568 if(error32 & 0x087) 569 sysbus_error(1, error32 & 0x087, error_found, handle_error); 570 571 if(error32 & 0x378) 572 sysbus_error(0, error32 & 0x378, error_found, handle_error); 573} 574 575static void e752x_check_membuf (struct e752x_error_info *info, 576 int *error_found, int handle_error) 577{ 578 u8 stat8; 579 580 stat8 = info->buf_ferr; 581 582 if (stat8 & 0x0f) { /* Error, so process */ 583 stat8 &= 0x0f; 584 membuf_error(stat8, error_found, handle_error); 585 } 586 587 stat8 = info->buf_nerr; 588 589 if (stat8 & 0x0f) { /* Error, so process */ 590 stat8 &= 0x0f; 591 membuf_error(stat8, error_found, handle_error); 592 } 593} 594 595static void e752x_check_dram (struct mem_ctl_info *mci, 596 struct e752x_error_info *info, int *error_found, 597 int handle_error) 598{ 599 u16 error_one, error_next; 600 601 error_one = info->dram_ferr; 602 error_next = info->dram_nerr; 603 604 /* decode and report errors */ 605 if(error_one & 0x0101) /* check first error correctable */ 606 process_ce(mci, error_one, info->dram_sec1_add, 607 info->dram_sec1_syndrome, error_found, 608 handle_error); 609 610 if(error_next & 0x0101) /* check next error correctable */ 611 process_ce(mci, error_next, info->dram_sec2_add, 612 info->dram_sec2_syndrome, error_found, 613 handle_error); 614 615 if(error_one & 0x4040) 616 process_ue_no_info_wr(mci, error_found, handle_error); 617 618 if(error_next & 0x4040) 619 process_ue_no_info_wr(mci, error_found, handle_error); 620 621 if(error_one & 0x2020) 622 process_ded_retry(mci, error_one, info->dram_retr_add, 623 error_found, handle_error); 624 625 if(error_next & 0x2020) 626 process_ded_retry(mci, error_next, info->dram_retr_add, 627 error_found, handle_error); 628 629 if(error_one & 0x0808) 630 process_threshold_ce(mci, error_one, error_found, 631 handle_error); 632 633 if(error_next & 0x0808) 634 process_threshold_ce(mci, error_next, error_found, 635 handle_error); 636 637 if(error_one & 0x0606) 638 process_ue(mci, error_one, info->dram_ded_add, 639 info->dram_scrb_add, error_found, handle_error); 640 641 if(error_next & 0x0606) 642 process_ue(mci, error_next, info->dram_ded_add, 643 info->dram_scrb_add, error_found, handle_error); 644} 645 646static void e752x_get_error_info (struct mem_ctl_info *mci, 647 struct e752x_error_info *info) 648{ 649 struct pci_dev *dev; 650 struct e752x_pvt *pvt; 651 652 memset(info, 0, sizeof(*info)); 653 pvt = (struct e752x_pvt *) mci->pvt_info; 654 dev = pvt->dev_d0f1; 655 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global); 656 657 if (info->ferr_global) { 658 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr); 659 pci_read_config_word(dev, E752X_SYSBUS_FERR, 660 &info->sysbus_ferr); 661 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr); 662 pci_read_config_word(dev, E752X_DRAM_FERR, 663 &info->dram_ferr); 664 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD, 665 &info->dram_sec1_add); 666 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME, 667 &info->dram_sec1_syndrome); 668 pci_read_config_dword(dev, E752X_DRAM_DED_ADD, 669 &info->dram_ded_add); 670 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD, 671 &info->dram_scrb_add); 672 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD, 673 &info->dram_retr_add); 674 675 if (info->hi_ferr & 0x7f) 676 pci_write_config_byte(dev, E752X_HI_FERR, 677 info->hi_ferr); 678 679 if (info->sysbus_ferr) 680 pci_write_config_word(dev, E752X_SYSBUS_FERR, 681 info->sysbus_ferr); 682 683 if (info->buf_ferr & 0x0f) 684 pci_write_config_byte(dev, E752X_BUF_FERR, 685 info->buf_ferr); 686 687 if (info->dram_ferr) 688 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR, 689 info->dram_ferr, info->dram_ferr); 690 691 pci_write_config_dword(dev, E752X_FERR_GLOBAL, 692 info->ferr_global); 693 } 694 695 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global); 696 697 if (info->nerr_global) { 698 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr); 699 pci_read_config_word(dev, E752X_SYSBUS_NERR, 700 &info->sysbus_nerr); 701 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr); 702 pci_read_config_word(dev, E752X_DRAM_NERR, 703 &info->dram_nerr); 704 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD, 705 &info->dram_sec2_add); 706 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME, 707 &info->dram_sec2_syndrome); 708 709 if (info->hi_nerr & 0x7f) 710 pci_write_config_byte(dev, E752X_HI_NERR, 711 info->hi_nerr); 712 713 if (info->sysbus_nerr) 714 pci_write_config_word(dev, E752X_SYSBUS_NERR, 715 info->sysbus_nerr); 716 717 if (info->buf_nerr & 0x0f) 718 pci_write_config_byte(dev, E752X_BUF_NERR, 719 info->buf_nerr); 720 721 if (info->dram_nerr) 722 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR, 723 info->dram_nerr, info->dram_nerr); 724 725 pci_write_config_dword(dev, E752X_NERR_GLOBAL, 726 info->nerr_global); 727 } 728} 729 730static int e752x_process_error_info (struct mem_ctl_info *mci, 731 struct e752x_error_info *info, int handle_errors) 732{ 733 u32 error32, stat32; 734 int error_found; 735 736 error_found = 0; 737 error32 = (info->ferr_global >> 18) & 0x3ff; 738 stat32 = (info->ferr_global >> 4) & 0x7ff; 739 740 if (error32) 741 global_error(1, error32, &error_found, handle_errors); 742 743 if (stat32) 744 global_error(0, stat32, &error_found, handle_errors); 745 746 error32 = (info->nerr_global >> 18) & 0x3ff; 747 stat32 = (info->nerr_global >> 4) & 0x7ff; 748 749 if (error32) 750 global_error(1, error32, &error_found, handle_errors); 751 752 if (stat32) 753 global_error(0, stat32, &error_found, handle_errors); 754 755 e752x_check_hub_interface(info, &error_found, handle_errors); 756 e752x_check_sysbus(info, &error_found, handle_errors); 757 e752x_check_membuf(info, &error_found, handle_errors); 758 e752x_check_dram(mci, info, &error_found, handle_errors); 759 return error_found; 760} 761 762static void e752x_check(struct mem_ctl_info *mci) 763{ 764 struct e752x_error_info info; 765 766 debugf3("%s()\n", __func__); 767 e752x_get_error_info(mci, &info); 768 e752x_process_error_info(mci, &info, 1); 769} 770 771/* Return 1 if dual channel mode is active. Else return 0. */ 772static inline int dual_channel_active(u16 ddrcsr) 773{ 774 return (((ddrcsr >> 12) & 3) == 3); 775} 776 777static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, 778 u16 ddrcsr) 779{ 780 struct csrow_info *csrow; 781 unsigned long last_cumul_size; 782 int index, mem_dev, drc_chan; 783 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */ 784 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */ 785 u8 value; 786 u32 dra, drc, cumul_size; 787 788 dra = 0; 789 for (index=0; index < 4; index++) { 790 u8 dra_reg; 791 pci_read_config_byte(pdev, E752X_DRA+index, &dra_reg); 792 dra |= dra_reg << (index * 8); 793 } 794 pci_read_config_dword(pdev, E752X_DRC, &drc); 795 drc_chan = dual_channel_active(ddrcsr); 796 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */ 797 drc_ddim = (drc >> 20) & 0x3; 798 799 /* The dram row boundary (DRB) reg values are boundary address for 800 * each DRAM row with a granularity of 64 or 128MB (single/dual 801 * channel operation). DRB regs are cumulative; therefore DRB7 will 802 * contain the total memory contained in all eight rows. 803 */ 804 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) { 805 /* mem_dev 0=x8, 1=x4 */ 806 mem_dev = (dra >> (index * 4 + 2)) & 0x3; 807 csrow = &mci->csrows[index]; 808 809 mem_dev = (mem_dev == 2); 810 pci_read_config_byte(pdev, E752X_DRB + index, &value); 811 /* convert a 128 or 64 MiB DRB to a page size. */ 812 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); 813 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, 814 cumul_size); 815 if (cumul_size == last_cumul_size) 816 continue; /* not populated */ 817 818 csrow->first_page = last_cumul_size; 819 csrow->last_page = cumul_size - 1; 820 csrow->nr_pages = cumul_size - last_cumul_size; 821 last_cumul_size = cumul_size; 822 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ 823 csrow->mtype = MEM_RDDR; /* only one type supported */ 824 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; 825 826 /* 827 * if single channel or x8 devices then SECDED 828 * if dual channel and x4 then S4ECD4ED 829 */ 830 if (drc_ddim) { 831 if (drc_chan && mem_dev) { 832 csrow->edac_mode = EDAC_S4ECD4ED; 833 mci->edac_cap |= EDAC_FLAG_S4ECD4ED; 834 } else { 835 csrow->edac_mode = EDAC_SECDED; 836 mci->edac_cap |= EDAC_FLAG_SECDED; 837 } 838 } else 839 csrow->edac_mode = EDAC_NONE; 840 } 841} 842 843static void e752x_init_mem_map_table(struct pci_dev *pdev, 844 struct e752x_pvt *pvt) 845{ 846 int index; 847 u8 value, last, row, stat8; 848 849 last = 0; 850 row = 0; 851 852 for (index = 0; index < 8; index += 2) { 853 pci_read_config_byte(pdev, E752X_DRB + index, &value); 854 /* test if there is a dimm in this slot */ 855 if (value == last) { 856 /* no dimm in the slot, so flag it as empty */ 857 pvt->map[index] = 0xff; 858 pvt->map[index + 1] = 0xff; 859 } else { /* there is a dimm in the slot */ 860 pvt->map[index] = row; 861 row++; 862 last = value; 863 /* test the next value to see if the dimm is double 864 * sided 865 */ 866 pci_read_config_byte(pdev, E752X_DRB + index + 1, 867 &value); 868 pvt->map[index + 1] = (value == last) ? 869 0xff : /* the dimm is single sided, 870 so flag as empty */ 871 row; /* this is a double sided dimm 872 to save the next row # */ 873 row++; 874 last = value; 875 } 876 } 877 878 /* set the map type. 1 = normal, 0 = reversed */ 879 pci_read_config_byte(pdev, E752X_DRM, &stat8); 880 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f)); 881} 882 883/* Return 0 on success or 1 on failure. */ 884static int e752x_get_devs(struct pci_dev *pdev, int dev_idx, 885 struct e752x_pvt *pvt) 886{ 887 struct pci_dev *dev; 888 889 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, 890 pvt->dev_info->err_dev, 891 pvt->bridge_ck); 892 893 if (pvt->bridge_ck == NULL) 894 pvt->bridge_ck = pci_scan_single_device(pdev->bus, 895 PCI_DEVFN(0, 1)); 896 897 if (pvt->bridge_ck == NULL) { 898 e752x_printk(KERN_ERR, "error reporting device not found:" 899 "vendor %x device 0x%x (broken BIOS?)\n", 900 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev); 901 return 1; 902 } 903 904 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev, 905 NULL); 906 907 if (dev == NULL) 908 goto fail; 909 910 pvt->dev_d0f0 = dev; 911 pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck); 912 913 return 0; 914 915fail: 916 pci_dev_put(pvt->bridge_ck); 917 return 1; 918} 919 920static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt) 921{ 922 struct pci_dev *dev; 923 924 dev = pvt->dev_d0f1; 925 /* Turn off error disable & SMI in case the BIOS turned it on */ 926 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00); 927 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00); 928 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00); 929 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00); 930 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00); 931 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00); 932 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00); 933 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00); 934} 935 936static int e752x_probe1(struct pci_dev *pdev, int dev_idx) 937{ 938 u16 pci_data; 939 u8 stat8; 940 struct mem_ctl_info *mci; 941 struct e752x_pvt *pvt; 942 u16 ddrcsr; 943 int drc_chan; /* Number of channels 0=1chan,1=2chan */ 944 struct e752x_error_info discard; 945 946 debugf0("%s(): mci\n", __func__); 947 debugf0("Starting Probe1\n"); 948 949 /* check to see if device 0 function 1 is enabled; if it isn't, we 950 * assume the BIOS has reserved it for a reason and is expecting 951 * exclusive access, we take care not to violate that assumption and 952 * fail the probe. */ 953 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8); 954 if (!force_function_unhide && !(stat8 & (1 << 5))) { 955 printk(KERN_INFO "Contact your BIOS vendor to see if the " 956 "E752x error registers can be safely un-hidden\n"); 957 return -ENOMEM; 958 } 959 stat8 |= (1 << 5); 960 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8); 961 962 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr); 963 /* Dual channel = 1, Single channel = 0 */ 964 drc_chan = dual_channel_active(ddrcsr); 965 966 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1); 967 968 if (mci == NULL) { 969 return -ENOMEM; 970 } 971 972 debugf3("%s(): init mci\n", __func__); 973 mci->mtype_cap = MEM_FLAG_RDDR; 974 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | 975 EDAC_FLAG_S4ECD4ED; 976 mci->mod_name = EDAC_MOD_STR; 977 mci->mod_ver = E752X_REVISION; 978 mci->dev = &pdev->dev; 979 980 debugf3("%s(): init pvt\n", __func__); 981 pvt = (struct e752x_pvt *) mci->pvt_info; 982 pvt->dev_info = &e752x_devs[dev_idx]; 983 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0); 984 985 if (e752x_get_devs(pdev, dev_idx, pvt)) { 986 edac_mc_free(mci); 987 return -ENODEV; 988 } 989 990 debugf3("%s(): more mci init\n", __func__); 991 mci->ctl_name = pvt->dev_info->ctl_name; 992 mci->edac_check = e752x_check; 993 mci->ctl_page_to_phys = ctl_page_to_phys; 994 995 e752x_init_csrows(mci, pdev, ddrcsr); 996 e752x_init_mem_map_table(pdev, pvt); 997 998 /* set the map type. 1 = normal, 0 = reversed */ 999 pci_read_config_byte(pdev, E752X_DRM, &stat8); 1000 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f)); 1001 1002 mci->edac_cap |= EDAC_FLAG_NONE; 1003 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__); 1004 1005 /* load the top of low memory, remap base, and remap limit vars */ 1006 pci_read_config_word(pdev, E752X_TOLM, &pci_data); 1007 pvt->tolm = ((u32) pci_data) << 4; 1008 pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data); 1009 pvt->remapbase = ((u32) pci_data) << 14; 1010 pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data); 1011 pvt->remaplimit = ((u32) pci_data) << 14; 1012 e752x_printk(KERN_INFO, 1013 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm, 1014 pvt->remapbase, pvt->remaplimit); 1015 1016 /* Here we assume that we will never see multiple instances of this 1017 * type of memory controller. The ID is therefore hardcoded to 0. 1018 */ 1019 if (edac_mc_add_mc(mci,0)) { 1020 debugf3("%s(): failed edac_mc_add_mc()\n", __func__); 1021 goto fail; 1022 } 1023 1024 e752x_init_error_reporting_regs(pvt); 1025 e752x_get_error_info(mci, &discard); /* clear other MCH errors */ 1026 1027 /* get this far and it's successful */ 1028 debugf3("%s(): success\n", __func__); 1029 return 0; 1030 1031fail: 1032 pci_dev_put(pvt->dev_d0f0); 1033 pci_dev_put(pvt->dev_d0f1); 1034 pci_dev_put(pvt->bridge_ck); 1035 edac_mc_free(mci); 1036 1037 return -ENODEV; 1038} 1039 1040/* returns count (>= 0), or negative on error */ 1041static int __devinit e752x_init_one(struct pci_dev *pdev, 1042 const struct pci_device_id *ent) 1043{ 1044 debugf0("%s()\n", __func__); 1045 1046 /* wake up and enable device */ 1047 if(pci_enable_device(pdev) < 0) 1048 return -EIO; 1049 1050 return e752x_probe1(pdev, ent->driver_data); 1051} 1052 1053static void __devexit e752x_remove_one(struct pci_dev *pdev) 1054{ 1055 struct mem_ctl_info *mci; 1056 struct e752x_pvt *pvt; 1057 1058 debugf0("%s()\n", __func__); 1059 1060 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) 1061 return; 1062 1063 pvt = (struct e752x_pvt *) mci->pvt_info; 1064 pci_dev_put(pvt->dev_d0f0); 1065 pci_dev_put(pvt->dev_d0f1); 1066 pci_dev_put(pvt->bridge_ck); 1067 edac_mc_free(mci); 1068} 1069 1070static const struct pci_device_id e752x_pci_tbl[] __devinitdata = { 1071 { 1072 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1073 E7520 1074 }, 1075 { 1076 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1077 E7525 1078 }, 1079 { 1080 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1081 E7320 1082 }, 1083 { 1084 0, 1085 } /* 0 terminated list. */ 1086}; 1087 1088MODULE_DEVICE_TABLE(pci, e752x_pci_tbl); 1089 1090static struct pci_driver e752x_driver = { 1091 .name = EDAC_MOD_STR, 1092 .probe = e752x_init_one, 1093 .remove = __devexit_p(e752x_remove_one), 1094 .id_table = e752x_pci_tbl, 1095}; 1096 1097static int __init e752x_init(void) 1098{ 1099 int pci_rc; 1100 1101 debugf3("%s()\n", __func__); 1102 pci_rc = pci_register_driver(&e752x_driver); 1103 return (pci_rc < 0) ? pci_rc : 0; 1104} 1105 1106static void __exit e752x_exit(void) 1107{ 1108 debugf3("%s()\n", __func__); 1109 pci_unregister_driver(&e752x_driver); 1110} 1111 1112module_init(e752x_init); 1113module_exit(e752x_exit); 1114 1115MODULE_LICENSE("GPL"); 1116MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n"); 1117MODULE_DESCRIPTION("MC support for Intel e752x memory controllers"); 1118 1119module_param(force_function_unhide, int, 0444); 1120MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:" 1121" 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access"); 1122