1/* 2 * linux/drivers/char/watchdog/omap_wdt.c 3 * 4 * Watchdog driver for the TI OMAP 16xx & 24xx 32KHz (non-secure) watchdog 5 * 6 * Author: MontaVista Software, Inc. 7 * <gdavis@mvista.com> or <source@mvista.com> 8 * 9 * 2003 (c) MontaVista Software, Inc. This file is licensed under the 10 * terms of the GNU General Public License version 2. This program is 11 * licensed "as is" without any warranty of any kind, whether express 12 * or implied. 13 * 14 * History: 15 * 16 * 20030527: George G. Davis <gdavis@mvista.com> 17 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c 18 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu> 19 * Based on SoftDog driver by Alan Cox <alan@redhat.com> 20 * 21 * Copyright (c) 2004 Texas Instruments. 22 * 1. Modified to support OMAP1610 32-KHz watchdog timer 23 * 2. Ported to 2.6 kernel 24 * 25 * Copyright (c) 2005 David Brownell 26 * Use the driver model and standard identifiers; handle bigger timeouts. 27 */ 28 29#include <linux/module.h> 30#include <linux/types.h> 31#include <linux/kernel.h> 32#include <linux/fs.h> 33#include <linux/mm.h> 34#include <linux/miscdevice.h> 35#include <linux/watchdog.h> 36#include <linux/reboot.h> 37#include <linux/init.h> 38#include <linux/err.h> 39#include <linux/platform_device.h> 40#include <linux/moduleparam.h> 41#include <linux/clk.h> 42 43#include <asm/io.h> 44#include <asm/uaccess.h> 45#include <asm/hardware.h> 46#include <asm/bitops.h> 47 48#include <asm/arch/prcm.h> 49 50#include "omap_wdt.h" 51 52static unsigned timer_margin; 53module_param(timer_margin, uint, 0); 54MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); 55 56static int omap_wdt_users; 57static struct clk *armwdt_ck = NULL; 58static struct clk *mpu_wdt_ick = NULL; 59static struct clk *mpu_wdt_fck = NULL; 60 61static unsigned int wdt_trgr_pattern = 0x1234; 62 63static void omap_wdt_ping(void) 64{ 65 /* wait for posted write to complete */ 66 while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08) 67 cpu_relax(); 68 wdt_trgr_pattern = ~wdt_trgr_pattern; 69 omap_writel(wdt_trgr_pattern, (OMAP_WATCHDOG_TGR)); 70 /* wait for posted write to complete */ 71 while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08) 72 cpu_relax(); 73 /* reloaded WCRR from WLDR */ 74} 75 76static void omap_wdt_enable(void) 77{ 78 /* Sequence to enable the watchdog */ 79 omap_writel(0xBBBB, OMAP_WATCHDOG_SPR); 80 while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10) 81 cpu_relax(); 82 omap_writel(0x4444, OMAP_WATCHDOG_SPR); 83 while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10) 84 cpu_relax(); 85} 86 87static void omap_wdt_disable(void) 88{ 89 /* sequence required to disable watchdog */ 90 omap_writel(0xAAAA, OMAP_WATCHDOG_SPR); /* TIMER_MODE */ 91 while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10) 92 cpu_relax(); 93 omap_writel(0x5555, OMAP_WATCHDOG_SPR); /* TIMER_MODE */ 94 while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10) 95 cpu_relax(); 96} 97 98static void omap_wdt_adjust_timeout(unsigned new_timeout) 99{ 100 if (new_timeout < TIMER_MARGIN_MIN) 101 new_timeout = TIMER_MARGIN_DEFAULT; 102 if (new_timeout > TIMER_MARGIN_MAX) 103 new_timeout = TIMER_MARGIN_MAX; 104 timer_margin = new_timeout; 105} 106 107static void omap_wdt_set_timeout(void) 108{ 109 u32 pre_margin = GET_WLDR_VAL(timer_margin); 110 111 /* just count up at 32 KHz */ 112 while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04) 113 cpu_relax(); 114 omap_writel(pre_margin, OMAP_WATCHDOG_LDR); 115 while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04) 116 cpu_relax(); 117} 118 119/* 120 * Allow only one task to hold it open 121 */ 122 123static int omap_wdt_open(struct inode *inode, struct file *file) 124{ 125 if (test_and_set_bit(1, (unsigned long *)&omap_wdt_users)) 126 return -EBUSY; 127 128 if (cpu_is_omap16xx()) 129 clk_enable(armwdt_ck); /* Enable the clock */ 130 131 if (cpu_is_omap24xx()) { 132 clk_enable(mpu_wdt_ick); /* Enable the interface clock */ 133 clk_enable(mpu_wdt_fck); /* Enable the functional clock */ 134 } 135 136 /* initialize prescaler */ 137 while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01) 138 cpu_relax(); 139 omap_writel((1 << 5) | (PTV << 2), OMAP_WATCHDOG_CNTRL); 140 while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01) 141 cpu_relax(); 142 143 omap_wdt_set_timeout(); 144 omap_wdt_enable(); 145 return 0; 146} 147 148static int omap_wdt_release(struct inode *inode, struct file *file) 149{ 150 /* 151 * Shut off the timer unless NOWAYOUT is defined. 152 */ 153#ifndef CONFIG_WATCHDOG_NOWAYOUT 154 omap_wdt_disable(); 155 156 if (cpu_is_omap16xx()) { 157 clk_disable(armwdt_ck); /* Disable the clock */ 158 clk_put(armwdt_ck); 159 armwdt_ck = NULL; 160 } 161 162 if (cpu_is_omap24xx()) { 163 clk_disable(mpu_wdt_ick); /* Disable the clock */ 164 clk_disable(mpu_wdt_fck); /* Disable the clock */ 165 clk_put(mpu_wdt_ick); 166 clk_put(mpu_wdt_fck); 167 mpu_wdt_ick = NULL; 168 mpu_wdt_fck = NULL; 169 } 170#else 171 printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n"); 172#endif 173 omap_wdt_users = 0; 174 return 0; 175} 176 177static ssize_t 178omap_wdt_write(struct file *file, const char __user *data, 179 size_t len, loff_t *ppos) 180{ 181 /* Refresh LOAD_TIME. */ 182 if (len) 183 omap_wdt_ping(); 184 return len; 185} 186 187static int 188omap_wdt_ioctl(struct inode *inode, struct file *file, 189 unsigned int cmd, unsigned long arg) 190{ 191 int new_margin; 192 static struct watchdog_info ident = { 193 .identity = "OMAP Watchdog", 194 .options = WDIOF_SETTIMEOUT, 195 .firmware_version = 0, 196 }; 197 198 switch (cmd) { 199 default: 200 return -ENOIOCTLCMD; 201 case WDIOC_GETSUPPORT: 202 return copy_to_user((struct watchdog_info __user *)arg, &ident, 203 sizeof(ident)); 204 case WDIOC_GETSTATUS: 205 return put_user(0, (int __user *)arg); 206 case WDIOC_GETBOOTSTATUS: 207 if (cpu_is_omap16xx()) 208 return put_user(omap_readw(ARM_SYSST), 209 (int __user *)arg); 210 if (cpu_is_omap24xx()) 211 return put_user(omap_prcm_get_reset_sources(), 212 (int __user *)arg); 213 case WDIOC_KEEPALIVE: 214 omap_wdt_ping(); 215 return 0; 216 case WDIOC_SETTIMEOUT: 217 if (get_user(new_margin, (int __user *)arg)) 218 return -EFAULT; 219 omap_wdt_adjust_timeout(new_margin); 220 221 omap_wdt_disable(); 222 omap_wdt_set_timeout(); 223 omap_wdt_enable(); 224 225 omap_wdt_ping(); 226 /* Fall */ 227 case WDIOC_GETTIMEOUT: 228 return put_user(timer_margin, (int __user *)arg); 229 } 230} 231 232static const struct file_operations omap_wdt_fops = { 233 .owner = THIS_MODULE, 234 .write = omap_wdt_write, 235 .ioctl = omap_wdt_ioctl, 236 .open = omap_wdt_open, 237 .release = omap_wdt_release, 238}; 239 240static struct miscdevice omap_wdt_miscdev = { 241 .minor = WATCHDOG_MINOR, 242 .name = "watchdog", 243 .fops = &omap_wdt_fops 244}; 245 246static int __init omap_wdt_probe(struct platform_device *pdev) 247{ 248 struct resource *res, *mem; 249 int ret; 250 251 /* reserve static register mappings */ 252 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 253 if (!res) 254 return -ENOENT; 255 256 mem = request_mem_region(res->start, res->end - res->start + 1, 257 pdev->name); 258 if (mem == NULL) 259 return -EBUSY; 260 261 platform_set_drvdata(pdev, mem); 262 263 omap_wdt_users = 0; 264 265 if (cpu_is_omap16xx()) { 266 armwdt_ck = clk_get(&pdev->dev, "armwdt_ck"); 267 if (IS_ERR(armwdt_ck)) { 268 ret = PTR_ERR(armwdt_ck); 269 armwdt_ck = NULL; 270 goto fail; 271 } 272 } 273 274 if (cpu_is_omap24xx()) { 275 mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick"); 276 if (IS_ERR(mpu_wdt_ick)) { 277 ret = PTR_ERR(mpu_wdt_ick); 278 mpu_wdt_ick = NULL; 279 goto fail; 280 } 281 mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck"); 282 if (IS_ERR(mpu_wdt_fck)) { 283 ret = PTR_ERR(mpu_wdt_fck); 284 mpu_wdt_fck = NULL; 285 goto fail; 286 } 287 } 288 289 omap_wdt_disable(); 290 omap_wdt_adjust_timeout(timer_margin); 291 292 omap_wdt_miscdev.parent = &pdev->dev; 293 ret = misc_register(&omap_wdt_miscdev); 294 if (ret) 295 goto fail; 296 297 pr_info("OMAP Watchdog Timer: initial timeout %d sec\n", timer_margin); 298 299 /* autogate OCP interface clock */ 300 omap_writel(0x01, OMAP_WATCHDOG_SYS_CONFIG); 301 return 0; 302 303fail: 304 if (armwdt_ck) 305 clk_put(armwdt_ck); 306 if (mpu_wdt_ick) 307 clk_put(mpu_wdt_ick); 308 if (mpu_wdt_fck) 309 clk_put(mpu_wdt_fck); 310 release_resource(mem); 311 return ret; 312} 313 314static void omap_wdt_shutdown(struct platform_device *pdev) 315{ 316 omap_wdt_disable(); 317} 318 319static int omap_wdt_remove(struct platform_device *pdev) 320{ 321 struct resource *mem = platform_get_drvdata(pdev); 322 misc_deregister(&omap_wdt_miscdev); 323 release_resource(mem); 324 if (armwdt_ck) 325 clk_put(armwdt_ck); 326 if (mpu_wdt_ick) 327 clk_put(mpu_wdt_ick); 328 if (mpu_wdt_fck) 329 clk_put(mpu_wdt_fck); 330 return 0; 331} 332 333#ifdef CONFIG_PM 334 335/* REVISIT ... not clear this is the best way to handle system suspend; and 336 * it's very inappropriate for selective device suspend (e.g. suspending this 337 * through sysfs rather than by stopping the watchdog daemon). Also, this 338 * may not play well enough with NOWAYOUT... 339 */ 340 341static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state) 342{ 343 if (omap_wdt_users) 344 omap_wdt_disable(); 345 return 0; 346} 347 348static int omap_wdt_resume(struct platform_device *pdev) 349{ 350 if (omap_wdt_users) { 351 omap_wdt_enable(); 352 omap_wdt_ping(); 353 } 354 return 0; 355} 356 357#else 358#define omap_wdt_suspend NULL 359#define omap_wdt_resume NULL 360#endif 361 362static struct platform_driver omap_wdt_driver = { 363 .probe = omap_wdt_probe, 364 .remove = omap_wdt_remove, 365 .shutdown = omap_wdt_shutdown, 366 .suspend = omap_wdt_suspend, 367 .resume = omap_wdt_resume, 368 .driver = { 369 .owner = THIS_MODULE, 370 .name = "omap_wdt", 371 }, 372}; 373 374static int __init omap_wdt_init(void) 375{ 376 return platform_driver_register(&omap_wdt_driver); 377} 378 379static void __exit omap_wdt_exit(void) 380{ 381 platform_driver_unregister(&omap_wdt_driver); 382} 383 384module_init(omap_wdt_init); 385module_exit(omap_wdt_exit); 386 387MODULE_AUTHOR("George G. Davis"); 388MODULE_LICENSE("GPL"); 389MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); 390