1/* via_dmablit.c -- PCI DMA BitBlt support for the VIA Unichrome/Pro 2 * 3 * Copyright (C) 2005 Thomas Hellstrom, All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sub license, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Thomas Hellstrom. 26 * Partially based on code obtained from Digeo Inc. 27 */ 28 29 30 31#include "drmP.h" 32#include "via_drm.h" 33#include "via_drv.h" 34#include "via_dmablit.h" 35 36#include <linux/pagemap.h> 37 38#define VIA_PGDN(x) (((unsigned long)(x)) & PAGE_MASK) 39#define VIA_PGOFF(x) (((unsigned long)(x)) & ~PAGE_MASK) 40#define VIA_PFN(x) ((unsigned long)(x) >> PAGE_SHIFT) 41 42typedef struct _drm_via_descriptor { 43 uint32_t mem_addr; 44 uint32_t dev_addr; 45 uint32_t size; 46 uint32_t next; 47} drm_via_descriptor_t; 48 49 50/* 51 * Unmap a DMA mapping. 52 */ 53 54 55 56static void 57via_unmap_blit_from_device(struct pci_dev *pdev, drm_via_sg_info_t *vsg) 58{ 59 int num_desc = vsg->num_desc; 60 unsigned cur_descriptor_page = num_desc / vsg->descriptors_per_page; 61 unsigned descriptor_this_page = num_desc % vsg->descriptors_per_page; 62 drm_via_descriptor_t *desc_ptr = vsg->desc_pages[cur_descriptor_page] + 63 descriptor_this_page; 64 dma_addr_t next = vsg->chain_start; 65 66 while(num_desc--) { 67 if (descriptor_this_page-- == 0) { 68 cur_descriptor_page--; 69 descriptor_this_page = vsg->descriptors_per_page - 1; 70 desc_ptr = vsg->desc_pages[cur_descriptor_page] + 71 descriptor_this_page; 72 } 73 dma_unmap_single(&pdev->dev, next, sizeof(*desc_ptr), DMA_TO_DEVICE); 74 dma_unmap_page(&pdev->dev, desc_ptr->mem_addr, desc_ptr->size, vsg->direction); 75 next = (dma_addr_t) desc_ptr->next; 76 desc_ptr--; 77 } 78} 79 80/* 81 * If mode = 0, count how many descriptors are needed. 82 * If mode = 1, Map the DMA pages for the device, put together and map also the descriptors. 83 * Descriptors are run in reverse order by the hardware because we are not allowed to update the 84 * 'next' field without syncing calls when the descriptor is already mapped. 85 */ 86 87static void 88via_map_blit_for_device(struct pci_dev *pdev, 89 const drm_via_dmablit_t *xfer, 90 drm_via_sg_info_t *vsg, 91 int mode) 92{ 93 unsigned cur_descriptor_page = 0; 94 unsigned num_descriptors_this_page = 0; 95 unsigned char *mem_addr = xfer->mem_addr; 96 unsigned char *cur_mem; 97 unsigned char *first_addr = (unsigned char *)VIA_PGDN(mem_addr); 98 uint32_t fb_addr = xfer->fb_addr; 99 uint32_t cur_fb; 100 unsigned long line_len; 101 unsigned remaining_len; 102 int num_desc = 0; 103 int cur_line; 104 dma_addr_t next = 0 | VIA_DMA_DPR_EC; 105 drm_via_descriptor_t *desc_ptr = NULL; 106 107 if (mode == 1) 108 desc_ptr = vsg->desc_pages[cur_descriptor_page]; 109 110 for (cur_line = 0; cur_line < xfer->num_lines; ++cur_line) { 111 112 line_len = xfer->line_length; 113 cur_fb = fb_addr; 114 cur_mem = mem_addr; 115 116 while (line_len > 0) { 117 118 remaining_len = min(PAGE_SIZE-VIA_PGOFF(cur_mem), line_len); 119 line_len -= remaining_len; 120 121 if (mode == 1) { 122 desc_ptr->mem_addr = 123 dma_map_page(&pdev->dev, 124 vsg->pages[VIA_PFN(cur_mem) - 125 VIA_PFN(first_addr)], 126 VIA_PGOFF(cur_mem), remaining_len, 127 vsg->direction); 128 desc_ptr->dev_addr = cur_fb; 129 130 desc_ptr->size = remaining_len; 131 desc_ptr->next = (uint32_t) next; 132 next = dma_map_single(&pdev->dev, desc_ptr, sizeof(*desc_ptr), 133 DMA_TO_DEVICE); 134 desc_ptr++; 135 if (++num_descriptors_this_page >= vsg->descriptors_per_page) { 136 num_descriptors_this_page = 0; 137 desc_ptr = vsg->desc_pages[++cur_descriptor_page]; 138 } 139 } 140 141 num_desc++; 142 cur_mem += remaining_len; 143 cur_fb += remaining_len; 144 } 145 146 mem_addr += xfer->mem_stride; 147 fb_addr += xfer->fb_stride; 148 } 149 150 if (mode == 1) { 151 vsg->chain_start = next; 152 vsg->state = dr_via_device_mapped; 153 } 154 vsg->num_desc = num_desc; 155} 156 157/* 158 * Function that frees up all resources for a blit. It is usable even if the 159 * blit info has only been partially built as long as the status enum is consistent 160 * with the actual status of the used resources. 161 */ 162 163 164static void 165via_free_sg_info(struct pci_dev *pdev, drm_via_sg_info_t *vsg) 166{ 167 struct page *page; 168 int i; 169 170 switch(vsg->state) { 171 case dr_via_device_mapped: 172 via_unmap_blit_from_device(pdev, vsg); 173 case dr_via_desc_pages_alloc: 174 for (i=0; i<vsg->num_desc_pages; ++i) { 175 if (vsg->desc_pages[i] != NULL) 176 free_page((unsigned long)vsg->desc_pages[i]); 177 } 178 kfree(vsg->desc_pages); 179 case dr_via_pages_locked: 180 for (i=0; i<vsg->num_pages; ++i) { 181 if ( NULL != (page = vsg->pages[i])) { 182 if (! PageReserved(page) && (DMA_FROM_DEVICE == vsg->direction)) 183 SetPageDirty(page); 184 page_cache_release(page); 185 } 186 } 187 case dr_via_pages_alloc: 188 vfree(vsg->pages); 189 default: 190 vsg->state = dr_via_sg_init; 191 } 192 if (vsg->bounce_buffer) { 193 vfree(vsg->bounce_buffer); 194 vsg->bounce_buffer = NULL; 195 } 196 vsg->free_on_sequence = 0; 197} 198 199/* 200 * Fire a blit engine. 201 */ 202 203static void 204via_fire_dmablit(drm_device_t *dev, drm_via_sg_info_t *vsg, int engine) 205{ 206 drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 207 208 VIA_WRITE(VIA_PCI_DMA_MAR0 + engine*0x10, 0); 209 VIA_WRITE(VIA_PCI_DMA_DAR0 + engine*0x10, 0); 210 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD | 211 VIA_DMA_CSR_DE); 212 VIA_WRITE(VIA_PCI_DMA_MR0 + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE); 213 VIA_WRITE(VIA_PCI_DMA_BCR0 + engine*0x10, 0); 214 VIA_WRITE(VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start); 215 DRM_WRITEMEMORYBARRIER(); 216 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS); 217 VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04); 218} 219 220/* 221 * Obtain a page pointer array and lock all pages into system memory. A segmentation violation will 222 * occur here if the calling user does not have access to the submitted address. 223 */ 224 225static int 226via_lock_all_dma_pages(drm_via_sg_info_t *vsg, drm_via_dmablit_t *xfer) 227{ 228 int ret; 229 unsigned long first_pfn = VIA_PFN(xfer->mem_addr); 230 vsg->num_pages = VIA_PFN(xfer->mem_addr + (xfer->num_lines * xfer->mem_stride -1)) - 231 first_pfn + 1; 232 233 if (NULL == (vsg->pages = vmalloc(sizeof(struct page *) * vsg->num_pages))) 234 return DRM_ERR(ENOMEM); 235 memset(vsg->pages, 0, sizeof(struct page *) * vsg->num_pages); 236 down_read(¤t->mm->mmap_sem); 237 ret = get_user_pages(current, current->mm, 238 (unsigned long)xfer->mem_addr, 239 vsg->num_pages, 240 (vsg->direction == DMA_FROM_DEVICE), 241 0, vsg->pages, NULL); 242 243 up_read(¤t->mm->mmap_sem); 244 if (ret != vsg->num_pages) { 245 if (ret < 0) 246 return ret; 247 vsg->state = dr_via_pages_locked; 248 return DRM_ERR(EINVAL); 249 } 250 vsg->state = dr_via_pages_locked; 251 DRM_DEBUG("DMA pages locked\n"); 252 return 0; 253} 254 255/* 256 * Allocate DMA capable memory for the blit descriptor chain, and an array that keeps track of the 257 * pages we allocate. We don't want to use kmalloc for the descriptor chain because it may be 258 * quite large for some blits, and pages don't need to be contingous. 259 */ 260 261static int 262via_alloc_desc_pages(drm_via_sg_info_t *vsg) 263{ 264 int i; 265 266 vsg->descriptors_per_page = PAGE_SIZE / sizeof( drm_via_descriptor_t); 267 vsg->num_desc_pages = (vsg->num_desc + vsg->descriptors_per_page - 1) / 268 vsg->descriptors_per_page; 269 270 if (NULL == (vsg->desc_pages = kmalloc(sizeof(void *) * vsg->num_desc_pages, GFP_KERNEL))) 271 return DRM_ERR(ENOMEM); 272 273 memset(vsg->desc_pages, 0, sizeof(void *) * vsg->num_desc_pages); 274 vsg->state = dr_via_desc_pages_alloc; 275 for (i=0; i<vsg->num_desc_pages; ++i) { 276 if (NULL == (vsg->desc_pages[i] = 277 (drm_via_descriptor_t *) __get_free_page(GFP_KERNEL))) 278 return DRM_ERR(ENOMEM); 279 } 280 DRM_DEBUG("Allocated %d pages for %d descriptors.\n", vsg->num_desc_pages, 281 vsg->num_desc); 282 return 0; 283} 284 285static void 286via_abort_dmablit(drm_device_t *dev, int engine) 287{ 288 drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 289 290 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA); 291} 292 293static void 294via_dmablit_engine_off(drm_device_t *dev, int engine) 295{ 296 drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 297 298 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD); 299} 300 301 302 303/* 304 * The dmablit part of the IRQ handler. Trying to do only reasonably fast things here. 305 * The rest, like unmapping and freeing memory for done blits is done in a separate workqueue 306 * task. Basically the task of the interrupt handler is to submit a new blit to the engine, while 307 * the workqueue task takes care of processing associated with the old blit. 308 */ 309 310void 311via_dmablit_handler(drm_device_t *dev, int engine, int from_irq) 312{ 313 drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 314 drm_via_blitq_t *blitq = dev_priv->blit_queues + engine; 315 int cur; 316 int done_transfer; 317 unsigned long irqsave=0; 318 uint32_t status = 0; 319 320 DRM_DEBUG("DMA blit handler called. engine = %d, from_irq = %d, blitq = 0x%lx\n", 321 engine, from_irq, (unsigned long) blitq); 322 323 if (from_irq) { 324 spin_lock(&blitq->blit_lock); 325 } else { 326 spin_lock_irqsave(&blitq->blit_lock, irqsave); 327 } 328 329 done_transfer = blitq->is_active && 330 (( status = VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD); 331 done_transfer = done_transfer || ( blitq->aborting && !(status & VIA_DMA_CSR_DE)); 332 333 cur = blitq->cur; 334 if (done_transfer) { 335 336 blitq->blits[cur]->aborted = blitq->aborting; 337 blitq->done_blit_handle++; 338 DRM_WAKEUP(blitq->blit_queue + cur); 339 340 cur++; 341 if (cur >= VIA_NUM_BLIT_SLOTS) 342 cur = 0; 343 blitq->cur = cur; 344 345 /* 346 * Clear transfer done flag. 347 */ 348 349 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD); 350 351 blitq->is_active = 0; 352 blitq->aborting = 0; 353 schedule_work(&blitq->wq); 354 355 } else if (blitq->is_active && time_after_eq(jiffies, blitq->end)) { 356 357 /* 358 * Abort transfer after one second. 359 */ 360 361 via_abort_dmablit(dev, engine); 362 blitq->aborting = 1; 363 blitq->end = jiffies + DRM_HZ; 364 } 365 366 if (!blitq->is_active) { 367 if (blitq->num_outstanding) { 368 via_fire_dmablit(dev, blitq->blits[cur], engine); 369 blitq->is_active = 1; 370 blitq->cur = cur; 371 blitq->num_outstanding--; 372 blitq->end = jiffies + DRM_HZ; 373 if (!timer_pending(&blitq->poll_timer)) 374 mod_timer(&blitq->poll_timer, jiffies + 1); 375 } else { 376 if (timer_pending(&blitq->poll_timer)) { 377 del_timer(&blitq->poll_timer); 378 } 379 via_dmablit_engine_off(dev, engine); 380 } 381 } 382 383 if (from_irq) { 384 spin_unlock(&blitq->blit_lock); 385 } else { 386 spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 387 } 388} 389 390 391 392/* 393 * Check whether this blit is still active, performing necessary locking. 394 */ 395 396static int 397via_dmablit_active(drm_via_blitq_t *blitq, int engine, uint32_t handle, wait_queue_head_t **queue) 398{ 399 unsigned long irqsave; 400 uint32_t slot; 401 int active; 402 403 spin_lock_irqsave(&blitq->blit_lock, irqsave); 404 405 /* 406 * Allow for handle wraparounds. 407 */ 408 409 active = ((blitq->done_blit_handle - handle) > (1 << 23)) && 410 ((blitq->cur_blit_handle - handle) <= (1 << 23)); 411 412 if (queue && active) { 413 slot = handle - blitq->done_blit_handle + blitq->cur -1; 414 if (slot >= VIA_NUM_BLIT_SLOTS) { 415 slot -= VIA_NUM_BLIT_SLOTS; 416 } 417 *queue = blitq->blit_queue + slot; 418 } 419 420 spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 421 422 return active; 423} 424 425/* 426 * Sync. Wait for at least three seconds for the blit to be performed. 427 */ 428 429static int 430via_dmablit_sync(drm_device_t *dev, uint32_t handle, int engine) 431{ 432 433 drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 434 drm_via_blitq_t *blitq = dev_priv->blit_queues + engine; 435 wait_queue_head_t *queue; 436 int ret = 0; 437 438 if (via_dmablit_active(blitq, engine, handle, &queue)) { 439 DRM_WAIT_ON(ret, *queue, 3 * DRM_HZ, 440 !via_dmablit_active(blitq, engine, handle, NULL)); 441 } 442 DRM_DEBUG("DMA blit sync handle 0x%x engine %d returned %d\n", 443 handle, engine, ret); 444 445 return ret; 446} 447 448 449/* 450 * A timer that regularly polls the blit engine in cases where we don't have interrupts: 451 * a) Broken hardware (typically those that don't have any video capture facility). 452 * b) Blit abort. The hardware doesn't send an interrupt when a blit is aborted. 453 * The timer and hardware IRQ's can and do work in parallel. If the hardware has 454 * irqs, it will shorten the latency somewhat. 455 */ 456 457 458 459static void 460via_dmablit_timer(unsigned long data) 461{ 462 drm_via_blitq_t *blitq = (drm_via_blitq_t *) data; 463 drm_device_t *dev = blitq->dev; 464 int engine = (int) 465 (blitq - ((drm_via_private_t *)dev->dev_private)->blit_queues); 466 467 DRM_DEBUG("Polling timer called for engine %d, jiffies %lu\n", engine, 468 (unsigned long) jiffies); 469 470 via_dmablit_handler(dev, engine, 0); 471 472 if (!timer_pending(&blitq->poll_timer)) { 473 mod_timer(&blitq->poll_timer, jiffies + 1); 474 475 /* 476 * Rerun handler to delete timer if engines are off, and 477 * to shorten abort latency. This is a little nasty. 478 */ 479 480 via_dmablit_handler(dev, engine, 0); 481 482 } 483} 484 485 486 487 488/* 489 * Workqueue task that frees data and mappings associated with a blit. 490 * Also wakes up waiting processes. Each of these tasks handles one 491 * blit engine only and may not be called on each interrupt. 492 */ 493 494 495static void 496via_dmablit_workqueue(struct work_struct *work) 497{ 498 drm_via_blitq_t *blitq = container_of(work, drm_via_blitq_t, wq); 499 drm_device_t *dev = blitq->dev; 500 unsigned long irqsave; 501 drm_via_sg_info_t *cur_sg; 502 int cur_released; 503 504 505 DRM_DEBUG("Workqueue task called for blit engine %ld\n",(unsigned long) 506 (blitq - ((drm_via_private_t *)dev->dev_private)->blit_queues)); 507 508 spin_lock_irqsave(&blitq->blit_lock, irqsave); 509 510 while(blitq->serviced != blitq->cur) { 511 512 cur_released = blitq->serviced++; 513 514 DRM_DEBUG("Releasing blit slot %d\n", cur_released); 515 516 if (blitq->serviced >= VIA_NUM_BLIT_SLOTS) 517 blitq->serviced = 0; 518 519 cur_sg = blitq->blits[cur_released]; 520 blitq->num_free++; 521 522 spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 523 524 DRM_WAKEUP(&blitq->busy_queue); 525 526 via_free_sg_info(dev->pdev, cur_sg); 527 kfree(cur_sg); 528 529 spin_lock_irqsave(&blitq->blit_lock, irqsave); 530 } 531 532 spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 533} 534 535 536/* 537 * Init all blit engines. Currently we use two, but some hardware have 4. 538 */ 539 540 541void 542via_init_dmablit(drm_device_t *dev) 543{ 544 int i,j; 545 drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 546 drm_via_blitq_t *blitq; 547 548 pci_set_master(dev->pdev); 549 550 for (i=0; i< VIA_NUM_BLIT_ENGINES; ++i) { 551 blitq = dev_priv->blit_queues + i; 552 blitq->dev = dev; 553 blitq->cur_blit_handle = 0; 554 blitq->done_blit_handle = 0; 555 blitq->head = 0; 556 blitq->cur = 0; 557 blitq->serviced = 0; 558 blitq->num_free = VIA_NUM_BLIT_SLOTS; 559 blitq->num_outstanding = 0; 560 blitq->is_active = 0; 561 blitq->aborting = 0; 562 spin_lock_init(&blitq->blit_lock); 563 for (j=0; j<VIA_NUM_BLIT_SLOTS; ++j) { 564 DRM_INIT_WAITQUEUE(blitq->blit_queue + j); 565 } 566 DRM_INIT_WAITQUEUE(&blitq->busy_queue); 567 INIT_WORK(&blitq->wq, via_dmablit_workqueue); 568 setup_timer(&blitq->poll_timer, via_dmablit_timer, 569 (unsigned long)blitq); 570 } 571} 572 573/* 574 * Build all info and do all mappings required for a blit. 575 */ 576 577 578static int 579via_build_sg_info(drm_device_t *dev, drm_via_sg_info_t *vsg, drm_via_dmablit_t *xfer) 580{ 581 int draw = xfer->to_fb; 582 int ret = 0; 583 584 vsg->direction = (draw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 585 vsg->bounce_buffer = NULL; 586 587 vsg->state = dr_via_sg_init; 588 589 if (xfer->num_lines <= 0 || xfer->line_length <= 0) { 590 DRM_ERROR("Zero size bitblt.\n"); 591 return DRM_ERR(EINVAL); 592 } 593 594 /* 595 * Below check is a driver limitation, not a hardware one. We 596 * don't want to lock unused pages, and don't want to incoporate the 597 * extra logic of avoiding them. Make sure there are no. 598 * (Not a big limitation anyway.) 599 */ 600 601 if ((xfer->mem_stride - xfer->line_length) >= PAGE_SIZE) { 602 DRM_ERROR("Too large system memory stride. Stride: %d, " 603 "Length: %d\n", xfer->mem_stride, xfer->line_length); 604 return DRM_ERR(EINVAL); 605 } 606 607 if ((xfer->mem_stride == xfer->line_length) && 608 (xfer->fb_stride == xfer->line_length)) { 609 xfer->mem_stride *= xfer->num_lines; 610 xfer->line_length = xfer->mem_stride; 611 xfer->fb_stride = xfer->mem_stride; 612 xfer->num_lines = 1; 613 } 614 615 /* 616 * Don't lock an arbitrary large number of pages, since that causes a 617 * DOS security hole. 618 */ 619 620 if (xfer->num_lines > 2048 || (xfer->num_lines*xfer->mem_stride > (2048*2048*4))) { 621 DRM_ERROR("Too large PCI DMA bitblt.\n"); 622 return DRM_ERR(EINVAL); 623 } 624 625 /* 626 * we allow a negative fb stride to allow flipping of images in 627 * transfer. 628 */ 629 630 if (xfer->mem_stride < xfer->line_length || 631 abs(xfer->fb_stride) < xfer->line_length) { 632 DRM_ERROR("Invalid frame-buffer / memory stride.\n"); 633 return DRM_ERR(EINVAL); 634 } 635 636 /* 637 * A hardware bug seems to be worked around if system memory addresses start on 638 * 16 byte boundaries. This seems a bit restrictive however. VIA is contacted 639 * about this. Meanwhile, impose the following restrictions: 640 */ 641 642#ifdef VIA_BUGFREE 643 if ((((unsigned long)xfer->mem_addr & 3) != ((unsigned long)xfer->fb_addr & 3)) || 644 ((xfer->num_lines > 1) && ((xfer->mem_stride & 3) != (xfer->fb_stride & 3)))) { 645 DRM_ERROR("Invalid DRM bitblt alignment.\n"); 646 return DRM_ERR(EINVAL); 647 } 648#else 649 if ((((unsigned long)xfer->mem_addr & 15) || 650 ((unsigned long)xfer->fb_addr & 3)) || 651 ((xfer->num_lines > 1) && 652 ((xfer->mem_stride & 15) || (xfer->fb_stride & 3)))) { 653 DRM_ERROR("Invalid DRM bitblt alignment.\n"); 654 return DRM_ERR(EINVAL); 655 } 656#endif 657 658 if (0 != (ret = via_lock_all_dma_pages(vsg, xfer))) { 659 DRM_ERROR("Could not lock DMA pages.\n"); 660 via_free_sg_info(dev->pdev, vsg); 661 return ret; 662 } 663 664 via_map_blit_for_device(dev->pdev, xfer, vsg, 0); 665 if (0 != (ret = via_alloc_desc_pages(vsg))) { 666 DRM_ERROR("Could not allocate DMA descriptor pages.\n"); 667 via_free_sg_info(dev->pdev, vsg); 668 return ret; 669 } 670 via_map_blit_for_device(dev->pdev, xfer, vsg, 1); 671 672 return 0; 673} 674 675 676/* 677 * Reserve one free slot in the blit queue. Will wait for one second for one 678 * to become available. Otherwise -EBUSY is returned. 679 */ 680 681static int 682via_dmablit_grab_slot(drm_via_blitq_t *blitq, int engine) 683{ 684 int ret=0; 685 unsigned long irqsave; 686 687 DRM_DEBUG("Num free is %d\n", blitq->num_free); 688 spin_lock_irqsave(&blitq->blit_lock, irqsave); 689 while(blitq->num_free == 0) { 690 spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 691 692 DRM_WAIT_ON(ret, blitq->busy_queue, DRM_HZ, blitq->num_free > 0); 693 if (ret) { 694 return (DRM_ERR(EINTR) == ret) ? DRM_ERR(EAGAIN) : ret; 695 } 696 697 spin_lock_irqsave(&blitq->blit_lock, irqsave); 698 } 699 700 blitq->num_free--; 701 spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 702 703 return 0; 704} 705 706/* 707 * Hand back a free slot if we changed our mind. 708 */ 709 710static void 711via_dmablit_release_slot(drm_via_blitq_t *blitq) 712{ 713 unsigned long irqsave; 714 715 spin_lock_irqsave(&blitq->blit_lock, irqsave); 716 blitq->num_free++; 717 spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 718 DRM_WAKEUP( &blitq->busy_queue ); 719} 720 721/* 722 * Grab a free slot. Build blit info and queue a blit. 723 */ 724 725 726static int 727via_dmablit(drm_device_t *dev, drm_via_dmablit_t *xfer) 728{ 729 drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 730 drm_via_sg_info_t *vsg; 731 drm_via_blitq_t *blitq; 732 int ret; 733 int engine; 734 unsigned long irqsave; 735 736 if (dev_priv == NULL) { 737 DRM_ERROR("Called without initialization.\n"); 738 return DRM_ERR(EINVAL); 739 } 740 741 engine = (xfer->to_fb) ? 0 : 1; 742 blitq = dev_priv->blit_queues + engine; 743 if (0 != (ret = via_dmablit_grab_slot(blitq, engine))) { 744 return ret; 745 } 746 if (NULL == (vsg = kmalloc(sizeof(*vsg), GFP_KERNEL))) { 747 via_dmablit_release_slot(blitq); 748 return DRM_ERR(ENOMEM); 749 } 750 if (0 != (ret = via_build_sg_info(dev, vsg, xfer))) { 751 via_dmablit_release_slot(blitq); 752 kfree(vsg); 753 return ret; 754 } 755 spin_lock_irqsave(&blitq->blit_lock, irqsave); 756 757 blitq->blits[blitq->head++] = vsg; 758 if (blitq->head >= VIA_NUM_BLIT_SLOTS) 759 blitq->head = 0; 760 blitq->num_outstanding++; 761 xfer->sync.sync_handle = ++blitq->cur_blit_handle; 762 763 spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 764 xfer->sync.engine = engine; 765 766 via_dmablit_handler(dev, engine, 0); 767 768 return 0; 769} 770 771/* 772 * Sync on a previously submitted blit. Note that the X server use signals extensively, and 773 * that there is a very big probability that this IOCTL will be interrupted by a signal. In that 774 * case it returns with -EAGAIN for the signal to be delivered. 775 * The caller should then reissue the IOCTL. This is similar to what is being done for drmGetLock(). 776 */ 777 778int 779via_dma_blit_sync( DRM_IOCTL_ARGS ) 780{ 781 drm_via_blitsync_t sync; 782 int err; 783 DRM_DEVICE; 784 785 DRM_COPY_FROM_USER_IOCTL(sync, (drm_via_blitsync_t *)data, sizeof(sync)); 786 787 if (sync.engine >= VIA_NUM_BLIT_ENGINES) 788 return DRM_ERR(EINVAL); 789 790 err = via_dmablit_sync(dev, sync.sync_handle, sync.engine); 791 792 if (DRM_ERR(EINTR) == err) 793 err = DRM_ERR(EAGAIN); 794 795 return err; 796} 797 798 799/* 800 * Queue a blit and hand back a handle to be used for sync. This IOCTL may be interrupted by a signal 801 * while waiting for a free slot in the blit queue. In that case it returns with -EAGAIN and should 802 * be reissued. See the above IOCTL code. 803 */ 804 805int 806via_dma_blit( DRM_IOCTL_ARGS ) 807{ 808 drm_via_dmablit_t xfer; 809 int err; 810 DRM_DEVICE; 811 812 DRM_COPY_FROM_USER_IOCTL(xfer, (drm_via_dmablit_t __user *)data, sizeof(xfer)); 813 814 err = via_dmablit(dev, &xfer); 815 816 DRM_COPY_TO_USER_IOCTL((void __user *)data, xfer, sizeof(xfer)); 817 818 return err; 819} 820