1/*
2 * VIA AGPGART routines.
3 */
4
5#include <linux/types.h>
6#include <linux/module.h>
7#include <linux/pci.h>
8#include <linux/init.h>
9#include <linux/agp_backend.h>
10#include "agp.h"
11
12static const struct pci_device_id agp_via_pci_table[];
13
14#define VIA_GARTCTRL	0x80
15#define VIA_APSIZE	0x84
16#define VIA_ATTBASE	0x88
17
18#define VIA_AGP3_GARTCTRL	0x90
19#define VIA_AGP3_APSIZE		0x94
20#define VIA_AGP3_ATTBASE	0x98
21#define VIA_AGPSEL		0xfd
22
23static int via_fetch_size(void)
24{
25	int i;
26	u8 temp;
27	struct aper_size_info_8 *values;
28
29	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
30	pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);
31	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
32		if (temp == values[i].size_value) {
33			agp_bridge->previous_size =
34			    agp_bridge->current_size = (void *) (values + i);
35			agp_bridge->aperture_size_idx = i;
36			return values[i].size;
37		}
38	}
39	printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp);
40	return 0;
41}
42
43
44static int via_configure(void)
45{
46	u32 temp;
47	struct aper_size_info_8 *current_size;
48
49	current_size = A_SIZE_8(agp_bridge->current_size);
50	/* aperture size */
51	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
52			      current_size->size_value);
53	/* address to map too */
54	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
55	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
56
57	/* GART control register */
58	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
59
60	/* attbase - aperture GATT base */
61	pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,
62			    (agp_bridge->gatt_bus_addr & 0xfffff000) | 3);
63	return 0;
64}
65
66
67static void via_cleanup(void)
68{
69	struct aper_size_info_8 *previous_size;
70
71	previous_size = A_SIZE_8(agp_bridge->previous_size);
72	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
73			      previous_size->size_value);
74	/* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
75	 * during reinitialization.
76	 */
77}
78
79
80static void via_tlbflush(struct agp_memory *mem)
81{
82	u32 temp;
83
84	pci_read_config_dword(agp_bridge->dev, VIA_GARTCTRL, &temp);
85	temp |= (1<<7);
86	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
87	temp &= ~(1<<7);
88	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
89}
90
91
92static const struct aper_size_info_8 via_generic_sizes[9] =
93{
94	{256, 65536, 6, 0},
95	{128, 32768, 5, 128},
96	{64, 16384, 4, 192},
97	{32, 8192, 3, 224},
98	{16, 4096, 2, 240},
99	{8, 2048, 1, 248},
100	{4, 1024, 0, 252},
101	{2, 512, 0, 254},
102	{1, 256, 0, 255}
103};
104
105
106static int via_fetch_size_agp3(void)
107{
108	int i;
109	u16 temp;
110	struct aper_size_info_16 *values;
111
112	values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
113	pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp);
114	temp &= 0xfff;
115
116	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
117		if (temp == values[i].size_value) {
118			agp_bridge->previous_size =
119				agp_bridge->current_size = (void *) (values + i);
120			agp_bridge->aperture_size_idx = i;
121			return values[i].size;
122		}
123	}
124	return 0;
125}
126
127
128static int via_configure_agp3(void)
129{
130	u32 temp;
131	struct aper_size_info_16 *current_size;
132
133	current_size = A_SIZE_16(agp_bridge->current_size);
134
135	/* address to map too */
136	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
137	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
138
139	/* attbase - aperture GATT base */
140	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
141		agp_bridge->gatt_bus_addr & 0xfffff000);
142
143	/* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch
144	 *    translation table first.
145	 * 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the
146	 *    graphics AGP aperture for the AGP3.0 port.
147	 */
148	pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
149	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp | (3<<7));
150	return 0;
151}
152
153
154static void via_cleanup_agp3(void)
155{
156	struct aper_size_info_16 *previous_size;
157
158	previous_size = A_SIZE_16(agp_bridge->previous_size);
159	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value);
160}
161
162
163static void via_tlbflush_agp3(struct agp_memory *mem)
164{
165	u32 temp;
166
167	pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
168	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
169	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp);
170}
171
172
173static const struct agp_bridge_driver via_agp3_driver = {
174	.owner			= THIS_MODULE,
175	.aperture_sizes		= agp3_generic_sizes,
176	.size_type		= U8_APER_SIZE,
177	.num_aperture_sizes	= 10,
178	.configure		= via_configure_agp3,
179	.fetch_size		= via_fetch_size_agp3,
180	.cleanup		= via_cleanup_agp3,
181	.tlb_flush		= via_tlbflush_agp3,
182	.mask_memory		= agp_generic_mask_memory,
183	.masks			= NULL,
184	.agp_enable		= agp_generic_enable,
185	.cache_flush		= global_cache_flush,
186	.create_gatt_table	= agp_generic_create_gatt_table,
187	.free_gatt_table	= agp_generic_free_gatt_table,
188	.insert_memory		= agp_generic_insert_memory,
189	.remove_memory		= agp_generic_remove_memory,
190	.alloc_by_type		= agp_generic_alloc_by_type,
191	.free_by_type		= agp_generic_free_by_type,
192	.agp_alloc_page		= agp_generic_alloc_page,
193	.agp_destroy_page	= agp_generic_destroy_page,
194	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
195};
196
197static const struct agp_bridge_driver via_driver = {
198	.owner			= THIS_MODULE,
199	.aperture_sizes		= via_generic_sizes,
200	.size_type		= U8_APER_SIZE,
201	.num_aperture_sizes	= 9,
202	.configure		= via_configure,
203	.fetch_size		= via_fetch_size,
204	.cleanup		= via_cleanup,
205	.tlb_flush		= via_tlbflush,
206	.mask_memory		= agp_generic_mask_memory,
207	.masks			= NULL,
208	.agp_enable		= agp_generic_enable,
209	.cache_flush		= global_cache_flush,
210	.create_gatt_table	= agp_generic_create_gatt_table,
211	.free_gatt_table	= agp_generic_free_gatt_table,
212	.insert_memory		= agp_generic_insert_memory,
213	.remove_memory		= agp_generic_remove_memory,
214	.alloc_by_type		= agp_generic_alloc_by_type,
215	.free_by_type		= agp_generic_free_by_type,
216	.agp_alloc_page		= agp_generic_alloc_page,
217	.agp_destroy_page	= agp_generic_destroy_page,
218	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
219};
220
221static struct agp_device_ids via_agp_device_ids[] __devinitdata =
222{
223	{
224		.device_id	= PCI_DEVICE_ID_VIA_82C597_0,
225		.chipset_name	= "Apollo VP3",
226	},
227
228	{
229		.device_id	= PCI_DEVICE_ID_VIA_82C598_0,
230		.chipset_name	= "Apollo MVP3",
231	},
232
233	{
234		.device_id	= PCI_DEVICE_ID_VIA_8501_0,
235		.chipset_name	= "Apollo MVP4",
236	},
237
238	/* VT8601 */
239	{
240		.device_id	= PCI_DEVICE_ID_VIA_8601_0,
241		.chipset_name	= "Apollo ProMedia/PLE133Ta",
242	},
243
244	/* VT82C693A / VT28C694T */
245	{
246		.device_id	= PCI_DEVICE_ID_VIA_82C691_0,
247		.chipset_name	= "Apollo Pro 133",
248	},
249
250	{
251		.device_id	= PCI_DEVICE_ID_VIA_8371_0,
252		.chipset_name	= "KX133",
253	},
254
255	/* VT8633 */
256	{
257		.device_id	= PCI_DEVICE_ID_VIA_8633_0,
258		.chipset_name	= "Pro 266",
259	},
260
261	{
262		.device_id	= PCI_DEVICE_ID_VIA_XN266,
263		.chipset_name	= "Apollo Pro266",
264	},
265
266	/* VT8361 */
267	{
268		.device_id	= PCI_DEVICE_ID_VIA_8361,
269		.chipset_name	= "KLE133",
270	},
271
272	/* VT8365 / VT8362 */
273	{
274		.device_id	= PCI_DEVICE_ID_VIA_8363_0,
275		.chipset_name	= "Twister-K/KT133x/KM133",
276	},
277
278	/* VT8753A */
279	{
280		.device_id	= PCI_DEVICE_ID_VIA_8753_0,
281		.chipset_name	= "P4X266",
282	},
283
284	/* VT8366 */
285	{
286		.device_id	= PCI_DEVICE_ID_VIA_8367_0,
287		.chipset_name	= "KT266/KY266x/KT333",
288	},
289
290	/* VT8633 (for CuMine/ Celeron) */
291	{
292		.device_id	= PCI_DEVICE_ID_VIA_8653_0,
293		.chipset_name	= "Pro266T",
294	},
295
296	/* KM266 / PM266 */
297	{
298		.device_id	= PCI_DEVICE_ID_VIA_XM266,
299		.chipset_name	= "PM266/KM266",
300	},
301
302	/* CLE266 */
303	{
304		.device_id	= PCI_DEVICE_ID_VIA_862X_0,
305		.chipset_name	= "CLE266",
306	},
307
308	{
309		.device_id	= PCI_DEVICE_ID_VIA_8377_0,
310		.chipset_name	= "KT400/KT400A/KT600",
311	},
312
313	/* VT8604 / VT8605 / VT8603
314	 * (Apollo Pro133A chipset with S3 Savage4) */
315	{
316		.device_id	= PCI_DEVICE_ID_VIA_8605_0,
317		.chipset_name	= "ProSavage PM133/PL133/PN133"
318	},
319
320	/* P4M266x/P4N266 */
321	{
322		.device_id	= PCI_DEVICE_ID_VIA_8703_51_0,
323		.chipset_name	= "P4M266x/P4N266",
324	},
325
326	/* VT8754 */
327	{
328		.device_id	= PCI_DEVICE_ID_VIA_8754C_0,
329		.chipset_name	= "PT800",
330	},
331
332	/* P4X600 */
333	{
334		.device_id	= PCI_DEVICE_ID_VIA_8763_0,
335		.chipset_name	= "P4X600"
336	},
337
338	/* KM400 */
339	{
340		.device_id	= PCI_DEVICE_ID_VIA_8378_0,
341		.chipset_name	= "KM400/KM400A",
342	},
343
344	/* PT880 */
345	{
346		.device_id	= PCI_DEVICE_ID_VIA_PT880,
347		.chipset_name	= "PT880",
348	},
349
350	/* PT880 Ultra */
351	{
352		.device_id	= PCI_DEVICE_ID_VIA_PT880ULTRA,
353		.chipset_name	= "PT880 Ultra",
354	},
355
356	/* PT890 */
357	{
358		.device_id	= PCI_DEVICE_ID_VIA_8783_0,
359		.chipset_name	= "PT890",
360	},
361
362	/* PM800/PN800/PM880/PN880 */
363	{
364		.device_id	= PCI_DEVICE_ID_VIA_PX8X0_0,
365		.chipset_name	= "PM800/PN800/PM880/PN880",
366	},
367	/* KT880 */
368	{
369		.device_id	= PCI_DEVICE_ID_VIA_3269_0,
370		.chipset_name	= "KT880",
371	},
372	/* KTxxx/Px8xx */
373	{
374		.device_id	= PCI_DEVICE_ID_VIA_83_87XX_1,
375		.chipset_name	= "VT83xx/VT87xx/KTxxx/Px8xx",
376	},
377	/* P4M800 */
378	{
379		.device_id	= PCI_DEVICE_ID_VIA_3296_0,
380		.chipset_name	= "P4M800",
381	},
382	/* P4M800CE */
383	{
384		.device_id	= PCI_DEVICE_ID_VIA_P4M800CE,
385		.chipset_name	= "VT3314",
386	},
387	/* VT3324 / CX700 */
388	{
389		.device_id  = PCI_DEVICE_ID_VIA_VT3324,
390		.chipset_name   = "CX700",
391	},
392	/* VT3336 */
393	{
394		.device_id  = PCI_DEVICE_ID_VIA_VT3336,
395		.chipset_name   = "VT3336",
396	},
397	/* P4M890 */
398	{
399		.device_id  = PCI_DEVICE_ID_VIA_P4M890,
400		.chipset_name   = "P4M890",
401	},
402	{ }, /* dummy final entry, always present */
403};
404
405
406/*
407 * VIA's AGP3 chipsets do magick to put the AGP bridge compliant
408 * with the same standards version as the graphics card.
409 */
410static void check_via_agp3 (struct agp_bridge_data *bridge)
411{
412	u8 reg;
413
414	pci_read_config_byte(bridge->dev, VIA_AGPSEL, &reg);
415	/* Check AGP 2.0 compatibility mode. */
416	if ((reg & (1<<1))==0)
417		bridge->driver = &via_agp3_driver;
418}
419
420
421static int __devinit agp_via_probe(struct pci_dev *pdev,
422				   const struct pci_device_id *ent)
423{
424	struct agp_device_ids *devs = via_agp_device_ids;
425	struct agp_bridge_data *bridge;
426	int j = 0;
427	u8 cap_ptr;
428
429	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
430	if (!cap_ptr)
431		return -ENODEV;
432
433	j = ent - agp_via_pci_table;
434	printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name);
435
436	bridge = agp_alloc_bridge();
437	if (!bridge)
438		return -ENOMEM;
439
440	bridge->dev = pdev;
441	bridge->capndx = cap_ptr;
442	bridge->driver = &via_driver;
443
444	/*
445	 * Garg, there are KT400s with KT266 IDs.
446	 */
447	if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
448		/* Is there a KT400 subsystem ? */
449		if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) {
450			printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
451			check_via_agp3(bridge);
452		}
453	}
454
455	/* If this is an AGP3 bridge, check which mode its in and adjust. */
456	get_agp_version(bridge);
457	if (bridge->major_version >= 3)
458		check_via_agp3(bridge);
459
460	/* Fill in the mode register */
461	pci_read_config_dword(pdev,
462			bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
463
464	pci_set_drvdata(pdev, bridge);
465	return agp_add_bridge(bridge);
466}
467
468static void __devexit agp_via_remove(struct pci_dev *pdev)
469{
470	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
471
472	agp_remove_bridge(bridge);
473	agp_put_bridge(bridge);
474}
475
476#ifdef CONFIG_PM
477
478static int agp_via_suspend(struct pci_dev *pdev, pm_message_t state)
479{
480	pci_save_state (pdev);
481	pci_set_power_state (pdev, PCI_D3hot);
482
483	return 0;
484}
485
486static int agp_via_resume(struct pci_dev *pdev)
487{
488	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
489
490	pci_set_power_state (pdev, PCI_D0);
491	pci_restore_state(pdev);
492
493	if (bridge->driver == &via_agp3_driver)
494		return via_configure_agp3();
495	else if (bridge->driver == &via_driver)
496		return via_configure();
497
498	return 0;
499}
500
501#endif /* CONFIG_PM */
502
503/* must be the same order as name table above */
504static const struct pci_device_id agp_via_pci_table[] = {
505#define ID(x) \
506	{						\
507	.class		= (PCI_CLASS_BRIDGE_HOST << 8),	\
508	.class_mask	= ~0,				\
509	.vendor		= PCI_VENDOR_ID_VIA,		\
510	.device		= x,				\
511	.subvendor	= PCI_ANY_ID,			\
512	.subdevice	= PCI_ANY_ID,			\
513	}
514	ID(PCI_DEVICE_ID_VIA_82C597_0),
515	ID(PCI_DEVICE_ID_VIA_82C598_0),
516	ID(PCI_DEVICE_ID_VIA_8501_0),
517	ID(PCI_DEVICE_ID_VIA_8601_0),
518	ID(PCI_DEVICE_ID_VIA_82C691_0),
519	ID(PCI_DEVICE_ID_VIA_8371_0),
520	ID(PCI_DEVICE_ID_VIA_8633_0),
521	ID(PCI_DEVICE_ID_VIA_XN266),
522	ID(PCI_DEVICE_ID_VIA_8361),
523	ID(PCI_DEVICE_ID_VIA_8363_0),
524	ID(PCI_DEVICE_ID_VIA_8753_0),
525	ID(PCI_DEVICE_ID_VIA_8367_0),
526	ID(PCI_DEVICE_ID_VIA_8653_0),
527	ID(PCI_DEVICE_ID_VIA_XM266),
528	ID(PCI_DEVICE_ID_VIA_862X_0),
529	ID(PCI_DEVICE_ID_VIA_8377_0),
530	ID(PCI_DEVICE_ID_VIA_8605_0),
531	ID(PCI_DEVICE_ID_VIA_8703_51_0),
532	ID(PCI_DEVICE_ID_VIA_8754C_0),
533	ID(PCI_DEVICE_ID_VIA_8763_0),
534	ID(PCI_DEVICE_ID_VIA_8378_0),
535	ID(PCI_DEVICE_ID_VIA_PT880),
536	ID(PCI_DEVICE_ID_VIA_PT880ULTRA),
537	ID(PCI_DEVICE_ID_VIA_8783_0),
538	ID(PCI_DEVICE_ID_VIA_PX8X0_0),
539	ID(PCI_DEVICE_ID_VIA_3269_0),
540	ID(PCI_DEVICE_ID_VIA_83_87XX_1),
541	ID(PCI_DEVICE_ID_VIA_3296_0),
542	ID(PCI_DEVICE_ID_VIA_P4M800CE),
543	ID(PCI_DEVICE_ID_VIA_VT3324),
544	ID(PCI_DEVICE_ID_VIA_VT3336),
545	ID(PCI_DEVICE_ID_VIA_P4M890),
546	{ }
547};
548
549MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
550
551
552static struct pci_driver agp_via_pci_driver = {
553	.name		= "agpgart-via",
554	.id_table	= agp_via_pci_table,
555	.probe		= agp_via_probe,
556	.remove		= agp_via_remove,
557#ifdef CONFIG_PM
558	.suspend	= agp_via_suspend,
559	.resume		= agp_via_resume,
560#endif
561};
562
563
564static int __init agp_via_init(void)
565{
566	if (agp_off)
567		return -EINVAL;
568	return pci_register_driver(&agp_via_pci_driver);
569}
570
571static void __exit agp_via_cleanup(void)
572{
573	pci_unregister_driver(&agp_via_pci_driver);
574}
575
576module_init(agp_via_init);
577module_exit(agp_via_cleanup);
578
579MODULE_LICENSE("GPL");
580MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
581