1/* 2 * UniNorth AGPGART routines. 3 */ 4#include <linux/module.h> 5#include <linux/pci.h> 6#include <linux/init.h> 7#include <linux/pagemap.h> 8#include <linux/agp_backend.h> 9#include <linux/delay.h> 10#include <asm/uninorth.h> 11#include <asm/pci-bridge.h> 12#include <asm/prom.h> 13#include <asm/pmac_feature.h> 14#include "agp.h" 15 16/* 17 * NOTES for uninorth3 (G5 AGP) supports : 18 * 19 * There maybe also possibility to have bigger cache line size for 20 * agp (see pmac_pci.c and look for cache line). Need to be investigated 21 * by someone. 22 * 23 * PAGE size are hardcoded but this may change, see asm/page.h. 24 * 25 * Jerome Glisse <j.glisse@gmail.com> 26 */ 27static int uninorth_rev; 28static int is_u3; 29 30static char __devinitdata *aperture = NULL; 31 32static int uninorth_fetch_size(void) 33{ 34 int i, size = 0; 35 struct aper_size_info_32 *values = 36 A_SIZE_32(agp_bridge->driver->aperture_sizes); 37 38 if (aperture) { 39 char *save = aperture; 40 41 size = memparse(aperture, &aperture) >> 20; 42 aperture = save; 43 44 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) 45 if (size == values[i].size) 46 break; 47 48 if (i == agp_bridge->driver->num_aperture_sizes) { 49 printk(KERN_ERR PFX "Invalid aperture size, using" 50 " default\n"); 51 size = 0; 52 aperture = NULL; 53 } 54 } 55 56 if (!size) { 57 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) 58 if (values[i].size == 32) 59 break; 60 } 61 62 agp_bridge->previous_size = 63 agp_bridge->current_size = (void *)(values + i); 64 agp_bridge->aperture_size_idx = i; 65 return values[i].size; 66} 67 68static void uninorth_tlbflush(struct agp_memory *mem) 69{ 70 u32 ctrl = UNI_N_CFG_GART_ENABLE; 71 72 if (is_u3) 73 ctrl |= U3_N_CFG_GART_PERFRD; 74 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 75 ctrl | UNI_N_CFG_GART_INVAL); 76 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl); 77 78 if (uninorth_rev <= 0x30) { 79 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 80 ctrl | UNI_N_CFG_GART_2xRESET); 81 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 82 ctrl); 83 } 84} 85 86static void uninorth_cleanup(void) 87{ 88 u32 tmp; 89 90 pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp); 91 if (!(tmp & UNI_N_CFG_GART_ENABLE)) 92 return; 93 tmp |= UNI_N_CFG_GART_INVAL; 94 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp); 95 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0); 96 97 if (uninorth_rev <= 0x30) { 98 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 99 UNI_N_CFG_GART_2xRESET); 100 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 101 0); 102 } 103} 104 105static int uninorth_configure(void) 106{ 107 struct aper_size_info_32 *current_size; 108 109 current_size = A_SIZE_32(agp_bridge->current_size); 110 111 printk(KERN_INFO PFX "configuring for size idx: %d\n", 112 current_size->size_value); 113 114 /* aperture size and gatt addr */ 115 pci_write_config_dword(agp_bridge->dev, 116 UNI_N_CFG_GART_BASE, 117 (agp_bridge->gatt_bus_addr & 0xfffff000) 118 | current_size->size_value); 119 120 /* HACK ALERT 121 * UniNorth seem to be buggy enough not to handle properly when 122 * the AGP aperture isn't mapped at bus physical address 0 123 */ 124 agp_bridge->gart_bus_addr = 0; 125#ifdef CONFIG_PPC64 126 /* Assume U3 or later on PPC64 systems */ 127 /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */ 128 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE, 129 (agp_bridge->gatt_bus_addr >> 32) & 0xf); 130#else 131 pci_write_config_dword(agp_bridge->dev, 132 UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr); 133#endif 134 135 if (is_u3) { 136 pci_write_config_dword(agp_bridge->dev, 137 UNI_N_CFG_GART_DUMMY_PAGE, 138 agp_bridge->scratch_page_real >> 12); 139 } 140 141 return 0; 142} 143 144static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, 145 int type) 146{ 147 int i, j, num_entries; 148 void *temp; 149 150 temp = agp_bridge->current_size; 151 num_entries = A_SIZE_32(temp)->num_entries; 152 153 if (type != 0 || mem->type != 0) 154 /* We know nothing of memory types */ 155 return -EINVAL; 156 if ((pg_start + mem->page_count) > num_entries) 157 return -EINVAL; 158 159 j = pg_start; 160 161 while (j < (pg_start + mem->page_count)) { 162 if (agp_bridge->gatt_table[j]) 163 return -EBUSY; 164 j++; 165 } 166 167 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 168 agp_bridge->gatt_table[j] = 169 cpu_to_le32((mem->memory[i] & 0xFFFFF000UL) | 0x1UL); 170 flush_dcache_range((unsigned long)__va(mem->memory[i]), 171 (unsigned long)__va(mem->memory[i])+0x1000); 172 } 173 (void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]); 174 mb(); 175 flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start], 176 (unsigned long)&agp_bridge->gatt_table[pg_start + mem->page_count]); 177 178 uninorth_tlbflush(mem); 179 return 0; 180} 181 182static int u3_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 183{ 184 int i, num_entries; 185 void *temp; 186 u32 *gp; 187 188 temp = agp_bridge->current_size; 189 num_entries = A_SIZE_32(temp)->num_entries; 190 191 if (type != 0 || mem->type != 0) 192 /* We know nothing of memory types */ 193 return -EINVAL; 194 if ((pg_start + mem->page_count) > num_entries) 195 return -EINVAL; 196 197 gp = (u32 *) &agp_bridge->gatt_table[pg_start]; 198 for (i = 0; i < mem->page_count; ++i) { 199 if (gp[i]) { 200 printk("u3_insert_memory: entry 0x%x occupied (%x)\n", 201 i, gp[i]); 202 return -EBUSY; 203 } 204 } 205 206 for (i = 0; i < mem->page_count; i++) { 207 gp[i] = (mem->memory[i] >> PAGE_SHIFT) | 0x80000000UL; 208 flush_dcache_range((unsigned long)__va(mem->memory[i]), 209 (unsigned long)__va(mem->memory[i])+0x1000); 210 } 211 mb(); 212 flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]); 213 uninorth_tlbflush(mem); 214 215 return 0; 216} 217 218int u3_remove_memory(struct agp_memory *mem, off_t pg_start, int type) 219{ 220 size_t i; 221 u32 *gp; 222 223 if (type != 0 || mem->type != 0) 224 /* We know nothing of memory types */ 225 return -EINVAL; 226 227 gp = (u32 *) &agp_bridge->gatt_table[pg_start]; 228 for (i = 0; i < mem->page_count; ++i) 229 gp[i] = 0; 230 mb(); 231 flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]); 232 uninorth_tlbflush(mem); 233 234 return 0; 235} 236 237static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode) 238{ 239 u32 command, scratch, status; 240 int timeout; 241 242 pci_read_config_dword(bridge->dev, 243 bridge->capndx + PCI_AGP_STATUS, 244 &status); 245 246 command = agp_collect_device_status(bridge, mode, status); 247 command |= PCI_AGP_COMMAND_AGP; 248 249 if (uninorth_rev == 0x21) { 250 /* 251 * Darwin disable AGP 4x on this revision, thus we 252 * may assume it's broken. This is an AGP2 controller. 253 */ 254 command &= ~AGPSTAT2_4X; 255 } 256 257 if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) { 258 /* 259 * We need to to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1, 260 * 2.2 and 2.3, Darwin do so. 261 */ 262 if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7) 263 command = (command & ~AGPSTAT_RQ_DEPTH) 264 | (7 << AGPSTAT_RQ_DEPTH_SHIFT); 265 } 266 267 uninorth_tlbflush(NULL); 268 269 timeout = 0; 270 do { 271 pci_write_config_dword(bridge->dev, 272 bridge->capndx + PCI_AGP_COMMAND, 273 command); 274 pci_read_config_dword(bridge->dev, 275 bridge->capndx + PCI_AGP_COMMAND, 276 &scratch); 277 } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000); 278 if ((scratch & PCI_AGP_COMMAND_AGP) == 0) 279 printk(KERN_ERR PFX "failed to write UniNorth AGP" 280 " command register\n"); 281 282 if (uninorth_rev >= 0x30) { 283 /* This is an AGP V3 */ 284 agp_device_command(command, (status & AGPSTAT_MODE_3_0)); 285 } else { 286 /* AGP V2 */ 287 agp_device_command(command, 0); 288 } 289 290 uninorth_tlbflush(NULL); 291} 292 293#ifdef CONFIG_PM 294/* 295 * These Power Management routines are _not_ called by the normal PCI PM layer, 296 * but directly by the video driver through function pointers in the device 297 * tree. 298 */ 299static int agp_uninorth_suspend(struct pci_dev *pdev) 300{ 301 struct agp_bridge_data *bridge; 302 u32 cmd; 303 u8 agp; 304 struct pci_dev *device = NULL; 305 306 bridge = agp_find_bridge(pdev); 307 if (bridge == NULL) 308 return -ENODEV; 309 310 /* Only one suspend supported */ 311 if (bridge->dev_private_data) 312 return 0; 313 314 /* turn off AGP on the video chip, if it was enabled */ 315 for_each_pci_dev(device) { 316 /* Don't touch the bridge yet, device first */ 317 if (device == pdev) 318 continue; 319 /* Only deal with devices on the same bus here, no Mac has a P2P 320 * bridge on the AGP port, and mucking around the entire PCI 321 * tree is source of problems on some machines because of a bug 322 * in some versions of pci_find_capability() when hitting a dead 323 * device 324 */ 325 if (device->bus != pdev->bus) 326 continue; 327 agp = pci_find_capability(device, PCI_CAP_ID_AGP); 328 if (!agp) 329 continue; 330 pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd); 331 if (!(cmd & PCI_AGP_COMMAND_AGP)) 332 continue; 333 printk("uninorth-agp: disabling AGP on device %s\n", 334 pci_name(device)); 335 cmd &= ~PCI_AGP_COMMAND_AGP; 336 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd); 337 } 338 339 /* turn off AGP on the bridge */ 340 agp = pci_find_capability(pdev, PCI_CAP_ID_AGP); 341 pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd); 342 bridge->dev_private_data = (void *)(long)cmd; 343 if (cmd & PCI_AGP_COMMAND_AGP) { 344 printk("uninorth-agp: disabling AGP on bridge %s\n", 345 pci_name(pdev)); 346 cmd &= ~PCI_AGP_COMMAND_AGP; 347 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd); 348 } 349 /* turn off the GART */ 350 uninorth_cleanup(); 351 352 return 0; 353} 354 355static int agp_uninorth_resume(struct pci_dev *pdev) 356{ 357 struct agp_bridge_data *bridge; 358 u32 command; 359 360 bridge = agp_find_bridge(pdev); 361 if (bridge == NULL) 362 return -ENODEV; 363 364 command = (long)bridge->dev_private_data; 365 bridge->dev_private_data = NULL; 366 if (!(command & PCI_AGP_COMMAND_AGP)) 367 return 0; 368 369 uninorth_agp_enable(bridge, command); 370 371 return 0; 372} 373#endif /* CONFIG_PM */ 374 375static int uninorth_create_gatt_table(struct agp_bridge_data *bridge) 376{ 377 char *table; 378 char *table_end; 379 int size; 380 int page_order; 381 int num_entries; 382 int i; 383 void *temp; 384 struct page *page; 385 386 /* We can't handle 2 level gatt's */ 387 if (bridge->driver->size_type == LVL2_APER_SIZE) 388 return -EINVAL; 389 390 table = NULL; 391 i = bridge->aperture_size_idx; 392 temp = bridge->current_size; 393 size = page_order = num_entries = 0; 394 395 do { 396 size = A_SIZE_32(temp)->size; 397 page_order = A_SIZE_32(temp)->page_order; 398 num_entries = A_SIZE_32(temp)->num_entries; 399 400 table = (char *) __get_free_pages(GFP_KERNEL, page_order); 401 402 if (table == NULL) { 403 i++; 404 bridge->current_size = A_IDX32(bridge); 405 } else { 406 bridge->aperture_size_idx = i; 407 } 408 } while (!table && (i < bridge->driver->num_aperture_sizes)); 409 410 if (table == NULL) 411 return -ENOMEM; 412 413 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); 414 415 for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) 416 SetPageReserved(page); 417 418 bridge->gatt_table_real = (u32 *) table; 419 bridge->gatt_table = (u32 *)table; 420 bridge->gatt_bus_addr = virt_to_gart(table); 421 422 for (i = 0; i < num_entries; i++) 423 bridge->gatt_table[i] = 0; 424 425 flush_dcache_range((unsigned long)table, (unsigned long)table_end); 426 427 return 0; 428} 429 430static int uninorth_free_gatt_table(struct agp_bridge_data *bridge) 431{ 432 int page_order; 433 char *table, *table_end; 434 void *temp; 435 struct page *page; 436 437 temp = bridge->current_size; 438 page_order = A_SIZE_32(temp)->page_order; 439 440 /* Do not worry about freeing memory, because if this is 441 * called, then all agp memory is deallocated and removed 442 * from the table. 443 */ 444 445 table = (char *) bridge->gatt_table_real; 446 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); 447 448 for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) 449 ClearPageReserved(page); 450 451 free_pages((unsigned long) bridge->gatt_table_real, page_order); 452 453 return 0; 454} 455 456void null_cache_flush(void) 457{ 458 mb(); 459} 460 461/* Setup function */ 462 463static const struct aper_size_info_32 uninorth_sizes[7] = 464{ 465 {32, 8192, 3, 8}, 466 {16, 4096, 2, 4}, 467 {8, 2048, 1, 2}, 468 {4, 1024, 0, 1} 469}; 470 471/* 472 * Not sure that u3 supports that high aperture sizes but it 473 * would strange if it did not :) 474 */ 475static const struct aper_size_info_32 u3_sizes[8] = 476{ 477 {512, 131072, 7, 128}, 478 {256, 65536, 6, 64}, 479 {128, 32768, 5, 32}, 480 {64, 16384, 4, 16}, 481 {32, 8192, 3, 8}, 482 {16, 4096, 2, 4}, 483 {8, 2048, 1, 2}, 484 {4, 1024, 0, 1} 485}; 486 487const struct agp_bridge_driver uninorth_agp_driver = { 488 .owner = THIS_MODULE, 489 .aperture_sizes = (void *)uninorth_sizes, 490 .size_type = U32_APER_SIZE, 491 .num_aperture_sizes = 4, 492 .configure = uninorth_configure, 493 .fetch_size = uninorth_fetch_size, 494 .cleanup = uninorth_cleanup, 495 .tlb_flush = uninorth_tlbflush, 496 .mask_memory = agp_generic_mask_memory, 497 .masks = NULL, 498 .cache_flush = null_cache_flush, 499 .agp_enable = uninorth_agp_enable, 500 .create_gatt_table = uninorth_create_gatt_table, 501 .free_gatt_table = uninorth_free_gatt_table, 502 .insert_memory = uninorth_insert_memory, 503 .remove_memory = agp_generic_remove_memory, 504 .alloc_by_type = agp_generic_alloc_by_type, 505 .free_by_type = agp_generic_free_by_type, 506 .agp_alloc_page = agp_generic_alloc_page, 507 .agp_destroy_page = agp_generic_destroy_page, 508 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 509 .cant_use_aperture = 1, 510}; 511 512const struct agp_bridge_driver u3_agp_driver = { 513 .owner = THIS_MODULE, 514 .aperture_sizes = (void *)u3_sizes, 515 .size_type = U32_APER_SIZE, 516 .num_aperture_sizes = 8, 517 .configure = uninorth_configure, 518 .fetch_size = uninorth_fetch_size, 519 .cleanup = uninorth_cleanup, 520 .tlb_flush = uninorth_tlbflush, 521 .mask_memory = agp_generic_mask_memory, 522 .masks = NULL, 523 .cache_flush = null_cache_flush, 524 .agp_enable = uninorth_agp_enable, 525 .create_gatt_table = uninorth_create_gatt_table, 526 .free_gatt_table = uninorth_free_gatt_table, 527 .insert_memory = u3_insert_memory, 528 .remove_memory = u3_remove_memory, 529 .alloc_by_type = agp_generic_alloc_by_type, 530 .free_by_type = agp_generic_free_by_type, 531 .agp_alloc_page = agp_generic_alloc_page, 532 .agp_destroy_page = agp_generic_destroy_page, 533 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 534 .cant_use_aperture = 1, 535 .needs_scratch_page = 1, 536}; 537 538static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = { 539 { 540 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP, 541 .chipset_name = "UniNorth", 542 }, 543 { 544 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P, 545 .chipset_name = "UniNorth/Pangea", 546 }, 547 { 548 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP15, 549 .chipset_name = "UniNorth 1.5", 550 }, 551 { 552 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2, 553 .chipset_name = "UniNorth 2", 554 }, 555 { 556 .device_id = PCI_DEVICE_ID_APPLE_U3_AGP, 557 .chipset_name = "U3", 558 }, 559 { 560 .device_id = PCI_DEVICE_ID_APPLE_U3L_AGP, 561 .chipset_name = "U3L", 562 }, 563 { 564 .device_id = PCI_DEVICE_ID_APPLE_U3H_AGP, 565 .chipset_name = "U3H", 566 }, 567 { 568 .device_id = PCI_DEVICE_ID_APPLE_IPID2_AGP, 569 .chipset_name = "UniNorth/Intrepid2", 570 }, 571}; 572 573static int __devinit agp_uninorth_probe(struct pci_dev *pdev, 574 const struct pci_device_id *ent) 575{ 576 struct agp_device_ids *devs = uninorth_agp_device_ids; 577 struct agp_bridge_data *bridge; 578 struct device_node *uninorth_node; 579 u8 cap_ptr; 580 int j; 581 582 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 583 if (cap_ptr == 0) 584 return -ENODEV; 585 586 /* probe for known chipsets */ 587 for (j = 0; devs[j].chipset_name != NULL; ++j) { 588 if (pdev->device == devs[j].device_id) { 589 printk(KERN_INFO PFX "Detected Apple %s chipset\n", 590 devs[j].chipset_name); 591 goto found; 592 } 593 } 594 595 printk(KERN_ERR PFX "Unsupported Apple chipset (device id: %04x).\n", 596 pdev->device); 597 return -ENODEV; 598 599 found: 600 /* Set revision to 0 if we could not read it. */ 601 uninorth_rev = 0; 602 is_u3 = 0; 603 /* Locate core99 Uni-N */ 604 uninorth_node = of_find_node_by_name(NULL, "uni-n"); 605 /* Locate G5 u3 */ 606 if (uninorth_node == NULL) { 607 is_u3 = 1; 608 uninorth_node = of_find_node_by_name(NULL, "u3"); 609 } 610 if (uninorth_node) { 611 const int *revprop = of_get_property(uninorth_node, 612 "device-rev", NULL); 613 if (revprop != NULL) 614 uninorth_rev = *revprop & 0x3f; 615 of_node_put(uninorth_node); 616 } 617 618#ifdef CONFIG_PM 619 /* Inform platform of our suspend/resume caps */ 620 pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume); 621#endif 622 623 /* Allocate & setup our driver */ 624 bridge = agp_alloc_bridge(); 625 if (!bridge) 626 return -ENOMEM; 627 628 if (is_u3) 629 bridge->driver = &u3_agp_driver; 630 else 631 bridge->driver = &uninorth_agp_driver; 632 633 bridge->dev = pdev; 634 bridge->capndx = cap_ptr; 635 bridge->flags = AGP_ERRATA_FASTWRITES; 636 637 /* Fill in the mode register */ 638 pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode); 639 640 pci_set_drvdata(pdev, bridge); 641 return agp_add_bridge(bridge); 642} 643 644static void __devexit agp_uninorth_remove(struct pci_dev *pdev) 645{ 646 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 647 648#ifdef CONFIG_PM 649 /* Inform platform of our suspend/resume caps */ 650 pmac_register_agp_pm(pdev, NULL, NULL); 651#endif 652 653 agp_remove_bridge(bridge); 654 agp_put_bridge(bridge); 655} 656 657static struct pci_device_id agp_uninorth_pci_table[] = { 658 { 659 .class = (PCI_CLASS_BRIDGE_HOST << 8), 660 .class_mask = ~0, 661 .vendor = PCI_VENDOR_ID_APPLE, 662 .device = PCI_ANY_ID, 663 .subvendor = PCI_ANY_ID, 664 .subdevice = PCI_ANY_ID, 665 }, 666 { } 667}; 668 669MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table); 670 671static struct pci_driver agp_uninorth_pci_driver = { 672 .name = "agpgart-uninorth", 673 .id_table = agp_uninorth_pci_table, 674 .probe = agp_uninorth_probe, 675 .remove = agp_uninorth_remove, 676}; 677 678static int __init agp_uninorth_init(void) 679{ 680 if (agp_off) 681 return -EINVAL; 682 return pci_register_driver(&agp_uninorth_pci_driver); 683} 684 685static void __exit agp_uninorth_cleanup(void) 686{ 687 pci_unregister_driver(&agp_uninorth_pci_driver); 688} 689 690module_init(agp_uninorth_init); 691module_exit(agp_uninorth_cleanup); 692 693module_param(aperture, charp, 0); 694MODULE_PARM_DESC(aperture, 695 "Aperture size, must be power of two between 4MB and an\n" 696 "\t\tupper limit specific to the UniNorth revision.\n" 697 "\t\tDefault: 32M"); 698 699MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras"); 700MODULE_LICENSE("GPL"); 701