1/* 2 * sx8.c: Driver for Promise SATA SX8 looks-like-I2O hardware 3 * 4 * Copyright 2004-2005 Red Hat, Inc. 5 * 6 * Author/maintainer: Jeff Garzik <jgarzik@pobox.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/init.h> 16#include <linux/pci.h> 17#include <linux/slab.h> 18#include <linux/spinlock.h> 19#include <linux/blkdev.h> 20#include <linux/sched.h> 21#include <linux/interrupt.h> 22#include <linux/compiler.h> 23#include <linux/workqueue.h> 24#include <linux/bitops.h> 25#include <linux/delay.h> 26#include <linux/time.h> 27#include <linux/hdreg.h> 28#include <linux/dma-mapping.h> 29#include <linux/completion.h> 30#include <asm/io.h> 31#include <asm/uaccess.h> 32 33#undef CARM_DEBUG 34#undef CARM_VERBOSE_DEBUG 35#undef CARM_NDEBUG 36 37#define DRV_NAME "sx8" 38#define DRV_VERSION "1.0" 39#define PFX DRV_NAME ": " 40 41MODULE_AUTHOR("Jeff Garzik"); 42MODULE_LICENSE("GPL"); 43MODULE_DESCRIPTION("Promise SATA SX8 block driver"); 44MODULE_VERSION(DRV_VERSION); 45 46/* 47 * SX8 hardware has a single message queue for all ATA ports. 48 * When this driver was written, the hardware (firmware?) would 49 * corrupt data eventually, if more than one request was outstanding. 50 * As one can imagine, having 8 ports bottlenecking on a single 51 * command hurts performance. 52 * 53 * Based on user reports, later versions of the hardware (firmware?) 54 * seem to be able to survive with more than one command queued. 55 * 56 * Therefore, we default to the safe option -- 1 command -- but 57 * allow the user to increase this. 58 * 59 * SX8 should be able to support up to ~60 queued commands (CARM_MAX_REQ), 60 * but problems seem to occur when you exceed ~30, even on newer hardware. 61 */ 62static int max_queue = 1; 63module_param(max_queue, int, 0444); 64MODULE_PARM_DESC(max_queue, "Maximum number of queued commands. (min==1, max==30, safe==1)"); 65 66 67#define NEXT_RESP(idx) ((idx + 1) % RMSG_Q_LEN) 68 69/* 0xf is just arbitrary, non-zero noise; this is sorta like poisoning */ 70#define TAG_ENCODE(tag) (((tag) << 16) | 0xf) 71#define TAG_DECODE(tag) (((tag) >> 16) & 0x1f) 72#define TAG_VALID(tag) ((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32)) 73 74/* note: prints function name for you */ 75#ifdef CARM_DEBUG 76#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) 77#ifdef CARM_VERBOSE_DEBUG 78#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) 79#else 80#define VPRINTK(fmt, args...) 81#endif /* CARM_VERBOSE_DEBUG */ 82#else 83#define DPRINTK(fmt, args...) 84#define VPRINTK(fmt, args...) 85#endif /* CARM_DEBUG */ 86 87#ifdef CARM_NDEBUG 88#define assert(expr) 89#else 90#define assert(expr) \ 91 if(unlikely(!(expr))) { \ 92 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \ 93 #expr,__FILE__,__FUNCTION__,__LINE__); \ 94 } 95#endif 96 97/* defines only for the constants which don't work well as enums */ 98struct carm_host; 99 100enum { 101 /* adapter-wide limits */ 102 CARM_MAX_PORTS = 8, 103 CARM_SHM_SIZE = (4096 << 7), 104 CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS, 105 CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1, 106 107 /* command message queue limits */ 108 CARM_MAX_REQ = 64, /* max command msgs per host */ 109 CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4), /* refill mark */ 110 111 /* S/G limits, host-wide and per-request */ 112 CARM_MAX_REQ_SG = 32, /* max s/g entries per request */ 113 CARM_MAX_HOST_SG = 600, /* max s/g entries per host */ 114 CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4), /* re-fill mark */ 115 116 /* hardware registers */ 117 CARM_IHQP = 0x1c, 118 CARM_INT_STAT = 0x10, /* interrupt status */ 119 CARM_INT_MASK = 0x14, /* interrupt mask */ 120 CARM_HMUC = 0x18, /* host message unit control */ 121 RBUF_ADDR_LO = 0x20, /* response msg DMA buf low 32 bits */ 122 RBUF_ADDR_HI = 0x24, /* response msg DMA buf high 32 bits */ 123 RBUF_BYTE_SZ = 0x28, 124 CARM_RESP_IDX = 0x2c, 125 CARM_CMS0 = 0x30, /* command message size reg 0 */ 126 CARM_LMUC = 0x48, 127 CARM_HMPHA = 0x6c, 128 CARM_INITC = 0xb5, 129 130 /* bits in CARM_INT_{STAT,MASK} */ 131 INT_RESERVED = 0xfffffff0, 132 INT_WATCHDOG = (1 << 3), /* watchdog timer */ 133 INT_Q_OVERFLOW = (1 << 2), /* cmd msg q overflow */ 134 INT_Q_AVAILABLE = (1 << 1), /* cmd msg q has free space */ 135 INT_RESPONSE = (1 << 0), /* response msg available */ 136 INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW, 137 INT_DEF_MASK = INT_RESERVED | INT_Q_OVERFLOW | 138 INT_RESPONSE, 139 140 /* command messages, and related register bits */ 141 CARM_HAVE_RESP = 0x01, 142 CARM_MSG_READ = 1, 143 CARM_MSG_WRITE = 2, 144 CARM_MSG_VERIFY = 3, 145 CARM_MSG_GET_CAPACITY = 4, 146 CARM_MSG_FLUSH = 5, 147 CARM_MSG_IOCTL = 6, 148 CARM_MSG_ARRAY = 8, 149 CARM_MSG_MISC = 9, 150 CARM_CME = (1 << 2), 151 CARM_RME = (1 << 1), 152 CARM_WZBC = (1 << 0), 153 CARM_RMI = (1 << 0), 154 CARM_Q_FULL = (1 << 3), 155 CARM_MSG_SIZE = 288, 156 CARM_Q_LEN = 48, 157 158 /* CARM_MSG_IOCTL messages */ 159 CARM_IOC_SCAN_CHAN = 5, /* scan channels for devices */ 160 CARM_IOC_GET_TCQ = 13, /* get tcq/ncq depth */ 161 CARM_IOC_SET_TCQ = 14, /* set tcq/ncq depth */ 162 163 IOC_SCAN_CHAN_NODEV = 0x1f, 164 IOC_SCAN_CHAN_OFFSET = 0x40, 165 166 /* CARM_MSG_ARRAY messages */ 167 CARM_ARRAY_INFO = 0, 168 169 ARRAY_NO_EXIST = (1 << 31), 170 171 /* response messages */ 172 RMSG_SZ = 8, /* sizeof(struct carm_response) */ 173 RMSG_Q_LEN = 48, /* resp. msg list length */ 174 RMSG_OK = 1, /* bit indicating msg was successful */ 175 /* length of entire resp. msg buffer */ 176 RBUF_LEN = RMSG_SZ * RMSG_Q_LEN, 177 178 PDC_SHM_SIZE = (4096 << 7), /* length of entire h/w buffer */ 179 180 /* CARM_MSG_MISC messages */ 181 MISC_GET_FW_VER = 2, 182 MISC_ALLOC_MEM = 3, 183 MISC_SET_TIME = 5, 184 185 /* MISC_GET_FW_VER feature bits */ 186 FW_VER_4PORT = (1 << 2), /* 1=4 ports, 0=8 ports */ 187 FW_VER_NON_RAID = (1 << 1), /* 1=non-RAID firmware, 0=RAID */ 188 FW_VER_ZCR = (1 << 0), /* zero channel RAID (whatever that is) */ 189 190 /* carm_host flags */ 191 FL_NON_RAID = FW_VER_NON_RAID, 192 FL_4PORT = FW_VER_4PORT, 193 FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT), 194 FL_DAC = (1 << 16), 195 FL_DYN_MAJOR = (1 << 17), 196}; 197 198enum { 199 CARM_SG_BOUNDARY = 0xffffUL, /* s/g segment boundary */ 200}; 201 202enum scatter_gather_types { 203 SGT_32BIT = 0, 204 SGT_64BIT = 1, 205}; 206 207enum host_states { 208 HST_INVALID, /* invalid state; never used */ 209 HST_ALLOC_BUF, /* setting up master SHM area */ 210 HST_ERROR, /* we never leave here */ 211 HST_PORT_SCAN, /* start dev scan */ 212 HST_DEV_SCAN_START, /* start per-device probe */ 213 HST_DEV_SCAN, /* continue per-device probe */ 214 HST_DEV_ACTIVATE, /* activate devices we found */ 215 HST_PROBE_FINISHED, /* probe is complete */ 216 HST_PROBE_START, /* initiate probe */ 217 HST_SYNC_TIME, /* tell firmware what time it is */ 218 HST_GET_FW_VER, /* get firmware version, adapter port cnt */ 219}; 220 221#ifdef CARM_DEBUG 222static const char *state_name[] = { 223 "HST_INVALID", 224 "HST_ALLOC_BUF", 225 "HST_ERROR", 226 "HST_PORT_SCAN", 227 "HST_DEV_SCAN_START", 228 "HST_DEV_SCAN", 229 "HST_DEV_ACTIVATE", 230 "HST_PROBE_FINISHED", 231 "HST_PROBE_START", 232 "HST_SYNC_TIME", 233 "HST_GET_FW_VER", 234}; 235#endif 236 237struct carm_port { 238 unsigned int port_no; 239 struct gendisk *disk; 240 struct carm_host *host; 241 242 /* attached device characteristics */ 243 u64 capacity; 244 char name[41]; 245 u16 dev_geom_head; 246 u16 dev_geom_sect; 247 u16 dev_geom_cyl; 248}; 249 250struct carm_request { 251 unsigned int tag; 252 int n_elem; 253 unsigned int msg_type; 254 unsigned int msg_subtype; 255 unsigned int msg_bucket; 256 struct request *rq; 257 struct carm_port *port; 258 struct scatterlist sg[CARM_MAX_REQ_SG]; 259}; 260 261struct carm_host { 262 unsigned long flags; 263 void __iomem *mmio; 264 void *shm; 265 dma_addr_t shm_dma; 266 267 int major; 268 int id; 269 char name[32]; 270 271 spinlock_t lock; 272 struct pci_dev *pdev; 273 unsigned int state; 274 u32 fw_ver; 275 276 request_queue_t *oob_q; 277 unsigned int n_oob; 278 279 unsigned int hw_sg_used; 280 281 unsigned int resp_idx; 282 283 unsigned int wait_q_prod; 284 unsigned int wait_q_cons; 285 request_queue_t *wait_q[CARM_MAX_WAIT_Q]; 286 287 unsigned int n_msgs; 288 u64 msg_alloc; 289 struct carm_request req[CARM_MAX_REQ]; 290 void *msg_base; 291 dma_addr_t msg_dma; 292 293 int cur_scan_dev; 294 unsigned long dev_active; 295 unsigned long dev_present; 296 struct carm_port port[CARM_MAX_PORTS]; 297 298 struct work_struct fsm_task; 299 300 struct completion probe_comp; 301}; 302 303struct carm_response { 304 __le32 ret_handle; 305 __le32 status; 306} __attribute__((packed)); 307 308struct carm_msg_sg { 309 __le32 start; 310 __le32 len; 311} __attribute__((packed)); 312 313struct carm_msg_rw { 314 u8 type; 315 u8 id; 316 u8 sg_count; 317 u8 sg_type; 318 __le32 handle; 319 __le32 lba; 320 __le16 lba_count; 321 __le16 lba_high; 322 struct carm_msg_sg sg[32]; 323} __attribute__((packed)); 324 325struct carm_msg_allocbuf { 326 u8 type; 327 u8 subtype; 328 u8 n_sg; 329 u8 sg_type; 330 __le32 handle; 331 __le32 addr; 332 __le32 len; 333 __le32 evt_pool; 334 __le32 n_evt; 335 __le32 rbuf_pool; 336 __le32 n_rbuf; 337 __le32 msg_pool; 338 __le32 n_msg; 339 struct carm_msg_sg sg[8]; 340} __attribute__((packed)); 341 342struct carm_msg_ioctl { 343 u8 type; 344 u8 subtype; 345 u8 array_id; 346 u8 reserved1; 347 __le32 handle; 348 __le32 data_addr; 349 u32 reserved2; 350} __attribute__((packed)); 351 352struct carm_msg_sync_time { 353 u8 type; 354 u8 subtype; 355 u16 reserved1; 356 __le32 handle; 357 u32 reserved2; 358 __le32 timestamp; 359} __attribute__((packed)); 360 361struct carm_msg_get_fw_ver { 362 u8 type; 363 u8 subtype; 364 u16 reserved1; 365 __le32 handle; 366 __le32 data_addr; 367 u32 reserved2; 368} __attribute__((packed)); 369 370struct carm_fw_ver { 371 __le32 version; 372 u8 features; 373 u8 reserved1; 374 u16 reserved2; 375} __attribute__((packed)); 376 377struct carm_array_info { 378 __le32 size; 379 380 __le16 size_hi; 381 __le16 stripe_size; 382 383 __le32 mode; 384 385 __le16 stripe_blk_sz; 386 __le16 reserved1; 387 388 __le16 cyl; 389 __le16 head; 390 391 __le16 sect; 392 u8 array_id; 393 u8 reserved2; 394 395 char name[40]; 396 397 __le32 array_status; 398 399 /* device list continues beyond this point? */ 400} __attribute__((packed)); 401 402static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 403static void carm_remove_one (struct pci_dev *pdev); 404static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo); 405 406static struct pci_device_id carm_pci_tbl[] = { 407 { PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, 408 { PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, 409 { } /* terminate list */ 410}; 411MODULE_DEVICE_TABLE(pci, carm_pci_tbl); 412 413static struct pci_driver carm_driver = { 414 .name = DRV_NAME, 415 .id_table = carm_pci_tbl, 416 .probe = carm_init_one, 417 .remove = carm_remove_one, 418}; 419 420static struct block_device_operations carm_bd_ops = { 421 .owner = THIS_MODULE, 422 .getgeo = carm_bdev_getgeo, 423}; 424 425static unsigned int carm_host_id; 426static unsigned long carm_major_alloc; 427 428 429 430static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo) 431{ 432 struct carm_port *port = bdev->bd_disk->private_data; 433 434 geo->heads = (u8) port->dev_geom_head; 435 geo->sectors = (u8) port->dev_geom_sect; 436 geo->cylinders = port->dev_geom_cyl; 437 return 0; 438} 439 440static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE }; 441 442static inline int carm_lookup_bucket(u32 msg_size) 443{ 444 int i; 445 446 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++) 447 if (msg_size <= msg_sizes[i]) 448 return i; 449 450 return -ENOENT; 451} 452 453static void carm_init_buckets(void __iomem *mmio) 454{ 455 unsigned int i; 456 457 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++) 458 writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i)); 459} 460 461static inline void *carm_ref_msg(struct carm_host *host, 462 unsigned int msg_idx) 463{ 464 return host->msg_base + (msg_idx * CARM_MSG_SIZE); 465} 466 467static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host, 468 unsigned int msg_idx) 469{ 470 return host->msg_dma + (msg_idx * CARM_MSG_SIZE); 471} 472 473static int carm_send_msg(struct carm_host *host, 474 struct carm_request *crq) 475{ 476 void __iomem *mmio = host->mmio; 477 u32 msg = (u32) carm_ref_msg_dma(host, crq->tag); 478 u32 cm_bucket = crq->msg_bucket; 479 u32 tmp; 480 int rc = 0; 481 482 VPRINTK("ENTER\n"); 483 484 tmp = readl(mmio + CARM_HMUC); 485 if (tmp & CARM_Q_FULL) { 486 DPRINTK("host msg queue full\n"); 487 rc = -EBUSY; 488 } else { 489 writel(msg | (cm_bucket << 1), mmio + CARM_IHQP); 490 readl(mmio + CARM_IHQP); /* flush */ 491 } 492 493 return rc; 494} 495 496static struct carm_request *carm_get_request(struct carm_host *host) 497{ 498 unsigned int i; 499 500 /* obey global hardware limit on S/G entries */ 501 if (host->hw_sg_used >= (CARM_MAX_HOST_SG - CARM_MAX_REQ_SG)) 502 return NULL; 503 504 for (i = 0; i < max_queue; i++) 505 if ((host->msg_alloc & (1ULL << i)) == 0) { 506 struct carm_request *crq = &host->req[i]; 507 crq->port = NULL; 508 crq->n_elem = 0; 509 510 host->msg_alloc |= (1ULL << i); 511 host->n_msgs++; 512 513 assert(host->n_msgs <= CARM_MAX_REQ); 514 return crq; 515 } 516 517 DPRINTK("no request available, returning NULL\n"); 518 return NULL; 519} 520 521static int carm_put_request(struct carm_host *host, struct carm_request *crq) 522{ 523 assert(crq->tag < max_queue); 524 525 if (unlikely((host->msg_alloc & (1ULL << crq->tag)) == 0)) 526 return -EINVAL; /* tried to clear a tag that was not active */ 527 528 assert(host->hw_sg_used >= crq->n_elem); 529 530 host->msg_alloc &= ~(1ULL << crq->tag); 531 host->hw_sg_used -= crq->n_elem; 532 host->n_msgs--; 533 534 return 0; 535} 536 537static struct carm_request *carm_get_special(struct carm_host *host) 538{ 539 unsigned long flags; 540 struct carm_request *crq = NULL; 541 struct request *rq; 542 int tries = 5000; 543 544 while (tries-- > 0) { 545 spin_lock_irqsave(&host->lock, flags); 546 crq = carm_get_request(host); 547 spin_unlock_irqrestore(&host->lock, flags); 548 549 if (crq) 550 break; 551 msleep(10); 552 } 553 554 if (!crq) 555 return NULL; 556 557 rq = blk_get_request(host->oob_q, WRITE /* bogus */, GFP_KERNEL); 558 if (!rq) { 559 spin_lock_irqsave(&host->lock, flags); 560 carm_put_request(host, crq); 561 spin_unlock_irqrestore(&host->lock, flags); 562 return NULL; 563 } 564 565 crq->rq = rq; 566 return crq; 567} 568 569static int carm_array_info (struct carm_host *host, unsigned int array_idx) 570{ 571 struct carm_msg_ioctl *ioc; 572 unsigned int idx; 573 u32 msg_data; 574 dma_addr_t msg_dma; 575 struct carm_request *crq; 576 int rc; 577 578 crq = carm_get_special(host); 579 if (!crq) { 580 rc = -ENOMEM; 581 goto err_out; 582 } 583 584 idx = crq->tag; 585 586 ioc = carm_ref_msg(host, idx); 587 msg_dma = carm_ref_msg_dma(host, idx); 588 msg_data = (u32) (msg_dma + sizeof(struct carm_array_info)); 589 590 crq->msg_type = CARM_MSG_ARRAY; 591 crq->msg_subtype = CARM_ARRAY_INFO; 592 rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) + 593 sizeof(struct carm_array_info)); 594 BUG_ON(rc < 0); 595 crq->msg_bucket = (u32) rc; 596 597 memset(ioc, 0, sizeof(*ioc)); 598 ioc->type = CARM_MSG_ARRAY; 599 ioc->subtype = CARM_ARRAY_INFO; 600 ioc->array_id = (u8) array_idx; 601 ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); 602 ioc->data_addr = cpu_to_le32(msg_data); 603 604 spin_lock_irq(&host->lock); 605 assert(host->state == HST_DEV_SCAN_START || 606 host->state == HST_DEV_SCAN); 607 spin_unlock_irq(&host->lock); 608 609 DPRINTK("blk_insert_request, tag == %u\n", idx); 610 blk_insert_request(host->oob_q, crq->rq, 1, crq); 611 612 return 0; 613 614err_out: 615 spin_lock_irq(&host->lock); 616 host->state = HST_ERROR; 617 spin_unlock_irq(&host->lock); 618 return rc; 619} 620 621typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *); 622 623static int carm_send_special (struct carm_host *host, carm_sspc_t func) 624{ 625 struct carm_request *crq; 626 struct carm_msg_ioctl *ioc; 627 void *mem; 628 unsigned int idx, msg_size; 629 int rc; 630 631 crq = carm_get_special(host); 632 if (!crq) 633 return -ENOMEM; 634 635 idx = crq->tag; 636 637 mem = carm_ref_msg(host, idx); 638 639 msg_size = func(host, idx, mem); 640 641 ioc = mem; 642 crq->msg_type = ioc->type; 643 crq->msg_subtype = ioc->subtype; 644 rc = carm_lookup_bucket(msg_size); 645 BUG_ON(rc < 0); 646 crq->msg_bucket = (u32) rc; 647 648 DPRINTK("blk_insert_request, tag == %u\n", idx); 649 blk_insert_request(host->oob_q, crq->rq, 1, crq); 650 651 return 0; 652} 653 654static unsigned int carm_fill_sync_time(struct carm_host *host, 655 unsigned int idx, void *mem) 656{ 657 struct timeval tv; 658 struct carm_msg_sync_time *st = mem; 659 660 do_gettimeofday(&tv); 661 662 memset(st, 0, sizeof(*st)); 663 st->type = CARM_MSG_MISC; 664 st->subtype = MISC_SET_TIME; 665 st->handle = cpu_to_le32(TAG_ENCODE(idx)); 666 st->timestamp = cpu_to_le32(tv.tv_sec); 667 668 return sizeof(struct carm_msg_sync_time); 669} 670 671static unsigned int carm_fill_alloc_buf(struct carm_host *host, 672 unsigned int idx, void *mem) 673{ 674 struct carm_msg_allocbuf *ab = mem; 675 676 memset(ab, 0, sizeof(*ab)); 677 ab->type = CARM_MSG_MISC; 678 ab->subtype = MISC_ALLOC_MEM; 679 ab->handle = cpu_to_le32(TAG_ENCODE(idx)); 680 ab->n_sg = 1; 681 ab->sg_type = SGT_32BIT; 682 ab->addr = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1)); 683 ab->len = cpu_to_le32(PDC_SHM_SIZE >> 1); 684 ab->evt_pool = cpu_to_le32(host->shm_dma + (16 * 1024)); 685 ab->n_evt = cpu_to_le32(1024); 686 ab->rbuf_pool = cpu_to_le32(host->shm_dma); 687 ab->n_rbuf = cpu_to_le32(RMSG_Q_LEN); 688 ab->msg_pool = cpu_to_le32(host->shm_dma + RBUF_LEN); 689 ab->n_msg = cpu_to_le32(CARM_Q_LEN); 690 ab->sg[0].start = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1)); 691 ab->sg[0].len = cpu_to_le32(65536); 692 693 return sizeof(struct carm_msg_allocbuf); 694} 695 696static unsigned int carm_fill_scan_channels(struct carm_host *host, 697 unsigned int idx, void *mem) 698{ 699 struct carm_msg_ioctl *ioc = mem; 700 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + 701 IOC_SCAN_CHAN_OFFSET); 702 703 memset(ioc, 0, sizeof(*ioc)); 704 ioc->type = CARM_MSG_IOCTL; 705 ioc->subtype = CARM_IOC_SCAN_CHAN; 706 ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); 707 ioc->data_addr = cpu_to_le32(msg_data); 708 709 /* fill output data area with "no device" default values */ 710 mem += IOC_SCAN_CHAN_OFFSET; 711 memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS); 712 713 return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS; 714} 715 716static unsigned int carm_fill_get_fw_ver(struct carm_host *host, 717 unsigned int idx, void *mem) 718{ 719 struct carm_msg_get_fw_ver *ioc = mem; 720 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc)); 721 722 memset(ioc, 0, sizeof(*ioc)); 723 ioc->type = CARM_MSG_MISC; 724 ioc->subtype = MISC_GET_FW_VER; 725 ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); 726 ioc->data_addr = cpu_to_le32(msg_data); 727 728 return sizeof(struct carm_msg_get_fw_ver) + 729 sizeof(struct carm_fw_ver); 730} 731 732static inline void carm_end_request_queued(struct carm_host *host, 733 struct carm_request *crq, 734 int uptodate) 735{ 736 struct request *req = crq->rq; 737 int rc; 738 739 rc = end_that_request_first(req, uptodate, req->hard_nr_sectors); 740 assert(rc == 0); 741 742 end_that_request_last(req, uptodate); 743 744 rc = carm_put_request(host, crq); 745 assert(rc == 0); 746} 747 748static inline void carm_push_q (struct carm_host *host, request_queue_t *q) 749{ 750 unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q; 751 752 blk_stop_queue(q); 753 VPRINTK("STOPPED QUEUE %p\n", q); 754 755 host->wait_q[idx] = q; 756 host->wait_q_prod++; 757 BUG_ON(host->wait_q_prod == host->wait_q_cons); /* overrun */ 758} 759 760static inline request_queue_t *carm_pop_q(struct carm_host *host) 761{ 762 unsigned int idx; 763 764 if (host->wait_q_prod == host->wait_q_cons) 765 return NULL; 766 767 idx = host->wait_q_cons % CARM_MAX_WAIT_Q; 768 host->wait_q_cons++; 769 770 return host->wait_q[idx]; 771} 772 773static inline void carm_round_robin(struct carm_host *host) 774{ 775 request_queue_t *q = carm_pop_q(host); 776 if (q) { 777 blk_start_queue(q); 778 VPRINTK("STARTED QUEUE %p\n", q); 779 } 780} 781 782static inline void carm_end_rq(struct carm_host *host, struct carm_request *crq, 783 int is_ok) 784{ 785 carm_end_request_queued(host, crq, is_ok); 786 if (max_queue == 1) 787 carm_round_robin(host); 788 else if ((host->n_msgs <= CARM_MSG_LOW_WATER) && 789 (host->hw_sg_used <= CARM_SG_LOW_WATER)) { 790 carm_round_robin(host); 791 } 792} 793 794static void carm_oob_rq_fn(request_queue_t *q) 795{ 796 struct carm_host *host = q->queuedata; 797 struct carm_request *crq; 798 struct request *rq; 799 int rc; 800 801 while (1) { 802 DPRINTK("get req\n"); 803 rq = elv_next_request(q); 804 if (!rq) 805 break; 806 807 blkdev_dequeue_request(rq); 808 809 crq = rq->special; 810 assert(crq != NULL); 811 assert(crq->rq == rq); 812 813 crq->n_elem = 0; 814 815 DPRINTK("send req\n"); 816 rc = carm_send_msg(host, crq); 817 if (rc) { 818 blk_requeue_request(q, rq); 819 carm_push_q(host, q); 820 return; /* call us again later, eventually */ 821 } 822 } 823} 824 825static void carm_rq_fn(request_queue_t *q) 826{ 827 struct carm_port *port = q->queuedata; 828 struct carm_host *host = port->host; 829 struct carm_msg_rw *msg; 830 struct carm_request *crq; 831 struct request *rq; 832 struct scatterlist *sg; 833 int writing = 0, pci_dir, i, n_elem, rc; 834 u32 tmp; 835 unsigned int msg_size; 836 837queue_one_request: 838 VPRINTK("get req\n"); 839 rq = elv_next_request(q); 840 if (!rq) 841 return; 842 843 crq = carm_get_request(host); 844 if (!crq) { 845 carm_push_q(host, q); 846 return; /* call us again later, eventually */ 847 } 848 crq->rq = rq; 849 850 blkdev_dequeue_request(rq); 851 852 if (rq_data_dir(rq) == WRITE) { 853 writing = 1; 854 pci_dir = PCI_DMA_TODEVICE; 855 } else { 856 pci_dir = PCI_DMA_FROMDEVICE; 857 } 858 859 /* get scatterlist from block layer */ 860 sg = &crq->sg[0]; 861 n_elem = blk_rq_map_sg(q, rq, sg); 862 if (n_elem <= 0) { 863 carm_end_rq(host, crq, 0); 864 return; /* request with no s/g entries? */ 865 } 866 867 /* map scatterlist to PCI bus addresses */ 868 n_elem = pci_map_sg(host->pdev, sg, n_elem, pci_dir); 869 if (n_elem <= 0) { 870 carm_end_rq(host, crq, 0); 871 return; /* request with no s/g entries? */ 872 } 873 crq->n_elem = n_elem; 874 crq->port = port; 875 host->hw_sg_used += n_elem; 876 877 /* 878 * build read/write message 879 */ 880 881 VPRINTK("build msg\n"); 882 msg = (struct carm_msg_rw *) carm_ref_msg(host, crq->tag); 883 884 if (writing) { 885 msg->type = CARM_MSG_WRITE; 886 crq->msg_type = CARM_MSG_WRITE; 887 } else { 888 msg->type = CARM_MSG_READ; 889 crq->msg_type = CARM_MSG_READ; 890 } 891 892 msg->id = port->port_no; 893 msg->sg_count = n_elem; 894 msg->sg_type = SGT_32BIT; 895 msg->handle = cpu_to_le32(TAG_ENCODE(crq->tag)); 896 msg->lba = cpu_to_le32(rq->sector & 0xffffffff); 897 tmp = (rq->sector >> 16) >> 16; 898 msg->lba_high = cpu_to_le16( (u16) tmp ); 899 msg->lba_count = cpu_to_le16(rq->nr_sectors); 900 901 msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg); 902 for (i = 0; i < n_elem; i++) { 903 struct carm_msg_sg *carm_sg = &msg->sg[i]; 904 carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i])); 905 carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i])); 906 msg_size += sizeof(struct carm_msg_sg); 907 } 908 909 rc = carm_lookup_bucket(msg_size); 910 BUG_ON(rc < 0); 911 crq->msg_bucket = (u32) rc; 912 913 /* 914 * queue read/write message to hardware 915 */ 916 917 VPRINTK("send msg, tag == %u\n", crq->tag); 918 rc = carm_send_msg(host, crq); 919 if (rc) { 920 carm_put_request(host, crq); 921 blk_requeue_request(q, rq); 922 carm_push_q(host, q); 923 return; /* call us again later, eventually */ 924 } 925 926 goto queue_one_request; 927} 928 929static void carm_handle_array_info(struct carm_host *host, 930 struct carm_request *crq, u8 *mem, 931 int is_ok) 932{ 933 struct carm_port *port; 934 u8 *msg_data = mem + sizeof(struct carm_array_info); 935 struct carm_array_info *desc = (struct carm_array_info *) msg_data; 936 u64 lo, hi; 937 int cur_port; 938 size_t slen; 939 940 DPRINTK("ENTER\n"); 941 942 carm_end_rq(host, crq, is_ok); 943 944 if (!is_ok) 945 goto out; 946 if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST) 947 goto out; 948 949 cur_port = host->cur_scan_dev; 950 951 /* should never occur */ 952 if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) { 953 printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n", 954 cur_port, (int) desc->array_id); 955 goto out; 956 } 957 958 port = &host->port[cur_port]; 959 960 lo = (u64) le32_to_cpu(desc->size); 961 hi = (u64) le16_to_cpu(desc->size_hi); 962 963 port->capacity = lo | (hi << 32); 964 port->dev_geom_head = le16_to_cpu(desc->head); 965 port->dev_geom_sect = le16_to_cpu(desc->sect); 966 port->dev_geom_cyl = le16_to_cpu(desc->cyl); 967 968 host->dev_active |= (1 << cur_port); 969 970 strncpy(port->name, desc->name, sizeof(port->name)); 971 port->name[sizeof(port->name) - 1] = 0; 972 slen = strlen(port->name); 973 while (slen && (port->name[slen - 1] == ' ')) { 974 port->name[slen - 1] = 0; 975 slen--; 976 } 977 978 printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n", 979 pci_name(host->pdev), port->port_no, 980 (unsigned long long) port->capacity); 981 printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n", 982 pci_name(host->pdev), port->port_no, port->name); 983 984out: 985 assert(host->state == HST_DEV_SCAN); 986 schedule_work(&host->fsm_task); 987} 988 989static void carm_handle_scan_chan(struct carm_host *host, 990 struct carm_request *crq, u8 *mem, 991 int is_ok) 992{ 993 u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET; 994 unsigned int i, dev_count = 0; 995 int new_state = HST_DEV_SCAN_START; 996 997 DPRINTK("ENTER\n"); 998 999 carm_end_rq(host, crq, is_ok); 1000 1001 if (!is_ok) { 1002 new_state = HST_ERROR; 1003 goto out; 1004 } 1005 1006 /* TODO: scan and support non-disk devices */ 1007 for (i = 0; i < 8; i++) 1008 if (msg_data[i] == 0) { /* direct-access device (disk) */ 1009 host->dev_present |= (1 << i); 1010 dev_count++; 1011 } 1012 1013 printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n", 1014 pci_name(host->pdev), dev_count); 1015 1016out: 1017 assert(host->state == HST_PORT_SCAN); 1018 host->state = new_state; 1019 schedule_work(&host->fsm_task); 1020} 1021 1022static void carm_handle_generic(struct carm_host *host, 1023 struct carm_request *crq, int is_ok, 1024 int cur_state, int next_state) 1025{ 1026 DPRINTK("ENTER\n"); 1027 1028 carm_end_rq(host, crq, is_ok); 1029 1030 assert(host->state == cur_state); 1031 if (is_ok) 1032 host->state = next_state; 1033 else 1034 host->state = HST_ERROR; 1035 schedule_work(&host->fsm_task); 1036} 1037 1038static inline void carm_handle_rw(struct carm_host *host, 1039 struct carm_request *crq, int is_ok) 1040{ 1041 int pci_dir; 1042 1043 VPRINTK("ENTER\n"); 1044 1045 if (rq_data_dir(crq->rq) == WRITE) 1046 pci_dir = PCI_DMA_TODEVICE; 1047 else 1048 pci_dir = PCI_DMA_FROMDEVICE; 1049 1050 pci_unmap_sg(host->pdev, &crq->sg[0], crq->n_elem, pci_dir); 1051 1052 carm_end_rq(host, crq, is_ok); 1053} 1054 1055static inline void carm_handle_resp(struct carm_host *host, 1056 __le32 ret_handle_le, u32 status) 1057{ 1058 u32 handle = le32_to_cpu(ret_handle_le); 1059 unsigned int msg_idx; 1060 struct carm_request *crq; 1061 int is_ok = (status == RMSG_OK); 1062 u8 *mem; 1063 1064 VPRINTK("ENTER, handle == 0x%x\n", handle); 1065 1066 if (unlikely(!TAG_VALID(handle))) { 1067 printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n", 1068 pci_name(host->pdev), handle); 1069 return; 1070 } 1071 1072 msg_idx = TAG_DECODE(handle); 1073 VPRINTK("tag == %u\n", msg_idx); 1074 1075 crq = &host->req[msg_idx]; 1076 1077 /* fast path */ 1078 if (likely(crq->msg_type == CARM_MSG_READ || 1079 crq->msg_type == CARM_MSG_WRITE)) { 1080 carm_handle_rw(host, crq, is_ok); 1081 return; 1082 } 1083 1084 mem = carm_ref_msg(host, msg_idx); 1085 1086 switch (crq->msg_type) { 1087 case CARM_MSG_IOCTL: { 1088 switch (crq->msg_subtype) { 1089 case CARM_IOC_SCAN_CHAN: 1090 carm_handle_scan_chan(host, crq, mem, is_ok); 1091 break; 1092 default: 1093 /* unknown / invalid response */ 1094 goto err_out; 1095 } 1096 break; 1097 } 1098 1099 case CARM_MSG_MISC: { 1100 switch (crq->msg_subtype) { 1101 case MISC_ALLOC_MEM: 1102 carm_handle_generic(host, crq, is_ok, 1103 HST_ALLOC_BUF, HST_SYNC_TIME); 1104 break; 1105 case MISC_SET_TIME: 1106 carm_handle_generic(host, crq, is_ok, 1107 HST_SYNC_TIME, HST_GET_FW_VER); 1108 break; 1109 case MISC_GET_FW_VER: { 1110 struct carm_fw_ver *ver = (struct carm_fw_ver *) 1111 mem + sizeof(struct carm_msg_get_fw_ver); 1112 if (is_ok) { 1113 host->fw_ver = le32_to_cpu(ver->version); 1114 host->flags |= (ver->features & FL_FW_VER_MASK); 1115 } 1116 carm_handle_generic(host, crq, is_ok, 1117 HST_GET_FW_VER, HST_PORT_SCAN); 1118 break; 1119 } 1120 default: 1121 /* unknown / invalid response */ 1122 goto err_out; 1123 } 1124 break; 1125 } 1126 1127 case CARM_MSG_ARRAY: { 1128 switch (crq->msg_subtype) { 1129 case CARM_ARRAY_INFO: 1130 carm_handle_array_info(host, crq, mem, is_ok); 1131 break; 1132 default: 1133 /* unknown / invalid response */ 1134 goto err_out; 1135 } 1136 break; 1137 } 1138 1139 default: 1140 /* unknown / invalid response */ 1141 goto err_out; 1142 } 1143 1144 return; 1145 1146err_out: 1147 printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n", 1148 pci_name(host->pdev), crq->msg_type, crq->msg_subtype); 1149 carm_end_rq(host, crq, 0); 1150} 1151 1152static inline void carm_handle_responses(struct carm_host *host) 1153{ 1154 void __iomem *mmio = host->mmio; 1155 struct carm_response *resp = (struct carm_response *) host->shm; 1156 unsigned int work = 0; 1157 unsigned int idx = host->resp_idx % RMSG_Q_LEN; 1158 1159 while (1) { 1160 u32 status = le32_to_cpu(resp[idx].status); 1161 1162 if (status == 0xffffffff) { 1163 VPRINTK("ending response on index %u\n", idx); 1164 writel(idx << 3, mmio + CARM_RESP_IDX); 1165 break; 1166 } 1167 1168 /* response to a message we sent */ 1169 else if ((status & (1 << 31)) == 0) { 1170 VPRINTK("handling msg response on index %u\n", idx); 1171 carm_handle_resp(host, resp[idx].ret_handle, status); 1172 resp[idx].status = cpu_to_le32(0xffffffff); 1173 } 1174 1175 /* asynchronous events the hardware throws our way */ 1176 else if ((status & 0xff000000) == (1 << 31)) { 1177 u8 *evt_type_ptr = (u8 *) &resp[idx]; 1178 u8 evt_type = *evt_type_ptr; 1179 printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n", 1180 pci_name(host->pdev), (int) evt_type); 1181 resp[idx].status = cpu_to_le32(0xffffffff); 1182 } 1183 1184 idx = NEXT_RESP(idx); 1185 work++; 1186 } 1187 1188 VPRINTK("EXIT, work==%u\n", work); 1189 host->resp_idx += work; 1190} 1191 1192static irqreturn_t carm_interrupt(int irq, void *__host) 1193{ 1194 struct carm_host *host = __host; 1195 void __iomem *mmio; 1196 u32 mask; 1197 int handled = 0; 1198 unsigned long flags; 1199 1200 if (!host) { 1201 VPRINTK("no host\n"); 1202 return IRQ_NONE; 1203 } 1204 1205 spin_lock_irqsave(&host->lock, flags); 1206 1207 mmio = host->mmio; 1208 1209 /* reading should also clear interrupts */ 1210 mask = readl(mmio + CARM_INT_STAT); 1211 1212 if (mask == 0 || mask == 0xffffffff) { 1213 VPRINTK("no work, mask == 0x%x\n", mask); 1214 goto out; 1215 } 1216 1217 if (mask & INT_ACK_MASK) 1218 writel(mask, mmio + CARM_INT_STAT); 1219 1220 if (unlikely(host->state == HST_INVALID)) { 1221 VPRINTK("not initialized yet, mask = 0x%x\n", mask); 1222 goto out; 1223 } 1224 1225 if (mask & CARM_HAVE_RESP) { 1226 handled = 1; 1227 carm_handle_responses(host); 1228 } 1229 1230out: 1231 spin_unlock_irqrestore(&host->lock, flags); 1232 VPRINTK("EXIT\n"); 1233 return IRQ_RETVAL(handled); 1234} 1235 1236static void carm_fsm_task (struct work_struct *work) 1237{ 1238 struct carm_host *host = 1239 container_of(work, struct carm_host, fsm_task); 1240 unsigned long flags; 1241 unsigned int state; 1242 int rc, i, next_dev; 1243 int reschedule = 0; 1244 int new_state = HST_INVALID; 1245 1246 spin_lock_irqsave(&host->lock, flags); 1247 state = host->state; 1248 spin_unlock_irqrestore(&host->lock, flags); 1249 1250 DPRINTK("ENTER, state == %s\n", state_name[state]); 1251 1252 switch (state) { 1253 case HST_PROBE_START: 1254 new_state = HST_ALLOC_BUF; 1255 reschedule = 1; 1256 break; 1257 1258 case HST_ALLOC_BUF: 1259 rc = carm_send_special(host, carm_fill_alloc_buf); 1260 if (rc) { 1261 new_state = HST_ERROR; 1262 reschedule = 1; 1263 } 1264 break; 1265 1266 case HST_SYNC_TIME: 1267 rc = carm_send_special(host, carm_fill_sync_time); 1268 if (rc) { 1269 new_state = HST_ERROR; 1270 reschedule = 1; 1271 } 1272 break; 1273 1274 case HST_GET_FW_VER: 1275 rc = carm_send_special(host, carm_fill_get_fw_ver); 1276 if (rc) { 1277 new_state = HST_ERROR; 1278 reschedule = 1; 1279 } 1280 break; 1281 1282 case HST_PORT_SCAN: 1283 rc = carm_send_special(host, carm_fill_scan_channels); 1284 if (rc) { 1285 new_state = HST_ERROR; 1286 reschedule = 1; 1287 } 1288 break; 1289 1290 case HST_DEV_SCAN_START: 1291 host->cur_scan_dev = -1; 1292 new_state = HST_DEV_SCAN; 1293 reschedule = 1; 1294 break; 1295 1296 case HST_DEV_SCAN: 1297 next_dev = -1; 1298 for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++) 1299 if (host->dev_present & (1 << i)) { 1300 next_dev = i; 1301 break; 1302 } 1303 1304 if (next_dev >= 0) { 1305 host->cur_scan_dev = next_dev; 1306 rc = carm_array_info(host, next_dev); 1307 if (rc) { 1308 new_state = HST_ERROR; 1309 reschedule = 1; 1310 } 1311 } else { 1312 new_state = HST_DEV_ACTIVATE; 1313 reschedule = 1; 1314 } 1315 break; 1316 1317 case HST_DEV_ACTIVATE: { 1318 int activated = 0; 1319 for (i = 0; i < CARM_MAX_PORTS; i++) 1320 if (host->dev_active & (1 << i)) { 1321 struct carm_port *port = &host->port[i]; 1322 struct gendisk *disk = port->disk; 1323 1324 set_capacity(disk, port->capacity); 1325 add_disk(disk); 1326 activated++; 1327 } 1328 1329 printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n", 1330 pci_name(host->pdev), activated); 1331 1332 new_state = HST_PROBE_FINISHED; 1333 reschedule = 1; 1334 break; 1335 } 1336 1337 case HST_PROBE_FINISHED: 1338 complete(&host->probe_comp); 1339 break; 1340 1341 case HST_ERROR: 1342 break; 1343 1344 default: 1345 /* should never occur */ 1346 printk(KERN_ERR PFX "BUG: unknown state %d\n", state); 1347 assert(0); 1348 break; 1349 } 1350 1351 if (new_state != HST_INVALID) { 1352 spin_lock_irqsave(&host->lock, flags); 1353 host->state = new_state; 1354 spin_unlock_irqrestore(&host->lock, flags); 1355 } 1356 if (reschedule) 1357 schedule_work(&host->fsm_task); 1358} 1359 1360static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit) 1361{ 1362 unsigned int i; 1363 1364 for (i = 0; i < 50000; i++) { 1365 u32 tmp = readl(mmio + CARM_LMUC); 1366 udelay(100); 1367 1368 if (test_bit) { 1369 if ((tmp & bits) == bits) 1370 return 0; 1371 } else { 1372 if ((tmp & bits) == 0) 1373 return 0; 1374 } 1375 1376 cond_resched(); 1377 } 1378 1379 printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n", 1380 bits, test_bit ? "yes" : "no"); 1381 return -EBUSY; 1382} 1383 1384static void carm_init_responses(struct carm_host *host) 1385{ 1386 void __iomem *mmio = host->mmio; 1387 unsigned int i; 1388 struct carm_response *resp = (struct carm_response *) host->shm; 1389 1390 for (i = 0; i < RMSG_Q_LEN; i++) 1391 resp[i].status = cpu_to_le32(0xffffffff); 1392 1393 writel(0, mmio + CARM_RESP_IDX); 1394} 1395 1396static int carm_init_host(struct carm_host *host) 1397{ 1398 void __iomem *mmio = host->mmio; 1399 u32 tmp; 1400 u8 tmp8; 1401 int rc; 1402 1403 DPRINTK("ENTER\n"); 1404 1405 writel(0, mmio + CARM_INT_MASK); 1406 1407 tmp8 = readb(mmio + CARM_INITC); 1408 if (tmp8 & 0x01) { 1409 tmp8 &= ~0x01; 1410 writeb(tmp8, mmio + CARM_INITC); 1411 readb(mmio + CARM_INITC); /* flush */ 1412 1413 DPRINTK("snooze...\n"); 1414 msleep(5000); 1415 } 1416 1417 tmp = readl(mmio + CARM_HMUC); 1418 if (tmp & CARM_CME) { 1419 DPRINTK("CME bit present, waiting\n"); 1420 rc = carm_init_wait(mmio, CARM_CME, 1); 1421 if (rc) { 1422 DPRINTK("EXIT, carm_init_wait 1 failed\n"); 1423 return rc; 1424 } 1425 } 1426 if (tmp & CARM_RME) { 1427 DPRINTK("RME bit present, waiting\n"); 1428 rc = carm_init_wait(mmio, CARM_RME, 1); 1429 if (rc) { 1430 DPRINTK("EXIT, carm_init_wait 2 failed\n"); 1431 return rc; 1432 } 1433 } 1434 1435 tmp &= ~(CARM_RME | CARM_CME); 1436 writel(tmp, mmio + CARM_HMUC); 1437 readl(mmio + CARM_HMUC); /* flush */ 1438 1439 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0); 1440 if (rc) { 1441 DPRINTK("EXIT, carm_init_wait 3 failed\n"); 1442 return rc; 1443 } 1444 1445 carm_init_buckets(mmio); 1446 1447 writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO); 1448 writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI); 1449 writel(RBUF_LEN, mmio + RBUF_BYTE_SZ); 1450 1451 tmp = readl(mmio + CARM_HMUC); 1452 tmp |= (CARM_RME | CARM_CME | CARM_WZBC); 1453 writel(tmp, mmio + CARM_HMUC); 1454 readl(mmio + CARM_HMUC); /* flush */ 1455 1456 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1); 1457 if (rc) { 1458 DPRINTK("EXIT, carm_init_wait 4 failed\n"); 1459 return rc; 1460 } 1461 1462 writel(0, mmio + CARM_HMPHA); 1463 writel(INT_DEF_MASK, mmio + CARM_INT_MASK); 1464 1465 carm_init_responses(host); 1466 1467 /* start initialization, probing state machine */ 1468 spin_lock_irq(&host->lock); 1469 assert(host->state == HST_INVALID); 1470 host->state = HST_PROBE_START; 1471 spin_unlock_irq(&host->lock); 1472 schedule_work(&host->fsm_task); 1473 1474 DPRINTK("EXIT\n"); 1475 return 0; 1476} 1477 1478static int carm_init_disks(struct carm_host *host) 1479{ 1480 unsigned int i; 1481 int rc = 0; 1482 1483 for (i = 0; i < CARM_MAX_PORTS; i++) { 1484 struct gendisk *disk; 1485 request_queue_t *q; 1486 struct carm_port *port; 1487 1488 port = &host->port[i]; 1489 port->host = host; 1490 port->port_no = i; 1491 1492 disk = alloc_disk(CARM_MINORS_PER_MAJOR); 1493 if (!disk) { 1494 rc = -ENOMEM; 1495 break; 1496 } 1497 1498 port->disk = disk; 1499 sprintf(disk->disk_name, DRV_NAME "/%u", 1500 (unsigned int) (host->id * CARM_MAX_PORTS) + i); 1501 disk->major = host->major; 1502 disk->first_minor = i * CARM_MINORS_PER_MAJOR; 1503 disk->fops = &carm_bd_ops; 1504 disk->private_data = port; 1505 1506 q = blk_init_queue(carm_rq_fn, &host->lock); 1507 if (!q) { 1508 rc = -ENOMEM; 1509 break; 1510 } 1511 disk->queue = q; 1512 blk_queue_max_hw_segments(q, CARM_MAX_REQ_SG); 1513 blk_queue_max_phys_segments(q, CARM_MAX_REQ_SG); 1514 blk_queue_segment_boundary(q, CARM_SG_BOUNDARY); 1515 1516 q->queuedata = port; 1517 } 1518 1519 return rc; 1520} 1521 1522static void carm_free_disks(struct carm_host *host) 1523{ 1524 unsigned int i; 1525 1526 for (i = 0; i < CARM_MAX_PORTS; i++) { 1527 struct gendisk *disk = host->port[i].disk; 1528 if (disk) { 1529 request_queue_t *q = disk->queue; 1530 1531 if (disk->flags & GENHD_FL_UP) 1532 del_gendisk(disk); 1533 if (q) 1534 blk_cleanup_queue(q); 1535 put_disk(disk); 1536 } 1537 } 1538} 1539 1540static int carm_init_shm(struct carm_host *host) 1541{ 1542 host->shm = pci_alloc_consistent(host->pdev, CARM_SHM_SIZE, 1543 &host->shm_dma); 1544 if (!host->shm) 1545 return -ENOMEM; 1546 1547 host->msg_base = host->shm + RBUF_LEN; 1548 host->msg_dma = host->shm_dma + RBUF_LEN; 1549 1550 memset(host->shm, 0xff, RBUF_LEN); 1551 memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN); 1552 1553 return 0; 1554} 1555 1556static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 1557{ 1558 static unsigned int printed_version; 1559 struct carm_host *host; 1560 unsigned int pci_dac; 1561 int rc; 1562 request_queue_t *q; 1563 unsigned int i; 1564 1565 if (!printed_version++) 1566 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); 1567 1568 rc = pci_enable_device(pdev); 1569 if (rc) 1570 return rc; 1571 1572 rc = pci_request_regions(pdev, DRV_NAME); 1573 if (rc) 1574 goto err_out; 1575 1576#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ 1577 rc = pci_set_dma_mask(pdev, DMA_64BIT_MASK); 1578 if (!rc) { 1579 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 1580 if (rc) { 1581 printk(KERN_ERR DRV_NAME "(%s): consistent DMA mask failure\n", 1582 pci_name(pdev)); 1583 goto err_out_regions; 1584 } 1585 pci_dac = 1; 1586 } else { 1587#endif 1588 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1589 if (rc) { 1590 printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n", 1591 pci_name(pdev)); 1592 goto err_out_regions; 1593 } 1594 pci_dac = 0; 1595#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ 1596 } 1597#endif 1598 1599 host = kmalloc(sizeof(*host), GFP_KERNEL); 1600 if (!host) { 1601 printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n", 1602 pci_name(pdev)); 1603 rc = -ENOMEM; 1604 goto err_out_regions; 1605 } 1606 1607 memset(host, 0, sizeof(*host)); 1608 host->pdev = pdev; 1609 host->flags = pci_dac ? FL_DAC : 0; 1610 spin_lock_init(&host->lock); 1611 INIT_WORK(&host->fsm_task, carm_fsm_task); 1612 init_completion(&host->probe_comp); 1613 1614 for (i = 0; i < ARRAY_SIZE(host->req); i++) 1615 host->req[i].tag = i; 1616 1617 host->mmio = ioremap(pci_resource_start(pdev, 0), 1618 pci_resource_len(pdev, 0)); 1619 if (!host->mmio) { 1620 printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n", 1621 pci_name(pdev)); 1622 rc = -ENOMEM; 1623 goto err_out_kfree; 1624 } 1625 1626 rc = carm_init_shm(host); 1627 if (rc) { 1628 printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n", 1629 pci_name(pdev)); 1630 goto err_out_iounmap; 1631 } 1632 1633 q = blk_init_queue(carm_oob_rq_fn, &host->lock); 1634 if (!q) { 1635 printk(KERN_ERR DRV_NAME "(%s): OOB queue alloc failure\n", 1636 pci_name(pdev)); 1637 rc = -ENOMEM; 1638 goto err_out_pci_free; 1639 } 1640 host->oob_q = q; 1641 q->queuedata = host; 1642 1643 /* 1644 * Figure out which major to use: 160, 161, or dynamic 1645 */ 1646 if (!test_and_set_bit(0, &carm_major_alloc)) 1647 host->major = 160; 1648 else if (!test_and_set_bit(1, &carm_major_alloc)) 1649 host->major = 161; 1650 else 1651 host->flags |= FL_DYN_MAJOR; 1652 1653 host->id = carm_host_id; 1654 sprintf(host->name, DRV_NAME "%d", carm_host_id); 1655 1656 rc = register_blkdev(host->major, host->name); 1657 if (rc < 0) 1658 goto err_out_free_majors; 1659 if (host->flags & FL_DYN_MAJOR) 1660 host->major = rc; 1661 1662 rc = carm_init_disks(host); 1663 if (rc) 1664 goto err_out_blkdev_disks; 1665 1666 pci_set_master(pdev); 1667 1668 rc = request_irq(pdev->irq, carm_interrupt, IRQF_SHARED, DRV_NAME, host); 1669 if (rc) { 1670 printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n", 1671 pci_name(pdev)); 1672 goto err_out_blkdev_disks; 1673 } 1674 1675 rc = carm_init_host(host); 1676 if (rc) 1677 goto err_out_free_irq; 1678 1679 DPRINTK("waiting for probe_comp\n"); 1680 wait_for_completion(&host->probe_comp); 1681 1682 printk(KERN_INFO "%s: pci %s, ports %d, io %llx, irq %u, major %d\n", 1683 host->name, pci_name(pdev), (int) CARM_MAX_PORTS, 1684 (unsigned long long)pci_resource_start(pdev, 0), 1685 pdev->irq, host->major); 1686 1687 carm_host_id++; 1688 pci_set_drvdata(pdev, host); 1689 return 0; 1690 1691err_out_free_irq: 1692 free_irq(pdev->irq, host); 1693err_out_blkdev_disks: 1694 carm_free_disks(host); 1695 unregister_blkdev(host->major, host->name); 1696err_out_free_majors: 1697 if (host->major == 160) 1698 clear_bit(0, &carm_major_alloc); 1699 else if (host->major == 161) 1700 clear_bit(1, &carm_major_alloc); 1701 blk_cleanup_queue(host->oob_q); 1702err_out_pci_free: 1703 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma); 1704err_out_iounmap: 1705 iounmap(host->mmio); 1706err_out_kfree: 1707 kfree(host); 1708err_out_regions: 1709 pci_release_regions(pdev); 1710err_out: 1711 pci_disable_device(pdev); 1712 return rc; 1713} 1714 1715static void carm_remove_one (struct pci_dev *pdev) 1716{ 1717 struct carm_host *host = pci_get_drvdata(pdev); 1718 1719 if (!host) { 1720 printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n", 1721 pci_name(pdev)); 1722 return; 1723 } 1724 1725 free_irq(pdev->irq, host); 1726 carm_free_disks(host); 1727 unregister_blkdev(host->major, host->name); 1728 if (host->major == 160) 1729 clear_bit(0, &carm_major_alloc); 1730 else if (host->major == 161) 1731 clear_bit(1, &carm_major_alloc); 1732 blk_cleanup_queue(host->oob_q); 1733 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma); 1734 iounmap(host->mmio); 1735 kfree(host); 1736 pci_release_regions(pdev); 1737 pci_disable_device(pdev); 1738 pci_set_drvdata(pdev, NULL); 1739} 1740 1741static int __init carm_init(void) 1742{ 1743 return pci_register_driver(&carm_driver); 1744} 1745 1746static void __exit carm_exit(void) 1747{ 1748 pci_unregister_driver(&carm_driver); 1749} 1750 1751module_init(carm_init); 1752module_exit(carm_exit); 1753