1/* 2 * pata_optidma.c - Opti DMA PATA for new ATA layer 3 * (C) 2006 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * The Opti DMA controllers are related to the older PIO PCI controllers 7 * and indeed the VLB ones. The main differences are that the timing 8 * numbers are now based off PCI clocks not VLB and differ, and that 9 * MWDMA is supported. 10 * 11 * This driver should support Viper-N+, FireStar, FireStar Plus. 12 * 13 * These devices support virtual DMA for read (aka the CS5520). Later 14 * chips support UDMA33, but only if the rest of the board logic does, 15 * so you have to get this right. We don't support the virtual DMA 16 * but we do handle UDMA. 17 * 18 * Bits that are worth knowing 19 * Most control registers are shadowed into I/O registers 20 * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz 21 * Virtual DMA registers *move* between rev 0x02 and rev 0x10 22 * UDMA requires a 66MHz FSB 23 * 24 */ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/pci.h> 29#include <linux/init.h> 30#include <linux/blkdev.h> 31#include <linux/delay.h> 32#include <scsi/scsi_host.h> 33#include <linux/libata.h> 34 35#define DRV_NAME "pata_optidma" 36#define DRV_VERSION "0.3.2" 37 38enum { 39 READ_REG = 0, /* index of Read cycle timing register */ 40 WRITE_REG = 1, /* index of Write cycle timing register */ 41 CNTRL_REG = 3, /* index of Control register */ 42 STRAP_REG = 5, /* index of Strap register */ 43 MISC_REG = 6 /* index of Miscellaneous register */ 44}; 45 46static int pci_clock; /* 0 = 33 1 = 25 */ 47 48/** 49 * optidma_pre_reset - probe begin 50 * @ap: ATA port 51 * @deadline: deadline jiffies for the operation 52 * 53 * Set up cable type and use generic probe init 54 */ 55 56static int optidma_pre_reset(struct ata_port *ap, unsigned long deadline) 57{ 58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 59 static const struct pci_bits optidma_enable_bits = { 60 0x40, 1, 0x08, 0x00 61 }; 62 63 if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits)) 64 return -ENOENT; 65 66 return ata_std_prereset(ap, deadline); 67} 68 69/** 70 * optidma_probe_reset - probe reset 71 * @ap: ATA port 72 * 73 * Perform the ATA probe and bus reset sequence plus specific handling 74 * for this hardware. The Opti needs little handling - we have no UDMA66 75 * capability that needs cable detection. All we must do is check the port 76 * is enabled. 77 */ 78 79static void optidma_error_handler(struct ata_port *ap) 80{ 81 ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 82} 83 84/** 85 * optidma_unlock - unlock control registers 86 * @ap: ATA port 87 * 88 * Unlock the control register block for this adapter. Registers must not 89 * be unlocked in a situation where libata might look at them. 90 */ 91 92static void optidma_unlock(struct ata_port *ap) 93{ 94 void __iomem *regio = ap->ioaddr.cmd_addr; 95 96 /* These 3 unlock the control register access */ 97 ioread16(regio + 1); 98 ioread16(regio + 1); 99 iowrite8(3, regio + 2); 100} 101 102/** 103 * optidma_lock - issue temporary relock 104 * @ap: ATA port 105 * 106 * Re-lock the configuration register settings. 107 */ 108 109static void optidma_lock(struct ata_port *ap) 110{ 111 void __iomem *regio = ap->ioaddr.cmd_addr; 112 113 /* Relock */ 114 iowrite8(0x83, regio + 2); 115} 116 117/** 118 * optidma_mode_setup - set mode data 119 * @ap: ATA interface 120 * @adev: ATA device 121 * @mode: Mode to set 122 * 123 * Called to do the DMA or PIO mode setup. Timing numbers are all 124 * pre computed to keep the code clean. There are two tables depending 125 * on the hardware clock speed. 126 * 127 * WARNING: While we do this the IDE registers vanish. If we take an 128 * IRQ here we depend on the host set locking to avoid catastrophe. 129 */ 130 131static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode) 132{ 133 struct ata_device *pair = ata_dev_pair(adev); 134 int pio = adev->pio_mode - XFER_PIO_0; 135 int dma = adev->dma_mode - XFER_MW_DMA_0; 136 void __iomem *regio = ap->ioaddr.cmd_addr; 137 u8 addr; 138 139 /* Address table precomputed with a DCLK of 2 */ 140 static const u8 addr_timing[2][5] = { 141 { 0x30, 0x20, 0x20, 0x10, 0x10 }, 142 { 0x20, 0x20, 0x10, 0x10, 0x10 } 143 }; 144 static const u8 data_rec_timing[2][5] = { 145 { 0x59, 0x46, 0x30, 0x20, 0x20 }, 146 { 0x46, 0x32, 0x20, 0x20, 0x10 } 147 }; 148 static const u8 dma_data_rec_timing[2][3] = { 149 { 0x76, 0x20, 0x20 }, 150 { 0x54, 0x20, 0x10 } 151 }; 152 153 /* Switch from IDE to control mode */ 154 optidma_unlock(ap); 155 156 157 158 if (mode >= XFER_MW_DMA_0) 159 addr = 0; 160 else 161 addr = addr_timing[pci_clock][pio]; 162 163 if (pair) { 164 u8 pair_addr; 165 /* Hardware constraint */ 166 if (pair->dma_mode) 167 pair_addr = 0; 168 else 169 pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0]; 170 if (pair_addr > addr) 171 addr = pair_addr; 172 } 173 174 /* Commence primary programming sequence */ 175 /* First we load the device number into the timing select */ 176 iowrite8(adev->devno, regio + MISC_REG); 177 /* Now we load the data timings into read data/write data */ 178 if (mode < XFER_MW_DMA_0) { 179 iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG); 180 iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG); 181 } else if (mode < XFER_UDMA_0) { 182 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG); 183 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG); 184 } 185 /* Finally we load the address setup into the misc register */ 186 iowrite8(addr | adev->devno, regio + MISC_REG); 187 188 /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */ 189 iowrite8(0x85, regio + CNTRL_REG); 190 191 /* Switch back to IDE mode */ 192 optidma_lock(ap); 193 194 /* Note: at this point our programming is incomplete. We are 195 not supposed to program PCI 0x43 "things we hacked onto the chip" 196 until we've done both sets of PIO/DMA timings */ 197} 198 199/** 200 * optiplus_mode_setup - DMA setup for Firestar Plus 201 * @ap: ATA port 202 * @adev: device 203 * @mode: desired mode 204 * 205 * The Firestar plus has additional UDMA functionality for UDMA0-2 and 206 * requires we do some additional work. Because the base work we must do 207 * is mostly shared we wrap the Firestar setup functionality in this 208 * one 209 */ 210 211static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode) 212{ 213 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 214 u8 udcfg; 215 u8 udslave; 216 int dev2 = 2 * adev->devno; 217 int unit = 2 * ap->port_no + adev->devno; 218 int udma = mode - XFER_UDMA_0; 219 220 pci_read_config_byte(pdev, 0x44, &udcfg); 221 if (mode <= XFER_UDMA_0) { 222 udcfg &= ~(1 << unit); 223 optidma_mode_setup(ap, adev, adev->dma_mode); 224 } else { 225 udcfg |= (1 << unit); 226 if (ap->port_no) { 227 pci_read_config_byte(pdev, 0x45, &udslave); 228 udslave &= ~(0x03 << dev2); 229 udslave |= (udma << dev2); 230 pci_write_config_byte(pdev, 0x45, udslave); 231 } else { 232 udcfg &= ~(0x30 << dev2); 233 udcfg |= (udma << dev2); 234 } 235 } 236 pci_write_config_byte(pdev, 0x44, udcfg); 237} 238 239/** 240 * optidma_set_pio_mode - PIO setup callback 241 * @ap: ATA port 242 * @adev: Device 243 * 244 * The libata core provides separate functions for handling PIO and 245 * DMA programming. The architecture of the Firestar makes it easier 246 * for us to have a common function so we provide wrappers 247 */ 248 249static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev) 250{ 251 optidma_mode_setup(ap, adev, adev->pio_mode); 252} 253 254/** 255 * optidma_set_dma_mode - DMA setup callback 256 * @ap: ATA port 257 * @adev: Device 258 * 259 * The libata core provides separate functions for handling PIO and 260 * DMA programming. The architecture of the Firestar makes it easier 261 * for us to have a common function so we provide wrappers 262 */ 263 264static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev) 265{ 266 optidma_mode_setup(ap, adev, adev->dma_mode); 267} 268 269/** 270 * optiplus_set_pio_mode - PIO setup callback 271 * @ap: ATA port 272 * @adev: Device 273 * 274 * The libata core provides separate functions for handling PIO and 275 * DMA programming. The architecture of the Firestar makes it easier 276 * for us to have a common function so we provide wrappers 277 */ 278 279static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev) 280{ 281 optiplus_mode_setup(ap, adev, adev->pio_mode); 282} 283 284/** 285 * optiplus_set_dma_mode - DMA setup callback 286 * @ap: ATA port 287 * @adev: Device 288 * 289 * The libata core provides separate functions for handling PIO and 290 * DMA programming. The architecture of the Firestar makes it easier 291 * for us to have a common function so we provide wrappers 292 */ 293 294static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev) 295{ 296 optiplus_mode_setup(ap, adev, adev->dma_mode); 297} 298 299/** 300 * optidma_make_bits - PCI setup helper 301 * @adev: ATA device 302 * 303 * Turn the ATA device setup into PCI configuration bits 304 * for register 0x43 and return the two bits needed. 305 */ 306 307static u8 optidma_make_bits43(struct ata_device *adev) 308{ 309 static const u8 bits43[5] = { 310 0, 0, 0, 1, 2 311 }; 312 if (!ata_dev_enabled(adev)) 313 return 0; 314 if (adev->dma_mode) 315 return adev->dma_mode - XFER_MW_DMA_0; 316 return bits43[adev->pio_mode - XFER_PIO_0]; 317} 318 319/** 320 * optidma_set_mode - mode setup 321 * @ap: port to set up 322 * 323 * Use the standard setup to tune the chipset and then finalise the 324 * configuration by writing the nibble of extra bits of data into 325 * the chip. 326 */ 327 328static int optidma_set_mode(struct ata_port *ap, struct ata_device **r_failed) 329{ 330 u8 r; 331 int nybble = 4 * ap->port_no; 332 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 333 int rc = ata_do_set_mode(ap, r_failed); 334 if (rc == 0) { 335 pci_read_config_byte(pdev, 0x43, &r); 336 337 r &= (0x0F << nybble); 338 r |= (optidma_make_bits43(&ap->device[0]) + 339 (optidma_make_bits43(&ap->device[0]) << 2)) << nybble; 340 pci_write_config_byte(pdev, 0x43, r); 341 } 342 return rc; 343} 344 345static struct scsi_host_template optidma_sht = { 346 .module = THIS_MODULE, 347 .name = DRV_NAME, 348 .ioctl = ata_scsi_ioctl, 349 .queuecommand = ata_scsi_queuecmd, 350 .can_queue = ATA_DEF_QUEUE, 351 .this_id = ATA_SHT_THIS_ID, 352 .sg_tablesize = LIBATA_MAX_PRD, 353 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 354 .emulated = ATA_SHT_EMULATED, 355 .use_clustering = ATA_SHT_USE_CLUSTERING, 356 .proc_name = DRV_NAME, 357 .dma_boundary = ATA_DMA_BOUNDARY, 358 .slave_configure = ata_scsi_slave_config, 359 .slave_destroy = ata_scsi_slave_destroy, 360 .bios_param = ata_std_bios_param, 361}; 362 363static struct ata_port_operations optidma_port_ops = { 364 .port_disable = ata_port_disable, 365 .set_piomode = optidma_set_pio_mode, 366 .set_dmamode = optidma_set_dma_mode, 367 368 .tf_load = ata_tf_load, 369 .tf_read = ata_tf_read, 370 .check_status = ata_check_status, 371 .exec_command = ata_exec_command, 372 .dev_select = ata_std_dev_select, 373 374 .freeze = ata_bmdma_freeze, 375 .thaw = ata_bmdma_thaw, 376 .post_internal_cmd = ata_bmdma_post_internal_cmd, 377 .error_handler = optidma_error_handler, 378 .set_mode = optidma_set_mode, 379 .cable_detect = ata_cable_40wire, 380 381 .bmdma_setup = ata_bmdma_setup, 382 .bmdma_start = ata_bmdma_start, 383 .bmdma_stop = ata_bmdma_stop, 384 .bmdma_status = ata_bmdma_status, 385 386 .qc_prep = ata_qc_prep, 387 .qc_issue = ata_qc_issue_prot, 388 389 .data_xfer = ata_data_xfer, 390 391 .irq_handler = ata_interrupt, 392 .irq_clear = ata_bmdma_irq_clear, 393 .irq_on = ata_irq_on, 394 .irq_ack = ata_irq_ack, 395 396 .port_start = ata_port_start, 397}; 398 399static struct ata_port_operations optiplus_port_ops = { 400 .port_disable = ata_port_disable, 401 .set_piomode = optiplus_set_pio_mode, 402 .set_dmamode = optiplus_set_dma_mode, 403 404 .tf_load = ata_tf_load, 405 .tf_read = ata_tf_read, 406 .check_status = ata_check_status, 407 .exec_command = ata_exec_command, 408 .dev_select = ata_std_dev_select, 409 410 .freeze = ata_bmdma_freeze, 411 .thaw = ata_bmdma_thaw, 412 .post_internal_cmd = ata_bmdma_post_internal_cmd, 413 .error_handler = optidma_error_handler, 414 .set_mode = optidma_set_mode, 415 .cable_detect = ata_cable_40wire, 416 417 .bmdma_setup = ata_bmdma_setup, 418 .bmdma_start = ata_bmdma_start, 419 .bmdma_stop = ata_bmdma_stop, 420 .bmdma_status = ata_bmdma_status, 421 422 .qc_prep = ata_qc_prep, 423 .qc_issue = ata_qc_issue_prot, 424 425 .data_xfer = ata_data_xfer, 426 427 .irq_handler = ata_interrupt, 428 .irq_clear = ata_bmdma_irq_clear, 429 .irq_on = ata_irq_on, 430 .irq_ack = ata_irq_ack, 431 432 .port_start = ata_port_start, 433}; 434 435/** 436 * optiplus_with_udma - Look for UDMA capable setup 437 * @pdev; ATA controller 438 */ 439 440static int optiplus_with_udma(struct pci_dev *pdev) 441{ 442 u8 r; 443 int ret = 0; 444 int ioport = 0x22; 445 struct pci_dev *dev1; 446 447 /* Find function 1 */ 448 dev1 = pci_get_device(0x1045, 0xC701, NULL); 449 if(dev1 == NULL) 450 return 0; 451 452 /* Rev must be >= 0x10 */ 453 pci_read_config_byte(dev1, 0x08, &r); 454 if (r < 0x10) 455 goto done_nomsg; 456 /* Read the chipset system configuration to check our mode */ 457 pci_read_config_byte(dev1, 0x5F, &r); 458 ioport |= (r << 8); 459 outb(0x10, ioport); 460 /* Must be 66Mhz sync */ 461 if ((inb(ioport + 2) & 1) == 0) 462 goto done; 463 464 /* Check the ATA arbitration/timing is suitable */ 465 pci_read_config_byte(pdev, 0x42, &r); 466 if ((r & 0x36) != 0x36) 467 goto done; 468 pci_read_config_byte(dev1, 0x52, &r); 469 if (r & 0x80) /* IDEDIR disabled */ 470 ret = 1; 471done: 472 printk(KERN_WARNING "UDMA not supported in this configuration.\n"); 473done_nomsg: /* Wrong chip revision */ 474 pci_dev_put(dev1); 475 return ret; 476} 477 478static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id) 479{ 480 static const struct ata_port_info info_82c700 = { 481 .sht = &optidma_sht, 482 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 483 .pio_mask = 0x1f, 484 .mwdma_mask = 0x07, 485 .port_ops = &optidma_port_ops 486 }; 487 static const struct ata_port_info info_82c700_udma = { 488 .sht = &optidma_sht, 489 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 490 .pio_mask = 0x1f, 491 .mwdma_mask = 0x07, 492 .udma_mask = 0x07, 493 .port_ops = &optiplus_port_ops 494 }; 495 const struct ata_port_info *ppi[] = { &info_82c700, NULL }; 496 static int printed_version; 497 498 if (!printed_version++) 499 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n"); 500 501 /* Fixed location chipset magic */ 502 inw(0x1F1); 503 inw(0x1F1); 504 pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */ 505 506 if (optiplus_with_udma(dev)) 507 ppi[0] = &info_82c700_udma; 508 509 return ata_pci_init_one(dev, ppi); 510} 511 512static const struct pci_device_id optidma[] = { 513 { PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */ 514 515 { }, 516}; 517 518static struct pci_driver optidma_pci_driver = { 519 .name = DRV_NAME, 520 .id_table = optidma, 521 .probe = optidma_init_one, 522 .remove = ata_pci_remove_one, 523#ifdef CONFIG_PM 524 .suspend = ata_pci_device_suspend, 525 .resume = ata_pci_device_resume, 526#endif 527}; 528 529static int __init optidma_init(void) 530{ 531 return pci_register_driver(&optidma_pci_driver); 532} 533 534static void __exit optidma_exit(void) 535{ 536 pci_unregister_driver(&optidma_pci_driver); 537} 538 539MODULE_AUTHOR("Alan Cox"); 540MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus"); 541MODULE_LICENSE("GPL"); 542MODULE_DEVICE_TABLE(pci, optidma); 543MODULE_VERSION(DRV_VERSION); 544 545module_init(optidma_init); 546module_exit(optidma_exit); 547