1/* Linker script for the sim85e2c simulator, which is a verilog simulation of 2 the V850E2 NA85E2C cpu core (CONFIG_V850E2_SIM85E2C). */ 3 4MEMORY { 5 /* 1MB of `instruction RAM', starting at 0. 6 Instruction fetches are much faster from IRAM than from DRAM. */ 7 IRAM : ORIGIN = IRAM_ADDR, LENGTH = IRAM_SIZE 8 9 /* 1MB of `data RAM', below and contiguous with the I/O space. 10 Data fetches are much faster from DRAM than from IRAM. */ 11 DRAM : ORIGIN = DRAM_ADDR, LENGTH = DRAM_SIZE 12 13 /* `external ram' (CS1 area), comes after IRAM. */ 14 ERAM : ORIGIN = ERAM_ADDR, LENGTH = ERAM_SIZE 15 16 /* Dynamic RAM; uses memory controller. */ 17 SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE 18} 19 20SECTIONS { 21 .iram : { 22 INTV_CONTENTS 23 *arch/v850/kernel/head.o 24 *(.early.text) 25 } > IRAM 26 .dram : { 27 _memcons_output = . ; 28 . = . + 0x8000 ; 29 _memcons_output_end = . ; 30 } > DRAM 31 .sdram : { 32 /* We stick console output into a buffer here. */ 33 RAMK_KRAM_CONTENTS 34 ROOT_FS_CONTENTS 35 } > SDRAM 36} 37