1/* $Id: math.c,v 1.1.1.1 2007/08/03 18:52:19 Exp $ 2 * arch/sparc64/math-emu/math.c 3 * 4 * Copyright (C) 1997,1999 Jakub Jelinek (jj@ultra.linux.cz) 5 * Copyright (C) 1999 David S. Miller (davem@redhat.com) 6 * 7 * Emulation routines originate from soft-fp package, which is part 8 * of glibc and has appropriate copyrights in it. 9 */ 10 11#include <linux/types.h> 12#include <linux/sched.h> 13#include <linux/errno.h> 14 15#include <asm/fpumacro.h> 16#include <asm/ptrace.h> 17#include <asm/uaccess.h> 18 19#include "sfp-util.h" 20#include <math-emu/soft-fp.h> 21#include <math-emu/single.h> 22#include <math-emu/double.h> 23#include <math-emu/quad.h> 24 25/* QUAD - ftt == 3 */ 26#define FMOVQ 0x003 27#define FNEGQ 0x007 28#define FABSQ 0x00b 29#define FSQRTQ 0x02b 30#define FADDQ 0x043 31#define FSUBQ 0x047 32#define FMULQ 0x04b 33#define FDIVQ 0x04f 34#define FDMULQ 0x06e 35#define FQTOX 0x083 36#define FXTOQ 0x08c 37#define FQTOS 0x0c7 38#define FQTOD 0x0cb 39#define FITOQ 0x0cc 40#define FSTOQ 0x0cd 41#define FDTOQ 0x0ce 42#define FQTOI 0x0d3 43/* SUBNORMAL - ftt == 2 */ 44#define FSQRTS 0x029 45#define FSQRTD 0x02a 46#define FADDS 0x041 47#define FADDD 0x042 48#define FSUBS 0x045 49#define FSUBD 0x046 50#define FMULS 0x049 51#define FMULD 0x04a 52#define FDIVS 0x04d 53#define FDIVD 0x04e 54#define FSMULD 0x069 55#define FSTOX 0x081 56#define FDTOX 0x082 57#define FDTOS 0x0c6 58#define FSTOD 0x0c9 59#define FSTOI 0x0d1 60#define FDTOI 0x0d2 61#define FXTOS 0x084 /* Only Ultra-III generates this. */ 62#define FXTOD 0x088 /* Only Ultra-III generates this. */ 63#define FITOD 0x0c8 /* Only Ultra-III generates this. */ 64/* FPOP2 */ 65#define FCMPQ 0x053 66#define FCMPEQ 0x057 67#define FMOVQ0 0x003 68#define FMOVQ1 0x043 69#define FMOVQ2 0x083 70#define FMOVQ3 0x0c3 71#define FMOVQI 0x103 72#define FMOVQX 0x183 73#define FMOVQZ 0x027 74#define FMOVQLE 0x047 75#define FMOVQLZ 0x067 76#define FMOVQNZ 0x0a7 77#define FMOVQGZ 0x0c7 78#define FMOVQGE 0x0e7 79 80#define FSR_TEM_SHIFT 23UL 81#define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT) 82#define FSR_AEXC_SHIFT 5UL 83#define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT) 84#define FSR_CEXC_SHIFT 0UL 85#define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT) 86 87/* All routines returning an exception to raise should detect 88 * such exceptions _before_ rounding to be consistent with 89 * the behavior of the hardware in the implemented cases 90 * (and thus with the recommendations in the V9 architecture 91 * manual). 92 * 93 * We return 0 if a SIGFPE should be sent, 1 otherwise. 94 */ 95static inline int record_exception(struct pt_regs *regs, int eflag) 96{ 97 u64 fsr = current_thread_info()->xfsr[0]; 98 int would_trap; 99 100 /* Determine if this exception would have generated a trap. */ 101 would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL; 102 103 /* If trapping, we only want to signal one bit. */ 104 if(would_trap != 0) { 105 eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT); 106 if((eflag & (eflag - 1)) != 0) { 107 if(eflag & FP_EX_INVALID) 108 eflag = FP_EX_INVALID; 109 else if(eflag & FP_EX_OVERFLOW) 110 eflag = FP_EX_OVERFLOW; 111 else if(eflag & FP_EX_UNDERFLOW) 112 eflag = FP_EX_UNDERFLOW; 113 else if(eflag & FP_EX_DIVZERO) 114 eflag = FP_EX_DIVZERO; 115 else if(eflag & FP_EX_INEXACT) 116 eflag = FP_EX_INEXACT; 117 } 118 } 119 120 /* Set CEXC, here is the rule: 121 * 122 * In general all FPU ops will set one and only one 123 * bit in the CEXC field, this is always the case 124 * when the IEEE exception trap is enabled in TEM. 125 */ 126 fsr &= ~(FSR_CEXC_MASK); 127 fsr |= ((long)eflag << FSR_CEXC_SHIFT); 128 129 /* Set the AEXC field, rule is: 130 * 131 * If a trap would not be generated, the 132 * CEXC just generated is OR'd into the 133 * existing value of AEXC. 134 */ 135 if(would_trap == 0) 136 fsr |= ((long)eflag << FSR_AEXC_SHIFT); 137 138 /* If trapping, indicate fault trap type IEEE. */ 139 if(would_trap != 0) 140 fsr |= (1UL << 14); 141 142 current_thread_info()->xfsr[0] = fsr; 143 144 /* If we will not trap, advance the program counter over 145 * the instruction being handled. 146 */ 147 if(would_trap == 0) { 148 regs->tpc = regs->tnpc; 149 regs->tnpc += 4; 150 } 151 152 return (would_trap ? 0 : 1); 153} 154 155typedef union { 156 u32 s; 157 u64 d; 158 u64 q[2]; 159} *argp; 160 161int do_mathemu(struct pt_regs *regs, struct fpustate *f) 162{ 163 unsigned long pc = regs->tpc; 164 unsigned long tstate = regs->tstate; 165 u32 insn = 0; 166 int type = 0; 167 /* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells 168 whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack) 169 non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */ 170#define TYPE(ftt, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6) | (ftt << 9) 171 int freg; 172 static u64 zero[2] = { 0L, 0L }; 173 int flags; 174 FP_DECL_EX; 175 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); 176 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR); 177 FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR); 178 int IR; 179 long XR, xfsr; 180 181 if (tstate & TSTATE_PRIV) 182 die_if_kernel("unfinished/unimplemented FPop from kernel", regs); 183 if (test_thread_flag(TIF_32BIT)) 184 pc = (u32)pc; 185 if (get_user(insn, (u32 __user *) pc) != -EFAULT) { 186 if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ { 187 switch ((insn >> 5) & 0x1ff) { 188 /* QUAD - ftt == 3 */ 189 case FMOVQ: 190 case FNEGQ: 191 case FABSQ: TYPE(3,3,0,3,0,0,0); break; 192 case FSQRTQ: TYPE(3,3,1,3,1,0,0); break; 193 case FADDQ: 194 case FSUBQ: 195 case FMULQ: 196 case FDIVQ: TYPE(3,3,1,3,1,3,1); break; 197 case FDMULQ: TYPE(3,3,1,2,1,2,1); break; 198 case FQTOX: TYPE(3,2,0,3,1,0,0); break; 199 case FXTOQ: TYPE(3,3,1,2,0,0,0); break; 200 case FQTOS: TYPE(3,1,1,3,1,0,0); break; 201 case FQTOD: TYPE(3,2,1,3,1,0,0); break; 202 case FITOQ: TYPE(3,3,1,1,0,0,0); break; 203 case FSTOQ: TYPE(3,3,1,1,1,0,0); break; 204 case FDTOQ: TYPE(3,3,1,2,1,0,0); break; 205 case FQTOI: TYPE(3,1,0,3,1,0,0); break; 206 207 /* We can get either unimplemented or unfinished 208 * for these cases. Pre-Niagara systems generate 209 * unfinished fpop for SUBNORMAL cases, and Niagara 210 * always gives unimplemented fpop for fsqrt{s,d}. 211 */ 212 case FSQRTS: { 213 unsigned long x = current_thread_info()->xfsr[0]; 214 215 x = (x >> 14) & 0xf; 216 TYPE(x,1,1,1,1,0,0); 217 break; 218 } 219 220 case FSQRTD: { 221 unsigned long x = current_thread_info()->xfsr[0]; 222 223 x = (x >> 14) & 0xf; 224 TYPE(x,2,1,2,1,0,0); 225 break; 226 } 227 228 /* SUBNORMAL - ftt == 2 */ 229 case FADDD: 230 case FSUBD: 231 case FMULD: 232 case FDIVD: TYPE(2,2,1,2,1,2,1); break; 233 case FADDS: 234 case FSUBS: 235 case FMULS: 236 case FDIVS: TYPE(2,1,1,1,1,1,1); break; 237 case FSMULD: TYPE(2,2,1,1,1,1,1); break; 238 case FSTOX: TYPE(2,2,0,1,1,0,0); break; 239 case FDTOX: TYPE(2,2,0,2,1,0,0); break; 240 case FDTOS: TYPE(2,1,1,2,1,0,0); break; 241 case FSTOD: TYPE(2,2,1,1,1,0,0); break; 242 case FSTOI: TYPE(2,1,0,1,1,0,0); break; 243 case FDTOI: TYPE(2,1,0,2,1,0,0); break; 244 245 /* Only Ultra-III generates these */ 246 case FXTOS: TYPE(2,1,1,2,0,0,0); break; 247 case FXTOD: TYPE(2,2,1,2,0,0,0); break; 248 case FITOD: TYPE(2,2,1,1,0,0,0); break; 249 } 250 } 251 else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ { 252 IR = 2; 253 switch ((insn >> 5) & 0x1ff) { 254 case FCMPQ: TYPE(3,0,0,3,1,3,1); break; 255 case FCMPEQ: TYPE(3,0,0,3,1,3,1); break; 256 /* Now the conditional fmovq support */ 257 case FMOVQ0: 258 case FMOVQ1: 259 case FMOVQ2: 260 case FMOVQ3: 261 /* fmovq %fccX, %fY, %fZ */ 262 if (!((insn >> 11) & 3)) 263 XR = current_thread_info()->xfsr[0] >> 10; 264 else 265 XR = current_thread_info()->xfsr[0] >> (30 + ((insn >> 10) & 0x6)); 266 XR &= 3; 267 IR = 0; 268 switch ((insn >> 14) & 0x7) { 269 /* case 0: IR = 0; break; */ /* Never */ 270 case 1: if (XR) IR = 1; break; /* Not Equal */ 271 case 2: if (XR == 1 || XR == 2) IR = 1; break; /* Less or Greater */ 272 case 3: if (XR & 1) IR = 1; break; /* Unordered or Less */ 273 case 4: if (XR == 1) IR = 1; break; /* Less */ 274 case 5: if (XR & 2) IR = 1; break; /* Unordered or Greater */ 275 case 6: if (XR == 2) IR = 1; break; /* Greater */ 276 case 7: if (XR == 3) IR = 1; break; /* Unordered */ 277 } 278 if ((insn >> 14) & 8) 279 IR ^= 1; 280 break; 281 case FMOVQI: 282 case FMOVQX: 283 /* fmovq %[ix]cc, %fY, %fZ */ 284 XR = regs->tstate >> 32; 285 if ((insn >> 5) & 0x80) 286 XR >>= 4; 287 XR &= 0xf; 288 IR = 0; 289 freg = ((XR >> 2) ^ XR) & 2; 290 switch ((insn >> 14) & 0x7) { 291 /* case 0: IR = 0; break; */ /* Never */ 292 case 1: if (XR & 4) IR = 1; break; /* Equal */ 293 case 2: if ((XR & 4) || freg) IR = 1; break; /* Less or Equal */ 294 case 3: if (freg) IR = 1; break; /* Less */ 295 case 4: if (XR & 5) IR = 1; break; /* Less or Equal Unsigned */ 296 case 5: if (XR & 1) IR = 1; break; /* Carry Set */ 297 case 6: if (XR & 8) IR = 1; break; /* Negative */ 298 case 7: if (XR & 2) IR = 1; break; /* Overflow Set */ 299 } 300 if ((insn >> 14) & 8) 301 IR ^= 1; 302 break; 303 case FMOVQZ: 304 case FMOVQLE: 305 case FMOVQLZ: 306 case FMOVQNZ: 307 case FMOVQGZ: 308 case FMOVQGE: 309 freg = (insn >> 14) & 0x1f; 310 if (!freg) 311 XR = 0; 312 else if (freg < 16) 313 XR = regs->u_regs[freg]; 314 else if (test_thread_flag(TIF_32BIT)) { 315 struct reg_window32 __user *win32; 316 flushw_user (); 317 win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP])); 318 get_user(XR, &win32->locals[freg - 16]); 319 } else { 320 struct reg_window __user *win; 321 flushw_user (); 322 win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS); 323 get_user(XR, &win->locals[freg - 16]); 324 } 325 IR = 0; 326 switch ((insn >> 10) & 3) { 327 case 1: if (!XR) IR = 1; break; /* Register Zero */ 328 case 2: if (XR <= 0) IR = 1; break; /* Register Less Than or Equal to Zero */ 329 case 3: if (XR < 0) IR = 1; break; /* Register Less Than Zero */ 330 } 331 if ((insn >> 10) & 4) 332 IR ^= 1; 333 break; 334 } 335 if (IR == 0) { 336 /* The fmov test was false. Do a nop instead */ 337 current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK); 338 regs->tpc = regs->tnpc; 339 regs->tnpc += 4; 340 return 1; 341 } else if (IR == 1) { 342 /* Change the instruction into plain fmovq */ 343 insn = (insn & 0x3e00001f) | 0x81a00060; 344 TYPE(3,3,0,3,0,0,0); 345 } 346 } 347 } 348 if (type) { 349 argp rs1 = NULL, rs2 = NULL, rd = NULL; 350 351 freg = (current_thread_info()->xfsr[0] >> 14) & 0xf; 352 if (freg != (type >> 9)) 353 goto err; 354 current_thread_info()->xfsr[0] &= ~0x1c000; 355 freg = ((insn >> 14) & 0x1f); 356 switch (type & 0x3) { 357 case 3: if (freg & 2) { 358 current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */; 359 goto err; 360 } 361 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e); 362 case 1: rs1 = (argp)&f->regs[freg]; 363 flags = (freg < 32) ? FPRS_DL : FPRS_DU; 364 if (!(current_thread_info()->fpsaved[0] & flags)) 365 rs1 = (argp)&zero; 366 break; 367 } 368 switch (type & 0x7) { 369 case 7: FP_UNPACK_QP (QA, rs1); break; 370 case 6: FP_UNPACK_DP (DA, rs1); break; 371 case 5: FP_UNPACK_SP (SA, rs1); break; 372 } 373 freg = (insn & 0x1f); 374 switch ((type >> 3) & 0x3) { 375 case 3: if (freg & 2) { 376 current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */; 377 goto err; 378 } 379 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e); 380 case 1: rs2 = (argp)&f->regs[freg]; 381 flags = (freg < 32) ? FPRS_DL : FPRS_DU; 382 if (!(current_thread_info()->fpsaved[0] & flags)) 383 rs2 = (argp)&zero; 384 break; 385 } 386 switch ((type >> 3) & 0x7) { 387 case 7: FP_UNPACK_QP (QB, rs2); break; 388 case 6: FP_UNPACK_DP (DB, rs2); break; 389 case 5: FP_UNPACK_SP (SB, rs2); break; 390 } 391 freg = ((insn >> 25) & 0x1f); 392 switch ((type >> 6) & 0x3) { 393 case 3: if (freg & 2) { 394 current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */; 395 goto err; 396 } 397 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e); 398 case 1: rd = (argp)&f->regs[freg]; 399 flags = (freg < 32) ? FPRS_DL : FPRS_DU; 400 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) { 401 current_thread_info()->fpsaved[0] = FPRS_FEF; 402 current_thread_info()->gsr[0] = 0; 403 } 404 if (!(current_thread_info()->fpsaved[0] & flags)) { 405 if (freg < 32) 406 memset(f->regs, 0, 32*sizeof(u32)); 407 else 408 memset(f->regs+32, 0, 32*sizeof(u32)); 409 } 410 current_thread_info()->fpsaved[0] |= flags; 411 break; 412 } 413 switch ((insn >> 5) & 0x1ff) { 414 /* + */ 415 case FADDS: FP_ADD_S (SR, SA, SB); break; 416 case FADDD: FP_ADD_D (DR, DA, DB); break; 417 case FADDQ: FP_ADD_Q (QR, QA, QB); break; 418 /* - */ 419 case FSUBS: FP_SUB_S (SR, SA, SB); break; 420 case FSUBD: FP_SUB_D (DR, DA, DB); break; 421 case FSUBQ: FP_SUB_Q (QR, QA, QB); break; 422 /* * */ 423 case FMULS: FP_MUL_S (SR, SA, SB); break; 424 case FSMULD: FP_CONV (D, S, 1, 1, DA, SA); 425 FP_CONV (D, S, 1, 1, DB, SB); 426 case FMULD: FP_MUL_D (DR, DA, DB); break; 427 case FDMULQ: FP_CONV (Q, D, 2, 1, QA, DA); 428 FP_CONV (Q, D, 2, 1, QB, DB); 429 case FMULQ: FP_MUL_Q (QR, QA, QB); break; 430 /* / */ 431 case FDIVS: FP_DIV_S (SR, SA, SB); break; 432 case FDIVD: FP_DIV_D (DR, DA, DB); break; 433 case FDIVQ: FP_DIV_Q (QR, QA, QB); break; 434 /* sqrt */ 435 case FSQRTS: FP_SQRT_S (SR, SB); break; 436 case FSQRTD: FP_SQRT_D (DR, DB); break; 437 case FSQRTQ: FP_SQRT_Q (QR, QB); break; 438 /* mov */ 439 case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break; 440 case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break; 441 case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break; 442 /* float to int */ 443 case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break; 444 case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break; 445 case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break; 446 case FSTOX: FP_TO_INT_S (XR, SB, 64, 1); break; 447 case FDTOX: FP_TO_INT_D (XR, DB, 64, 1); break; 448 case FQTOX: FP_TO_INT_Q (XR, QB, 64, 1); break; 449 /* int to float */ 450 case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break; 451 case FXTOQ: XR = rs2->d; FP_FROM_INT_Q (QR, XR, 64, long); break; 452 /* Only Ultra-III generates these */ 453 case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break; 454 case FXTOD: XR = rs2->d; FP_FROM_INT_D (DR, XR, 64, long); break; 455 case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break; 456 /* float to float */ 457 case FSTOD: FP_CONV (D, S, 1, 1, DR, SB); break; 458 case FSTOQ: FP_CONV (Q, S, 2, 1, QR, SB); break; 459 case FDTOQ: FP_CONV (Q, D, 2, 1, QR, DB); break; 460 case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break; 461 case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break; 462 case FQTOD: FP_CONV (D, Q, 1, 2, DR, QB); break; 463 /* comparison */ 464 case FCMPQ: 465 case FCMPEQ: 466 FP_CMP_Q(XR, QB, QA, 3); 467 if (XR == 3 && 468 (((insn >> 5) & 0x1ff) == FCMPEQ || 469 FP_ISSIGNAN_Q(QA) || 470 FP_ISSIGNAN_Q(QB))) 471 FP_SET_EXCEPTION (FP_EX_INVALID); 472 } 473 if (!FP_INHIBIT_RESULTS) { 474 switch ((type >> 6) & 0x7) { 475 case 0: xfsr = current_thread_info()->xfsr[0]; 476 if (XR == -1) XR = 2; 477 switch (freg & 3) { 478 /* fcc0, 1, 2, 3 */ 479 case 0: xfsr &= ~0xc00; xfsr |= (XR << 10); break; 480 case 1: xfsr &= ~0x300000000UL; xfsr |= (XR << 32); break; 481 case 2: xfsr &= ~0xc00000000UL; xfsr |= (XR << 34); break; 482 case 3: xfsr &= ~0x3000000000UL; xfsr |= (XR << 36); break; 483 } 484 current_thread_info()->xfsr[0] = xfsr; 485 break; 486 case 1: rd->s = IR; break; 487 case 2: rd->d = XR; break; 488 case 5: FP_PACK_SP (rd, SR); break; 489 case 6: FP_PACK_DP (rd, DR); break; 490 case 7: FP_PACK_QP (rd, QR); break; 491 } 492 } 493 494 if(_fex != 0) 495 return record_exception(regs, _fex); 496 497 /* Success and no exceptions detected. */ 498 current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK); 499 regs->tpc = regs->tnpc; 500 regs->tnpc += 4; 501 return 1; 502 } 503err: return 0; 504} 505