1/* $Id: sbus.c,v 1.1.1.1 2007/08/03 18:52:18 Exp $ 2 * sbus.c: UltraSparc SBUS controller support. 3 * 4 * Copyright (C) 1999 David S. Miller (davem@redhat.com) 5 */ 6 7#include <linux/kernel.h> 8#include <linux/types.h> 9#include <linux/mm.h> 10#include <linux/spinlock.h> 11#include <linux/slab.h> 12#include <linux/init.h> 13#include <linux/interrupt.h> 14 15#include <asm/page.h> 16#include <asm/sbus.h> 17#include <asm/io.h> 18#include <asm/upa.h> 19#include <asm/cache.h> 20#include <asm/dma.h> 21#include <asm/irq.h> 22#include <asm/prom.h> 23#include <asm/starfire.h> 24 25#include "iommu_common.h" 26 27#define MAP_BASE ((u32)0xc0000000) 28 29struct sbus_info { 30 struct iommu iommu; 31 struct strbuf strbuf; 32}; 33 34/* Offsets from iommu_regs */ 35#define SYSIO_IOMMUREG_BASE 0x2400UL 36#define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */ 37#define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */ 38#define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */ 39#define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */ 40#define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */ 41#define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */ 42#define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */ 43#define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */ 44 45#define IOMMU_DRAM_VALID (1UL << 30UL) 46 47static void __iommu_flushall(struct iommu *iommu) 48{ 49 unsigned long tag; 50 int entry; 51 52 tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL); 53 for (entry = 0; entry < 16; entry++) { 54 upa_writeq(0, tag); 55 tag += 8UL; 56 } 57 upa_readq(iommu->write_complete_reg); 58} 59 60/* Offsets from strbuf_regs */ 61#define SYSIO_STRBUFREG_BASE 0x2800UL 62#define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */ 63#define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */ 64#define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */ 65#define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */ 66#define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */ 67#define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */ 68#define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */ 69 70#define STRBUF_TAG_VALID 0x02UL 71 72static void sbus_strbuf_flush(struct iommu *iommu, struct strbuf *strbuf, u32 base, unsigned long npages, int direction) 73{ 74 unsigned long n; 75 int limit; 76 77 n = npages; 78 while (n--) 79 upa_writeq(base + (n << IO_PAGE_SHIFT), strbuf->strbuf_pflush); 80 81 /* If the device could not have possibly put dirty data into 82 * the streaming cache, no flush-flag synchronization needs 83 * to be performed. 84 */ 85 if (direction == SBUS_DMA_TODEVICE) 86 return; 87 88 *(strbuf->strbuf_flushflag) = 0UL; 89 90 /* Whoopee cushion! */ 91 upa_writeq(strbuf->strbuf_flushflag_pa, strbuf->strbuf_fsync); 92 upa_readq(iommu->write_complete_reg); 93 94 limit = 100000; 95 while (*(strbuf->strbuf_flushflag) == 0UL) { 96 limit--; 97 if (!limit) 98 break; 99 udelay(1); 100 rmb(); 101 } 102 if (!limit) 103 printk(KERN_WARNING "sbus_strbuf_flush: flushflag timeout " 104 "vaddr[%08x] npages[%ld]\n", 105 base, npages); 106} 107 108/* Based largely upon the ppc64 iommu allocator. */ 109static long sbus_arena_alloc(struct iommu *iommu, unsigned long npages) 110{ 111 struct iommu_arena *arena = &iommu->arena; 112 unsigned long n, i, start, end, limit; 113 int pass; 114 115 limit = arena->limit; 116 start = arena->hint; 117 pass = 0; 118 119again: 120 n = find_next_zero_bit(arena->map, limit, start); 121 end = n + npages; 122 if (unlikely(end >= limit)) { 123 if (likely(pass < 1)) { 124 limit = start; 125 start = 0; 126 __iommu_flushall(iommu); 127 pass++; 128 goto again; 129 } else { 130 /* Scanned the whole thing, give up. */ 131 return -1; 132 } 133 } 134 135 for (i = n; i < end; i++) { 136 if (test_bit(i, arena->map)) { 137 start = i + 1; 138 goto again; 139 } 140 } 141 142 for (i = n; i < end; i++) 143 __set_bit(i, arena->map); 144 145 arena->hint = end; 146 147 return n; 148} 149 150static void sbus_arena_free(struct iommu_arena *arena, unsigned long base, unsigned long npages) 151{ 152 unsigned long i; 153 154 for (i = base; i < (base + npages); i++) 155 __clear_bit(i, arena->map); 156} 157 158static void sbus_iommu_table_init(struct iommu *iommu, unsigned int tsbsize) 159{ 160 unsigned long tsbbase, order, sz, num_tsb_entries; 161 162 num_tsb_entries = tsbsize / sizeof(iopte_t); 163 164 /* Setup initial software IOMMU state. */ 165 spin_lock_init(&iommu->lock); 166 iommu->page_table_map_base = MAP_BASE; 167 168 /* Allocate and initialize the free area map. */ 169 sz = num_tsb_entries / 8; 170 sz = (sz + 7UL) & ~7UL; 171 iommu->arena.map = kzalloc(sz, GFP_KERNEL); 172 if (!iommu->arena.map) { 173 prom_printf("SBUS_IOMMU: Error, kmalloc(arena.map) failed.\n"); 174 prom_halt(); 175 } 176 iommu->arena.limit = num_tsb_entries; 177 178 /* Now allocate and setup the IOMMU page table itself. */ 179 order = get_order(tsbsize); 180 tsbbase = __get_free_pages(GFP_KERNEL, order); 181 if (!tsbbase) { 182 prom_printf("IOMMU: Error, gfp(tsb) failed.\n"); 183 prom_halt(); 184 } 185 iommu->page_table = (iopte_t *)tsbbase; 186 memset(iommu->page_table, 0, tsbsize); 187} 188 189static inline iopte_t *alloc_npages(struct iommu *iommu, unsigned long npages) 190{ 191 long entry; 192 193 entry = sbus_arena_alloc(iommu, npages); 194 if (unlikely(entry < 0)) 195 return NULL; 196 197 return iommu->page_table + entry; 198} 199 200static inline void free_npages(struct iommu *iommu, dma_addr_t base, unsigned long npages) 201{ 202 sbus_arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages); 203} 204 205void *sbus_alloc_consistent(struct sbus_dev *sdev, size_t size, dma_addr_t *dvma_addr) 206{ 207 struct sbus_info *info; 208 struct iommu *iommu; 209 iopte_t *iopte; 210 unsigned long flags, order, first_page; 211 void *ret; 212 int npages; 213 214 size = IO_PAGE_ALIGN(size); 215 order = get_order(size); 216 if (order >= 10) 217 return NULL; 218 219 first_page = __get_free_pages(GFP_KERNEL|__GFP_COMP, order); 220 if (first_page == 0UL) 221 return NULL; 222 memset((char *)first_page, 0, PAGE_SIZE << order); 223 224 info = sdev->bus->iommu; 225 iommu = &info->iommu; 226 227 spin_lock_irqsave(&iommu->lock, flags); 228 iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT); 229 spin_unlock_irqrestore(&iommu->lock, flags); 230 231 if (unlikely(iopte == NULL)) { 232 free_pages(first_page, order); 233 return NULL; 234 } 235 236 *dvma_addr = (iommu->page_table_map_base + 237 ((iopte - iommu->page_table) << IO_PAGE_SHIFT)); 238 ret = (void *) first_page; 239 npages = size >> IO_PAGE_SHIFT; 240 first_page = __pa(first_page); 241 while (npages--) { 242 iopte_val(*iopte) = (IOPTE_VALID | IOPTE_CACHE | 243 IOPTE_WRITE | 244 (first_page & IOPTE_PAGE)); 245 iopte++; 246 first_page += IO_PAGE_SIZE; 247 } 248 249 return ret; 250} 251 252void sbus_free_consistent(struct sbus_dev *sdev, size_t size, void *cpu, dma_addr_t dvma) 253{ 254 struct sbus_info *info; 255 struct iommu *iommu; 256 iopte_t *iopte; 257 unsigned long flags, order, npages; 258 259 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; 260 info = sdev->bus->iommu; 261 iommu = &info->iommu; 262 iopte = iommu->page_table + 263 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT); 264 265 spin_lock_irqsave(&iommu->lock, flags); 266 267 free_npages(iommu, dvma - iommu->page_table_map_base, npages); 268 269 spin_unlock_irqrestore(&iommu->lock, flags); 270 271 order = get_order(size); 272 if (order < 10) 273 free_pages((unsigned long)cpu, order); 274} 275 276dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr, size_t sz, int direction) 277{ 278 struct sbus_info *info; 279 struct iommu *iommu; 280 iopte_t *base; 281 unsigned long flags, npages, oaddr; 282 unsigned long i, base_paddr; 283 u32 bus_addr, ret; 284 unsigned long iopte_protection; 285 286 info = sdev->bus->iommu; 287 iommu = &info->iommu; 288 289 if (unlikely(direction == SBUS_DMA_NONE)) 290 BUG(); 291 292 oaddr = (unsigned long)ptr; 293 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); 294 npages >>= IO_PAGE_SHIFT; 295 296 spin_lock_irqsave(&iommu->lock, flags); 297 base = alloc_npages(iommu, npages); 298 spin_unlock_irqrestore(&iommu->lock, flags); 299 300 if (unlikely(!base)) 301 BUG(); 302 303 bus_addr = (iommu->page_table_map_base + 304 ((base - iommu->page_table) << IO_PAGE_SHIFT)); 305 ret = bus_addr | (oaddr & ~IO_PAGE_MASK); 306 base_paddr = __pa(oaddr & IO_PAGE_MASK); 307 308 iopte_protection = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE; 309 if (direction != SBUS_DMA_TODEVICE) 310 iopte_protection |= IOPTE_WRITE; 311 312 for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE) 313 iopte_val(*base) = iopte_protection | base_paddr; 314 315 return ret; 316} 317 318void sbus_unmap_single(struct sbus_dev *sdev, dma_addr_t bus_addr, size_t sz, int direction) 319{ 320 struct sbus_info *info = sdev->bus->iommu; 321 struct iommu *iommu = &info->iommu; 322 struct strbuf *strbuf = &info->strbuf; 323 iopte_t *base; 324 unsigned long flags, npages, i; 325 326 if (unlikely(direction == SBUS_DMA_NONE)) 327 BUG(); 328 329 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); 330 npages >>= IO_PAGE_SHIFT; 331 base = iommu->page_table + 332 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT); 333 334 bus_addr &= IO_PAGE_MASK; 335 336 spin_lock_irqsave(&iommu->lock, flags); 337 sbus_strbuf_flush(iommu, strbuf, bus_addr, npages, direction); 338 for (i = 0; i < npages; i++) 339 iopte_val(base[i]) = 0UL; 340 free_npages(iommu, bus_addr - iommu->page_table_map_base, npages); 341 spin_unlock_irqrestore(&iommu->lock, flags); 342} 343 344#define SG_ENT_PHYS_ADDRESS(SG) \ 345 (__pa(page_address((SG)->page)) + (SG)->offset) 346 347static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg, 348 int nused, int nelems, unsigned long iopte_protection) 349{ 350 struct scatterlist *dma_sg = sg; 351 struct scatterlist *sg_end = sg + nelems; 352 int i; 353 354 for (i = 0; i < nused; i++) { 355 unsigned long pteval = ~0UL; 356 u32 dma_npages; 357 358 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) + 359 dma_sg->dma_length + 360 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT; 361 do { 362 unsigned long offset; 363 signed int len; 364 365 /* If we are here, we know we have at least one 366 * more page to map. So walk forward until we 367 * hit a page crossing, and begin creating new 368 * mappings from that spot. 369 */ 370 for (;;) { 371 unsigned long tmp; 372 373 tmp = SG_ENT_PHYS_ADDRESS(sg); 374 len = sg->length; 375 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) { 376 pteval = tmp & IO_PAGE_MASK; 377 offset = tmp & (IO_PAGE_SIZE - 1UL); 378 break; 379 } 380 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) { 381 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK; 382 offset = 0UL; 383 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL))); 384 break; 385 } 386 sg++; 387 } 388 389 pteval = iopte_protection | (pteval & IOPTE_PAGE); 390 while (len > 0) { 391 *iopte++ = __iopte(pteval); 392 pteval += IO_PAGE_SIZE; 393 len -= (IO_PAGE_SIZE - offset); 394 offset = 0; 395 dma_npages--; 396 } 397 398 pteval = (pteval & IOPTE_PAGE) + len; 399 sg++; 400 401 /* Skip over any tail mappings we've fully mapped, 402 * adjusting pteval along the way. Stop when we 403 * detect a page crossing event. 404 */ 405 while (sg < sg_end && 406 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL && 407 (pteval == SG_ENT_PHYS_ADDRESS(sg)) && 408 ((pteval ^ 409 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) { 410 pteval += sg->length; 411 sg++; 412 } 413 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL) 414 pteval = ~0UL; 415 } while (dma_npages != 0); 416 dma_sg++; 417 } 418} 419 420int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems, int direction) 421{ 422 struct sbus_info *info; 423 struct iommu *iommu; 424 unsigned long flags, npages, iopte_protection; 425 iopte_t *base; 426 u32 dma_base; 427 struct scatterlist *sgtmp; 428 int used; 429 430 /* Fast path single entry scatterlists. */ 431 if (nelems == 1) { 432 sglist->dma_address = 433 sbus_map_single(sdev, 434 (page_address(sglist->page) + sglist->offset), 435 sglist->length, direction); 436 sglist->dma_length = sglist->length; 437 return 1; 438 } 439 440 info = sdev->bus->iommu; 441 iommu = &info->iommu; 442 443 if (unlikely(direction == SBUS_DMA_NONE)) 444 BUG(); 445 446 npages = prepare_sg(sglist, nelems); 447 448 spin_lock_irqsave(&iommu->lock, flags); 449 base = alloc_npages(iommu, npages); 450 spin_unlock_irqrestore(&iommu->lock, flags); 451 452 if (unlikely(base == NULL)) 453 BUG(); 454 455 dma_base = iommu->page_table_map_base + 456 ((base - iommu->page_table) << IO_PAGE_SHIFT); 457 458 /* Normalize DVMA addresses. */ 459 used = nelems; 460 461 sgtmp = sglist; 462 while (used && sgtmp->dma_length) { 463 sgtmp->dma_address += dma_base; 464 sgtmp++; 465 used--; 466 } 467 used = nelems - used; 468 469 iopte_protection = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE; 470 if (direction != SBUS_DMA_TODEVICE) 471 iopte_protection |= IOPTE_WRITE; 472 473 fill_sg(base, sglist, used, nelems, iopte_protection); 474 475#ifdef VERIFY_SG 476 verify_sglist(sglist, nelems, base, npages); 477#endif 478 479 return used; 480} 481 482void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems, int direction) 483{ 484 struct sbus_info *info; 485 struct iommu *iommu; 486 struct strbuf *strbuf; 487 iopte_t *base; 488 unsigned long flags, i, npages; 489 u32 bus_addr; 490 491 if (unlikely(direction == SBUS_DMA_NONE)) 492 BUG(); 493 494 info = sdev->bus->iommu; 495 iommu = &info->iommu; 496 strbuf = &info->strbuf; 497 498 bus_addr = sglist->dma_address & IO_PAGE_MASK; 499 500 for (i = 1; i < nelems; i++) 501 if (sglist[i].dma_length == 0) 502 break; 503 i--; 504 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) - 505 bus_addr) >> IO_PAGE_SHIFT; 506 507 base = iommu->page_table + 508 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT); 509 510 spin_lock_irqsave(&iommu->lock, flags); 511 sbus_strbuf_flush(iommu, strbuf, bus_addr, npages, direction); 512 for (i = 0; i < npages; i++) 513 iopte_val(base[i]) = 0UL; 514 free_npages(iommu, bus_addr - iommu->page_table_map_base, npages); 515 spin_unlock_irqrestore(&iommu->lock, flags); 516} 517 518void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev, dma_addr_t bus_addr, size_t sz, int direction) 519{ 520 struct sbus_info *info; 521 struct iommu *iommu; 522 struct strbuf *strbuf; 523 unsigned long flags, npages; 524 525 info = sdev->bus->iommu; 526 iommu = &info->iommu; 527 strbuf = &info->strbuf; 528 529 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); 530 npages >>= IO_PAGE_SHIFT; 531 bus_addr &= IO_PAGE_MASK; 532 533 spin_lock_irqsave(&iommu->lock, flags); 534 sbus_strbuf_flush(iommu, strbuf, bus_addr, npages, direction); 535 spin_unlock_irqrestore(&iommu->lock, flags); 536} 537 538void sbus_dma_sync_single_for_device(struct sbus_dev *sdev, dma_addr_t base, size_t size, int direction) 539{ 540} 541 542void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems, int direction) 543{ 544 struct sbus_info *info; 545 struct iommu *iommu; 546 struct strbuf *strbuf; 547 unsigned long flags, npages, i; 548 u32 bus_addr; 549 550 info = sdev->bus->iommu; 551 iommu = &info->iommu; 552 strbuf = &info->strbuf; 553 554 bus_addr = sglist[0].dma_address & IO_PAGE_MASK; 555 for (i = 0; i < nelems; i++) { 556 if (!sglist[i].dma_length) 557 break; 558 } 559 i--; 560 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) 561 - bus_addr) >> IO_PAGE_SHIFT; 562 563 spin_lock_irqsave(&iommu->lock, flags); 564 sbus_strbuf_flush(iommu, strbuf, bus_addr, npages, direction); 565 spin_unlock_irqrestore(&iommu->lock, flags); 566} 567 568void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction) 569{ 570} 571 572/* Enable 64-bit DVMA mode for the given device. */ 573void sbus_set_sbus64(struct sbus_dev *sdev, int bursts) 574{ 575 struct sbus_info *info = sdev->bus->iommu; 576 struct iommu *iommu = &info->iommu; 577 int slot = sdev->slot; 578 unsigned long cfg_reg; 579 u64 val; 580 581 cfg_reg = iommu->write_complete_reg; 582 switch (slot) { 583 case 0: 584 cfg_reg += 0x20UL; 585 break; 586 case 1: 587 cfg_reg += 0x28UL; 588 break; 589 case 2: 590 cfg_reg += 0x30UL; 591 break; 592 case 3: 593 cfg_reg += 0x38UL; 594 break; 595 case 13: 596 cfg_reg += 0x40UL; 597 break; 598 case 14: 599 cfg_reg += 0x48UL; 600 break; 601 case 15: 602 cfg_reg += 0x50UL; 603 break; 604 605 default: 606 return; 607 }; 608 609 val = upa_readq(cfg_reg); 610 if (val & (1UL << 14UL)) { 611 /* Extended transfer mode already enabled. */ 612 return; 613 } 614 615 val |= (1UL << 14UL); 616 617 if (bursts & DMA_BURST8) 618 val |= (1UL << 1UL); 619 if (bursts & DMA_BURST16) 620 val |= (1UL << 2UL); 621 if (bursts & DMA_BURST32) 622 val |= (1UL << 3UL); 623 if (bursts & DMA_BURST64) 624 val |= (1UL << 4UL); 625 upa_writeq(val, cfg_reg); 626} 627 628/* INO number to IMAP register offset for SYSIO external IRQ's. 629 * This should conform to both Sunfire/Wildfire server and Fusion 630 * desktop designs. 631 */ 632#define SYSIO_IMAP_SLOT0 0x2c00UL 633#define SYSIO_IMAP_SLOT1 0x2c08UL 634#define SYSIO_IMAP_SLOT2 0x2c10UL 635#define SYSIO_IMAP_SLOT3 0x2c18UL 636#define SYSIO_IMAP_SCSI 0x3000UL 637#define SYSIO_IMAP_ETH 0x3008UL 638#define SYSIO_IMAP_BPP 0x3010UL 639#define SYSIO_IMAP_AUDIO 0x3018UL 640#define SYSIO_IMAP_PFAIL 0x3020UL 641#define SYSIO_IMAP_KMS 0x3028UL 642#define SYSIO_IMAP_FLPY 0x3030UL 643#define SYSIO_IMAP_SHW 0x3038UL 644#define SYSIO_IMAP_KBD 0x3040UL 645#define SYSIO_IMAP_MS 0x3048UL 646#define SYSIO_IMAP_SER 0x3050UL 647#define SYSIO_IMAP_TIM0 0x3060UL 648#define SYSIO_IMAP_TIM1 0x3068UL 649#define SYSIO_IMAP_UE 0x3070UL 650#define SYSIO_IMAP_CE 0x3078UL 651#define SYSIO_IMAP_SBERR 0x3080UL 652#define SYSIO_IMAP_PMGMT 0x3088UL 653#define SYSIO_IMAP_GFX 0x3090UL 654#define SYSIO_IMAP_EUPA 0x3098UL 655 656#define bogon ((unsigned long) -1) 657static unsigned long sysio_irq_offsets[] = { 658 /* SBUS Slot 0 --> 3, level 1 --> 7 */ 659 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, 660 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, 661 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, 662 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, 663 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, 664 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, 665 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, 666 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, 667 668 /* Onboard devices (not relevant/used on SunFire). */ 669 SYSIO_IMAP_SCSI, 670 SYSIO_IMAP_ETH, 671 SYSIO_IMAP_BPP, 672 bogon, 673 SYSIO_IMAP_AUDIO, 674 SYSIO_IMAP_PFAIL, 675 bogon, 676 bogon, 677 SYSIO_IMAP_KMS, 678 SYSIO_IMAP_FLPY, 679 SYSIO_IMAP_SHW, 680 SYSIO_IMAP_KBD, 681 SYSIO_IMAP_MS, 682 SYSIO_IMAP_SER, 683 bogon, 684 bogon, 685 SYSIO_IMAP_TIM0, 686 SYSIO_IMAP_TIM1, 687 bogon, 688 bogon, 689 SYSIO_IMAP_UE, 690 SYSIO_IMAP_CE, 691 SYSIO_IMAP_SBERR, 692 SYSIO_IMAP_PMGMT, 693}; 694 695#undef bogon 696 697#define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets) 698 699/* Convert Interrupt Mapping register pointer to associated 700 * Interrupt Clear register pointer, SYSIO specific version. 701 */ 702#define SYSIO_ICLR_UNUSED0 0x3400UL 703#define SYSIO_ICLR_SLOT0 0x3408UL 704#define SYSIO_ICLR_SLOT1 0x3448UL 705#define SYSIO_ICLR_SLOT2 0x3488UL 706#define SYSIO_ICLR_SLOT3 0x34c8UL 707static unsigned long sysio_imap_to_iclr(unsigned long imap) 708{ 709 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0; 710 return imap + diff; 711} 712 713unsigned int sbus_build_irq(void *buscookie, unsigned int ino) 714{ 715 struct sbus_bus *sbus = (struct sbus_bus *)buscookie; 716 struct sbus_info *info = sbus->iommu; 717 struct iommu *iommu = &info->iommu; 718 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 719 unsigned long imap, iclr; 720 int sbus_level = 0; 721 722 imap = sysio_irq_offsets[ino]; 723 if (imap == ((unsigned long)-1)) { 724 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n", 725 ino); 726 prom_halt(); 727 } 728 imap += reg_base; 729 730 /* SYSIO inconsistency. For external SLOTS, we have to select 731 * the right ICLR register based upon the lower SBUS irq level 732 * bits. 733 */ 734 if (ino >= 0x20) { 735 iclr = sysio_imap_to_iclr(imap); 736 } else { 737 int sbus_slot = (ino & 0x18)>>3; 738 739 sbus_level = ino & 0x7; 740 741 switch(sbus_slot) { 742 case 0: 743 iclr = reg_base + SYSIO_ICLR_SLOT0; 744 break; 745 case 1: 746 iclr = reg_base + SYSIO_ICLR_SLOT1; 747 break; 748 case 2: 749 iclr = reg_base + SYSIO_ICLR_SLOT2; 750 break; 751 default: 752 case 3: 753 iclr = reg_base + SYSIO_ICLR_SLOT3; 754 break; 755 }; 756 757 iclr += ((unsigned long)sbus_level - 1UL) * 8UL; 758 } 759 return build_irq(sbus_level, iclr, imap); 760} 761 762/* Error interrupt handling. */ 763#define SYSIO_UE_AFSR 0x0030UL 764#define SYSIO_UE_AFAR 0x0038UL 765#define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */ 766#define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */ 767#define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */ 768#define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ 769#define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */ 770#define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/ 771#define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ 772#define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */ 773#define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */ 774#define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */ 775#define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ 776static irqreturn_t sysio_ue_handler(int irq, void *dev_id) 777{ 778 struct sbus_bus *sbus = dev_id; 779 struct sbus_info *info = sbus->iommu; 780 struct iommu *iommu = &info->iommu; 781 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 782 unsigned long afsr_reg, afar_reg; 783 unsigned long afsr, afar, error_bits; 784 int reported; 785 786 afsr_reg = reg_base + SYSIO_UE_AFSR; 787 afar_reg = reg_base + SYSIO_UE_AFAR; 788 789 /* Latch error status. */ 790 afsr = upa_readq(afsr_reg); 791 afar = upa_readq(afar_reg); 792 793 /* Clear primary/secondary error status bits. */ 794 error_bits = afsr & 795 (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR | 796 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR); 797 upa_writeq(error_bits, afsr_reg); 798 799 /* Log the error. */ 800 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n", 801 sbus->portid, 802 (((error_bits & SYSIO_UEAFSR_PPIO) ? 803 "PIO" : 804 ((error_bits & SYSIO_UEAFSR_PDRD) ? 805 "DVMA Read" : 806 ((error_bits & SYSIO_UEAFSR_PDWR) ? 807 "DVMA Write" : "???"))))); 808 printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n", 809 sbus->portid, 810 (afsr & SYSIO_UEAFSR_DOFF) >> 45UL, 811 (afsr & SYSIO_UEAFSR_SIZE) >> 42UL, 812 (afsr & SYSIO_UEAFSR_MID) >> 37UL); 813 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar); 814 printk("SYSIO[%x]: Secondary UE errors [", sbus->portid); 815 reported = 0; 816 if (afsr & SYSIO_UEAFSR_SPIO) { 817 reported++; 818 printk("(PIO)"); 819 } 820 if (afsr & SYSIO_UEAFSR_SDRD) { 821 reported++; 822 printk("(DVMA Read)"); 823 } 824 if (afsr & SYSIO_UEAFSR_SDWR) { 825 reported++; 826 printk("(DVMA Write)"); 827 } 828 if (!reported) 829 printk("(none)"); 830 printk("]\n"); 831 832 return IRQ_HANDLED; 833} 834 835#define SYSIO_CE_AFSR 0x0040UL 836#define SYSIO_CE_AFAR 0x0048UL 837#define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */ 838#define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */ 839#define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */ 840#define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */ 841#define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */ 842#define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/ 843#define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ 844#define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ 845#define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */ 846#define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */ 847#define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */ 848#define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ 849static irqreturn_t sysio_ce_handler(int irq, void *dev_id) 850{ 851 struct sbus_bus *sbus = dev_id; 852 struct sbus_info *info = sbus->iommu; 853 struct iommu *iommu = &info->iommu; 854 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 855 unsigned long afsr_reg, afar_reg; 856 unsigned long afsr, afar, error_bits; 857 int reported; 858 859 afsr_reg = reg_base + SYSIO_CE_AFSR; 860 afar_reg = reg_base + SYSIO_CE_AFAR; 861 862 /* Latch error status. */ 863 afsr = upa_readq(afsr_reg); 864 afar = upa_readq(afar_reg); 865 866 /* Clear primary/secondary error status bits. */ 867 error_bits = afsr & 868 (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR | 869 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR); 870 upa_writeq(error_bits, afsr_reg); 871 872 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n", 873 sbus->portid, 874 (((error_bits & SYSIO_CEAFSR_PPIO) ? 875 "PIO" : 876 ((error_bits & SYSIO_CEAFSR_PDRD) ? 877 "DVMA Read" : 878 ((error_bits & SYSIO_CEAFSR_PDWR) ? 879 "DVMA Write" : "???"))))); 880 881 printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n", 882 sbus->portid, 883 (afsr & SYSIO_CEAFSR_DOFF) >> 45UL, 884 (afsr & SYSIO_CEAFSR_ESYND) >> 48UL, 885 (afsr & SYSIO_CEAFSR_SIZE) >> 42UL, 886 (afsr & SYSIO_CEAFSR_MID) >> 37UL); 887 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar); 888 889 printk("SYSIO[%x]: Secondary CE errors [", sbus->portid); 890 reported = 0; 891 if (afsr & SYSIO_CEAFSR_SPIO) { 892 reported++; 893 printk("(PIO)"); 894 } 895 if (afsr & SYSIO_CEAFSR_SDRD) { 896 reported++; 897 printk("(DVMA Read)"); 898 } 899 if (afsr & SYSIO_CEAFSR_SDWR) { 900 reported++; 901 printk("(DVMA Write)"); 902 } 903 if (!reported) 904 printk("(none)"); 905 printk("]\n"); 906 907 return IRQ_HANDLED; 908} 909 910#define SYSIO_SBUS_AFSR 0x2010UL 911#define SYSIO_SBUS_AFAR 0x2018UL 912#define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */ 913#define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */ 914#define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */ 915#define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */ 916#define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */ 917#define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */ 918#define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */ 919#define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */ 920#define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */ 921#define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */ 922#define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */ 923#define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */ 924static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id) 925{ 926 struct sbus_bus *sbus = dev_id; 927 struct sbus_info *info = sbus->iommu; 928 struct iommu *iommu = &info->iommu; 929 unsigned long afsr_reg, afar_reg, reg_base; 930 unsigned long afsr, afar, error_bits; 931 int reported; 932 933 reg_base = iommu->write_complete_reg - 0x2000UL; 934 afsr_reg = reg_base + SYSIO_SBUS_AFSR; 935 afar_reg = reg_base + SYSIO_SBUS_AFAR; 936 937 afsr = upa_readq(afsr_reg); 938 afar = upa_readq(afar_reg); 939 940 /* Clear primary/secondary error status bits. */ 941 error_bits = afsr & 942 (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR | 943 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR); 944 upa_writeq(error_bits, afsr_reg); 945 946 /* Log the error. */ 947 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n", 948 sbus->portid, 949 (((error_bits & SYSIO_SBAFSR_PLE) ? 950 "Late PIO Error" : 951 ((error_bits & SYSIO_SBAFSR_PTO) ? 952 "Time Out" : 953 ((error_bits & SYSIO_SBAFSR_PBERR) ? 954 "Error Ack" : "???")))), 955 (afsr & SYSIO_SBAFSR_RD) ? 1 : 0); 956 printk("SYSIO[%x]: size[%lx] MID[%lx]\n", 957 sbus->portid, 958 (afsr & SYSIO_SBAFSR_SIZE) >> 42UL, 959 (afsr & SYSIO_SBAFSR_MID) >> 37UL); 960 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar); 961 printk("SYSIO[%x]: Secondary SBUS errors [", sbus->portid); 962 reported = 0; 963 if (afsr & SYSIO_SBAFSR_SLE) { 964 reported++; 965 printk("(Late PIO Error)"); 966 } 967 if (afsr & SYSIO_SBAFSR_STO) { 968 reported++; 969 printk("(Time Out)"); 970 } 971 if (afsr & SYSIO_SBAFSR_SBERR) { 972 reported++; 973 printk("(Error Ack)"); 974 } 975 if (!reported) 976 printk("(none)"); 977 printk("]\n"); 978 979 980 return IRQ_HANDLED; 981} 982 983#define ECC_CONTROL 0x0020UL 984#define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */ 985#define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */ 986#define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */ 987 988#define SYSIO_UE_INO 0x34 989#define SYSIO_CE_INO 0x35 990#define SYSIO_SBUSERR_INO 0x36 991 992static void __init sysio_register_error_handlers(struct sbus_bus *sbus) 993{ 994 struct sbus_info *info = sbus->iommu; 995 struct iommu *iommu = &info->iommu; 996 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 997 unsigned int irq; 998 u64 control; 999 1000 irq = sbus_build_irq(sbus, SYSIO_UE_INO); 1001 if (request_irq(irq, sysio_ue_handler, 0, 1002 "SYSIO_UE", sbus) < 0) { 1003 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n", 1004 sbus->portid); 1005 prom_halt(); 1006 } 1007 1008 irq = sbus_build_irq(sbus, SYSIO_CE_INO); 1009 if (request_irq(irq, sysio_ce_handler, 0, 1010 "SYSIO_CE", sbus) < 0) { 1011 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n", 1012 sbus->portid); 1013 prom_halt(); 1014 } 1015 1016 irq = sbus_build_irq(sbus, SYSIO_SBUSERR_INO); 1017 if (request_irq(irq, sysio_sbus_error_handler, 0, 1018 "SYSIO_SBERR", sbus) < 0) { 1019 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n", 1020 sbus->portid); 1021 prom_halt(); 1022 } 1023 1024 /* Now turn the error interrupts on and also enable ECC checking. */ 1025 upa_writeq((SYSIO_ECNTRL_ECCEN | 1026 SYSIO_ECNTRL_UEEN | 1027 SYSIO_ECNTRL_CEEN), 1028 reg_base + ECC_CONTROL); 1029 1030 control = upa_readq(iommu->write_complete_reg); 1031 control |= 0x100UL; /* SBUS Error Interrupt Enable */ 1032 upa_writeq(control, iommu->write_complete_reg); 1033} 1034 1035/* Boot time initialization. */ 1036static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus) 1037{ 1038 const struct linux_prom64_registers *pr; 1039 struct device_node *dp; 1040 struct sbus_info *info; 1041 struct iommu *iommu; 1042 struct strbuf *strbuf; 1043 unsigned long regs, reg_base; 1044 u64 control; 1045 int i; 1046 1047 dp = of_find_node_by_phandle(__node); 1048 1049 sbus->portid = of_getintprop_default(dp, "upa-portid", -1); 1050 1051 pr = of_get_property(dp, "reg", NULL); 1052 if (!pr) { 1053 prom_printf("sbus_iommu_init: Cannot map SYSIO control registers.\n"); 1054 prom_halt(); 1055 } 1056 regs = pr->phys_addr; 1057 1058 info = kzalloc(sizeof(*info), GFP_ATOMIC); 1059 if (info == NULL) { 1060 prom_printf("sbus_iommu_init: Fatal error, " 1061 "kmalloc(info) failed\n"); 1062 prom_halt(); 1063 } 1064 1065 iommu = &info->iommu; 1066 strbuf = &info->strbuf; 1067 1068 reg_base = regs + SYSIO_IOMMUREG_BASE; 1069 iommu->iommu_control = reg_base + IOMMU_CONTROL; 1070 iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE; 1071 iommu->iommu_flush = reg_base + IOMMU_FLUSH; 1072 1073 reg_base = regs + SYSIO_STRBUFREG_BASE; 1074 strbuf->strbuf_control = reg_base + STRBUF_CONTROL; 1075 strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH; 1076 strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC; 1077 1078 strbuf->strbuf_enabled = 1; 1079 1080 strbuf->strbuf_flushflag = (volatile unsigned long *) 1081 ((((unsigned long)&strbuf->__flushflag_buf[0]) 1082 + 63UL) 1083 & ~63UL); 1084 strbuf->strbuf_flushflag_pa = (unsigned long) 1085 __pa(strbuf->strbuf_flushflag); 1086 1087 /* The SYSIO SBUS control register is used for dummy reads 1088 * in order to ensure write completion. 1089 */ 1090 iommu->write_complete_reg = regs + 0x2000UL; 1091 1092 /* Link into SYSIO software state. */ 1093 sbus->iommu = info; 1094 1095 printk("SYSIO: UPA portID %x, at %016lx\n", 1096 sbus->portid, regs); 1097 1098 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */ 1099 sbus_iommu_table_init(iommu, IO_TSB_SIZE); 1100 1101 control = upa_readq(iommu->iommu_control); 1102 control = ((7UL << 16UL) | 1103 (0UL << 2UL) | 1104 (1UL << 1UL) | 1105 (1UL << 0UL)); 1106 upa_writeq(control, iommu->iommu_control); 1107 1108 /* Clean out any cruft in the IOMMU using 1109 * diagnostic accesses. 1110 */ 1111 for (i = 0; i < 16; i++) { 1112 unsigned long dram, tag; 1113 1114 dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL); 1115 tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL); 1116 1117 dram += (unsigned long)i * 8UL; 1118 tag += (unsigned long)i * 8UL; 1119 upa_writeq(0, dram); 1120 upa_writeq(0, tag); 1121 } 1122 upa_readq(iommu->write_complete_reg); 1123 1124 /* Give the TSB to SYSIO. */ 1125 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); 1126 1127 /* Setup streaming buffer, DE=1 SB_EN=1 */ 1128 control = (1UL << 1UL) | (1UL << 0UL); 1129 upa_writeq(control, strbuf->strbuf_control); 1130 1131 /* Clear out the tags using diagnostics. */ 1132 for (i = 0; i < 16; i++) { 1133 unsigned long ptag, ltag; 1134 1135 ptag = strbuf->strbuf_control + 1136 (STRBUF_PTAGDIAG - STRBUF_CONTROL); 1137 ltag = strbuf->strbuf_control + 1138 (STRBUF_LTAGDIAG - STRBUF_CONTROL); 1139 ptag += (unsigned long)i * 8UL; 1140 ltag += (unsigned long)i * 8UL; 1141 1142 upa_writeq(0UL, ptag); 1143 upa_writeq(0UL, ltag); 1144 } 1145 1146 /* Enable DVMA arbitration for all devices/slots. */ 1147 control = upa_readq(iommu->write_complete_reg); 1148 control |= 0x3fUL; 1149 upa_writeq(control, iommu->write_complete_reg); 1150 1151 /* Now some Xfire specific grot... */ 1152 if (this_is_starfire) 1153 starfire_hookup(sbus->portid); 1154 1155 sysio_register_error_handlers(sbus); 1156} 1157 1158void sbus_fill_device_irq(struct sbus_dev *sdev) 1159{ 1160 struct device_node *dp = of_find_node_by_phandle(sdev->prom_node); 1161 const struct linux_prom_irqs *irqs; 1162 1163 irqs = of_get_property(dp, "interrupts", NULL); 1164 if (!irqs) { 1165 sdev->irqs[0] = 0; 1166 sdev->num_irqs = 0; 1167 } else { 1168 unsigned int pri = irqs[0].pri; 1169 1170 sdev->num_irqs = 1; 1171 if (pri < 0x20) 1172 pri += sdev->slot * 8; 1173 1174 sdev->irqs[0] = sbus_build_irq(sdev->bus, pri); 1175 } 1176} 1177 1178void __init sbus_arch_bus_ranges_init(struct device_node *pn, struct sbus_bus *sbus) 1179{ 1180} 1181 1182void __init sbus_setup_iommu(struct sbus_bus *sbus, struct device_node *dp) 1183{ 1184 sbus_iommu_init(dp->node, sbus); 1185} 1186 1187void __init sbus_setup_arch_props(struct sbus_bus *sbus, struct device_node *dp) 1188{ 1189} 1190 1191int __init sbus_arch_preinit(void) 1192{ 1193 return 0; 1194} 1195 1196void __init sbus_arch_postinit(void) 1197{ 1198 extern void firetruck_init(void); 1199 1200 firetruck_init(); 1201} 1202