1/*
2 * arch/sh/kernel/cpu/sh3/probe.c
3 *
4 * CPU Subtype Probing for SH-3.
5 *
6 * Copyright (C) 1999, 2000  Niibe Yutaka
7 * Copyright (C) 2002  Paul Mundt
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License.  See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#include <linux/init.h>
15#include <asm/processor.h>
16#include <asm/cache.h>
17#include <asm/io.h>
18
19int __init detect_cpu_and_cache_system(void)
20{
21	unsigned long addr0, addr1, data0, data1, data2, data3;
22
23	jump_to_P2();
24	/*
25	 * Check if the entry shadows or not.
26	 * When shadowed, it's 128-entry system.
27	 * Otherwise, it's 256-entry system.
28	 */
29	addr0 = CACHE_OC_ADDRESS_ARRAY + (3 << 12);
30	addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
31
32	/* First, write back & invalidate */
33	data0  = ctrl_inl(addr0);
34	ctrl_outl(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
35	data1  = ctrl_inl(addr1);
36	ctrl_outl(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
37
38	/* Next, check if there's shadow or not */
39	data0 = ctrl_inl(addr0);
40	data0 ^= SH_CACHE_VALID;
41	ctrl_outl(data0, addr0);
42	data1 = ctrl_inl(addr1);
43	data2 = data1 ^ SH_CACHE_VALID;
44	ctrl_outl(data2, addr1);
45	data3 = ctrl_inl(addr0);
46
47	/* Lastly, invaliate them. */
48	ctrl_outl(data0&~SH_CACHE_VALID, addr0);
49	ctrl_outl(data2&~SH_CACHE_VALID, addr1);
50
51	back_to_P1();
52
53	current_cpu_data.dcache.ways		= 4;
54	current_cpu_data.dcache.entry_shift	= 4;
55	current_cpu_data.dcache.linesz		= L1_CACHE_BYTES;
56	current_cpu_data.dcache.flags		= 0;
57
58	/*
59	 * 7709A/7729 has 16K cache (256-entry), while 7702 has only
60	 * 2K(direct) 7702 is not supported (yet)
61	 */
62	if (data0 == data1 && data2 == data3) {	/* Shadow */
63		current_cpu_data.dcache.way_incr	= (1 << 11);
64		current_cpu_data.dcache.entry_mask	= 0x7f0;
65		current_cpu_data.dcache.sets		= 128;
66		current_cpu_data.type = CPU_SH7708;
67
68		current_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
69	} else {				/* 7709A or 7729  */
70		current_cpu_data.dcache.way_incr	= (1 << 12);
71		current_cpu_data.dcache.entry_mask	= 0xff0;
72		current_cpu_data.dcache.sets		= 256;
73		current_cpu_data.type = CPU_SH7729;
74
75#if defined(CONFIG_CPU_SUBTYPE_SH7706)
76		current_cpu_data.type = CPU_SH7706;
77#endif
78#if defined(CONFIG_CPU_SUBTYPE_SH7710)
79		current_cpu_data.type = CPU_SH7710;
80#endif
81#if defined(CONFIG_CPU_SUBTYPE_SH7712)
82		current_cpu_data.type = CPU_SH7712;
83#endif
84#if defined(CONFIG_CPU_SUBTYPE_SH7705)
85		current_cpu_data.type = CPU_SH7705;
86
87#if defined(CONFIG_SH7705_CACHE_32KB)
88		current_cpu_data.dcache.way_incr	= (1 << 13);
89		current_cpu_data.dcache.entry_mask	= 0x1ff0;
90		current_cpu_data.dcache.sets		= 512;
91		ctrl_outl(CCR_CACHE_32KB, CCR3);
92#else
93		ctrl_outl(CCR_CACHE_16KB, CCR3);
94#endif
95#endif
96	}
97
98	/*
99	 * SH-3 doesn't have separate caches
100	 */
101	current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
102	current_cpu_data.icache = current_cpu_data.dcache;
103
104	return 0;
105}
106