1/*
2 * arch/sh/drivers/pci/fixups-se7780.c
3 *
4 * HITACHI UL Solution Engine 7780  PCI fixups
5 *
6 * Copyright (C) 2003  Lineo uSolutions, Inc.
7 * Copyright (C) 2004 - 2006  Paul Mundt
8 * Copyright (C) 2006  Nobuhiro Iwamatsu
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License.  See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/pci.h>
15#include "pci-sh4.h"
16#include <asm/io.h>
17
18int pci_fixup_pcic(void)
19{
20	ctrl_outl(0x00000001, SH7780_PCI_VCR2);
21
22	/* Enable all interrupts, so we know what to fix */
23	pci_write_reg(0x0000C3FF, SH7780_PCIIMR);
24	pci_write_reg(0x0000380F, SH7780_PCIAINTM);
25
26	/* Set up standard PCI config registers */
27	ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));
28	ctrl_outw(0x0047, PCI_REG(SH7780_PCICMD));
29	ctrl_outb(  0x00, PCI_REG(SH7780_PCIPIF));
30	ctrl_outb(  0x00, PCI_REG(SH7780_PCISUB));
31	ctrl_outb(  0x06, PCI_REG(SH7780_PCIBCC));
32	ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));
33	ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));
34
35	pci_write_reg(0x08000000, SH7780_PCIMBAR0);     /* PCI */
36	pci_write_reg(0x08000000, SH7780_PCILAR0);     /* SHwy */
37	pci_write_reg(0x07F00001, SH7780_PCILSR);      /* size 128M w/ MBAR */
38
39	pci_write_reg(0x00000000, SH7780_PCIMBAR1);
40	pci_write_reg(0x00000000, SH7780_PCILAR1);
41	pci_write_reg(0x00000000, SH7780_PCILSR1);
42
43	pci_write_reg(0xAB000801, SH7780_PCIIBAR);
44
45	/*
46	 * Set the MBR so PCI address is one-to-one with window,
47	 * meaning all calls go straight through... use ifdef to
48	 * catch erroneous assumption.
49	 */
50	pci_write_reg(0xFD000000 , SH7780_PCIMBR0);
51	pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0);    /* 16M */
52
53	/* Set IOBR for window containing area specified in pci.h */
54	pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR);
55	pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR);
56
57	pci_write_reg(0xA5000C01, SH7780_PCICR);
58
59	return 0;
60}
61