1/* 2 * MPC83XX common board code 3 * 4 * Maintainer: Kumar Gala <galak@kernel.crashing.org> 5 * 6 * Copyright 2005 Freescale Semiconductor Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 * Added PCI support -- Tony Li <tony.li@freescale.com> 23 */ 24 25#include <linux/types.h> 26#include <linux/module.h> 27#include <linux/init.h> 28#include <linux/pci.h> 29#include <linux/serial.h> 30#include <linux/tty.h> /* for linux/serial_core.h */ 31#include <linux/serial_core.h> 32#include <linux/serial_8250.h> 33 34#include <asm/time.h> 35#include <asm/mpc83xx.h> 36#include <asm/mmu.h> 37#include <asm/ppc_sys.h> 38#include <asm/kgdb.h> 39#include <asm/delay.h> 40#include <asm/machdep.h> 41 42#include <syslib/ppc83xx_setup.h> 43#if defined(CONFIG_PCI) 44#include <asm/delay.h> 45#include <syslib/ppc83xx_pci.h> 46#endif 47 48phys_addr_t immrbar; 49 50/* Return the amount of memory */ 51unsigned long __init 52mpc83xx_find_end_of_memory(void) 53{ 54 bd_t *binfo; 55 56 binfo = (bd_t *) __res; 57 58 return binfo->bi_memsize; 59} 60 61long __init 62mpc83xx_time_init(void) 63{ 64#define SPCR_OFFS 0x00000110 65#define SPCR_TBEN 0x00400000 66 67 bd_t *binfo = (bd_t *)__res; 68 u32 *spcr = ioremap(binfo->bi_immr_base + SPCR_OFFS, 4); 69 70 *spcr |= SPCR_TBEN; 71 72 iounmap(spcr); 73 74 return 0; 75} 76 77/* The decrementer counts at the system (internal) clock freq divided by 4 */ 78void __init 79mpc83xx_calibrate_decr(void) 80{ 81 bd_t *binfo = (bd_t *) __res; 82 unsigned int freq, divisor; 83 84 freq = binfo->bi_busfreq; 85 divisor = 4; 86 tb_ticks_per_jiffy = freq / HZ / divisor; 87 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000); 88} 89 90#ifdef CONFIG_SERIAL_8250 91void __init 92mpc83xx_early_serial_map(void) 93{ 94#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) 95 struct uart_port serial_req; 96#endif 97 struct plat_serial8250_port *pdata; 98 bd_t *binfo = (bd_t *) __res; 99 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART); 100 101 /* Setup serial port access */ 102 pdata[0].uartclk = binfo->bi_busfreq; 103 pdata[0].mapbase += binfo->bi_immr_base; 104 pdata[0].membase = ioremap(pdata[0].mapbase, 0x100); 105 106#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) 107 memset(&serial_req, 0, sizeof (serial_req)); 108 serial_req.iotype = UPIO_MEM; 109 serial_req.mapbase = pdata[0].mapbase; 110 serial_req.membase = pdata[0].membase; 111 serial_req.regshift = 0; 112 113 gen550_init(0, &serial_req); 114#endif 115 116 pdata[1].uartclk = binfo->bi_busfreq; 117 pdata[1].mapbase += binfo->bi_immr_base; 118 pdata[1].membase = ioremap(pdata[1].mapbase, 0x100); 119 120#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) 121 /* Assume gen550_init() doesn't modify serial_req */ 122 serial_req.mapbase = pdata[1].mapbase; 123 serial_req.membase = pdata[1].membase; 124 125 gen550_init(1, &serial_req); 126#endif 127} 128#endif 129 130void 131mpc83xx_restart(char *cmd) 132{ 133 volatile unsigned char __iomem *reg; 134 unsigned char tmp; 135 136 reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE); 137 138 local_irq_disable(); 139 140 /* 141 * Unlock the BCSR bits so a PRST will update the contents. 142 * Otherwise the reset asserts but doesn't clear. 143 */ 144 tmp = in_8(reg + BCSR_MISC_REG3_OFF); 145 tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */ 146 out_8(reg + BCSR_MISC_REG3_OFF, tmp); 147 148 /* 149 * Trigger a reset via a low->high transition of the 150 * PORESET bit. 151 */ 152 tmp = in_8(reg + BCSR_MISC_REG2_OFF); 153 tmp &= ~BCSR_MISC_REG2_PORESET; 154 out_8(reg + BCSR_MISC_REG2_OFF, tmp); 155 156 udelay(1); 157 158 tmp |= BCSR_MISC_REG2_PORESET; 159 out_8(reg + BCSR_MISC_REG2_OFF, tmp); 160 161 for(;;); 162} 163 164void 165mpc83xx_power_off(void) 166{ 167 local_irq_disable(); 168 for(;;); 169} 170 171void 172mpc83xx_halt(void) 173{ 174 local_irq_disable(); 175 for(;;); 176} 177 178#if defined(CONFIG_PCI) 179void __init 180mpc83xx_setup_pci1(struct pci_controller *hose) 181{ 182 u16 reg16; 183 volatile immr_pcictrl_t * pci_ctrl; 184 volatile immr_ios_t * ios; 185 bd_t *binfo = (bd_t *) __res; 186 187 pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t)); 188 ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t)); 189 190 /* 191 * Configure PCI Outbound Translation Windows 192 */ 193 ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK; 194 ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK; 195 ios->pocmr0 = POCMR_EN | 196 (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM - 197 MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK); 198 199 /* mapped to PCI1 IO space */ 200 ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK; 201 ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK; 202 ios->pocmr1 = POCMR_EN | POCMR_IO | 203 (((0xffffffff - (MPC83xx_PCI1_UPPER_IO - 204 MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK); 205 206 /* 207 * Configure PCI Inbound Translation Windows 208 */ 209 pci_ctrl->pitar1 = 0x0; 210 pci_ctrl->pibar1 = 0x0; 211 pci_ctrl->piebar1 = 0x0; 212 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; 213 214 /* 215 * Release PCI RST signal 216 */ 217 pci_ctrl->gcr = 0; 218 udelay(2000); 219 pci_ctrl->gcr = 1; 220 udelay(2000); 221 222 reg16 = 0xff; 223 early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16); 224 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 225 early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16); 226 227 /* 228 * Clear non-reserved bits in status register. 229 */ 230 early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff); 231 early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80); 232 233 iounmap(pci_ctrl); 234 iounmap(ios); 235} 236 237void __init 238mpc83xx_setup_pci2(struct pci_controller *hose) 239{ 240 u16 reg16; 241 volatile immr_pcictrl_t * pci_ctrl; 242 volatile immr_ios_t * ios; 243 bd_t *binfo = (bd_t *) __res; 244 245 pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t)); 246 ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t)); 247 248 /* 249 * Configure PCI Outbound Translation Windows 250 */ 251 ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK; 252 ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK; 253 ios->pocmr3 = POCMR_EN | POCMR_DST | 254 (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM - 255 MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK); 256 257 /* mapped to PCI2 IO space */ 258 ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK; 259 ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK; 260 ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO | 261 (((0xffffffff - (MPC83xx_PCI2_UPPER_IO - 262 MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK); 263 264 /* 265 * Configure PCI Inbound Translation Windows 266 */ 267 pci_ctrl->pitar1 = 0x0; 268 pci_ctrl->pibar1 = 0x0; 269 pci_ctrl->piebar1 = 0x0; 270 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; 271 272 /* 273 * Release PCI RST signal 274 */ 275 pci_ctrl->gcr = 0; 276 udelay(2000); 277 pci_ctrl->gcr = 1; 278 udelay(2000); 279 280 reg16 = 0xff; 281 early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16); 282 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 283 early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16); 284 285 /* 286 * Clear non-reserved bits in status register. 287 */ 288 early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff); 289 early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80); 290 291 iounmap(pci_ctrl); 292 iounmap(ios); 293} 294 295/* 296 * PCI buses can be enabled only if SYS board combinates with PIB 297 * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses 298 * and 3 PCI slots, so people must configure the routes between them before 299 * enable PCI bus. This routes are under the control of PCA9555PW device which 300 * can be accessed via I2C bus 2 and are configured by firmware. Refer to 301 * Freescale to get more information about firmware configuration. 302 */ 303 304extern int mpc83xx_exclude_device(u_char bus, u_char devfn); 305extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, 306 unsigned char pin); 307void __init 308mpc83xx_setup_hose(void) 309{ 310 u32 val32; 311 volatile immr_clk_t * clk; 312 struct pci_controller * hose1; 313#ifdef CONFIG_MPC83xx_PCI2 314 struct pci_controller * hose2; 315#endif 316 bd_t * binfo = (bd_t *)__res; 317 318 clk = ioremap(binfo->bi_immr_base + 0xA00, 319 sizeof(immr_clk_t)); 320 321 /* 322 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode 323 */ 324 val32 = clk->occr; 325 udelay(2000); 326 clk->occr = 0xff000000; 327 udelay(2000); 328 329 iounmap(clk); 330 331 hose1 = pcibios_alloc_controller(); 332 if(!hose1) 333 return; 334 335 ppc_md.pci_swizzle = common_swizzle; 336 ppc_md.pci_map_irq = mpc83xx_map_irq; 337 338 hose1->bus_offset = 0; 339 hose1->first_busno = 0; 340 hose1->last_busno = 0xff; 341 342 setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET, 343 binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET); 344 hose1->set_cfg_type = 1; 345 346 mpc83xx_setup_pci1(hose1); 347 348 hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET; 349 hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM; 350 hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM; 351 352 hose1->io_base_phys = MPC83xx_PCI1_IO_BASE; 353 hose1->io_space.start = MPC83xx_PCI1_LOWER_IO; 354 hose1->io_space.end = MPC83xx_PCI1_UPPER_IO; 355#ifdef CONFIG_MPC83xx_PCI2 356 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, 357 MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE); 358#else 359 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, 360 MPC83xx_PCI1_IO_SIZE); 361#endif /* CONFIG_MPC83xx_PCI2 */ 362 hose1->io_base_virt = (void *)isa_io_base; 363 /* setup resources */ 364 pci_init_resource(&hose1->io_resource, 365 MPC83xx_PCI1_LOWER_IO, 366 MPC83xx_PCI1_UPPER_IO, 367 IORESOURCE_IO, "PCI host bridge 1"); 368 pci_init_resource(&hose1->mem_resources[0], 369 MPC83xx_PCI1_LOWER_MEM, 370 MPC83xx_PCI1_UPPER_MEM, 371 IORESOURCE_MEM, "PCI host bridge 1"); 372 373 ppc_md.pci_exclude_device = mpc83xx_exclude_device; 374 hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno); 375 376#ifdef CONFIG_MPC83xx_PCI2 377 hose2 = pcibios_alloc_controller(); 378 if(!hose2) 379 return; 380 381 hose2->bus_offset = hose1->last_busno + 1; 382 hose2->first_busno = hose1->last_busno + 1; 383 hose2->last_busno = 0xff; 384 setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET, 385 binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET); 386 hose2->set_cfg_type = 1; 387 388 mpc83xx_setup_pci2(hose2); 389 390 hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET; 391 hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM; 392 hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM; 393 394 hose2->io_base_phys = MPC83xx_PCI2_IO_BASE; 395 hose2->io_space.start = MPC83xx_PCI2_LOWER_IO; 396 hose2->io_space.end = MPC83xx_PCI2_UPPER_IO; 397 hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE); 398 /* setup resources */ 399 pci_init_resource(&hose2->io_resource, 400 MPC83xx_PCI2_LOWER_IO, 401 MPC83xx_PCI2_UPPER_IO, 402 IORESOURCE_IO, "PCI host bridge 2"); 403 pci_init_resource(&hose2->mem_resources[0], 404 MPC83xx_PCI2_LOWER_MEM, 405 MPC83xx_PCI2_UPPER_MEM, 406 IORESOURCE_MEM, "PCI host bridge 2"); 407 408 hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); 409#endif /* CONFIG_MPC83xx_PCI2 */ 410} 411#endif /*CONFIG_PCI*/ 412