1/* 2 * Copyright (c) 2005 Cisco Systems. All rights reserved. 3 * Roland Dreier <rolandd@cisco.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11#ifndef __PPC_SYSLIB_PPC440SPE_PCIE_H 12#define __PPC_SYSLIB_PPC440SPE_PCIE_H 13 14#define DCRN_SDR0_CFGADDR 0x00e 15#define DCRN_SDR0_CFGDATA 0x00f 16 17#define DCRN_PCIE0_BASE 0x100 18#define DCRN_PCIE1_BASE 0x120 19#define DCRN_PCIE2_BASE 0x140 20#define PCIE0 DCRN_PCIE0_BASE 21#define PCIE1 DCRN_PCIE1_BASE 22#define PCIE2 DCRN_PCIE2_BASE 23 24#define DCRN_PEGPL_CFGBAH(base) (base + 0x00) 25#define DCRN_PEGPL_CFGBAL(base) (base + 0x01) 26#define DCRN_PEGPL_CFGMSK(base) (base + 0x02) 27#define DCRN_PEGPL_MSGBAH(base) (base + 0x03) 28#define DCRN_PEGPL_MSGBAL(base) (base + 0x04) 29#define DCRN_PEGPL_MSGMSK(base) (base + 0x05) 30#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06) 31#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07) 32#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08) 33#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09) 34#define DCRN_PEGPL_REGBAH(base) (base + 0x12) 35#define DCRN_PEGPL_REGBAL(base) (base + 0x13) 36#define DCRN_PEGPL_REGMSK(base) (base + 0x14) 37#define DCRN_PEGPL_SPECIAL(base) (base + 0x15) 38 39/* 40 * System DCRs (SDRs) 41 */ 42#define PESDR0_PLLLCT1 0x03a0 43#define PESDR0_PLLLCT2 0x03a1 44#define PESDR0_PLLLCT3 0x03a2 45 46#define PESDR0_UTLSET1 0x0300 47#define PESDR0_UTLSET2 0x0301 48#define PESDR0_DLPSET 0x0302 49#define PESDR0_LOOP 0x0303 50#define PESDR0_RCSSET 0x0304 51#define PESDR0_RCSSTS 0x0305 52#define PESDR0_HSSL0SET1 0x0306 53#define PESDR0_HSSL0SET2 0x0307 54#define PESDR0_HSSL0STS 0x0308 55#define PESDR0_HSSL1SET1 0x0309 56#define PESDR0_HSSL1SET2 0x030a 57#define PESDR0_HSSL1STS 0x030b 58#define PESDR0_HSSL2SET1 0x030c 59#define PESDR0_HSSL2SET2 0x030d 60#define PESDR0_HSSL2STS 0x030e 61#define PESDR0_HSSL3SET1 0x030f 62#define PESDR0_HSSL3SET2 0x0310 63#define PESDR0_HSSL3STS 0x0311 64#define PESDR0_HSSL4SET1 0x0312 65#define PESDR0_HSSL4SET2 0x0313 66#define PESDR0_HSSL4STS 0x0314 67#define PESDR0_HSSL5SET1 0x0315 68#define PESDR0_HSSL5SET2 0x0316 69#define PESDR0_HSSL5STS 0x0317 70#define PESDR0_HSSL6SET1 0x0318 71#define PESDR0_HSSL6SET2 0x0319 72#define PESDR0_HSSL6STS 0x031a 73#define PESDR0_HSSL7SET1 0x031b 74#define PESDR0_HSSL7SET2 0x031c 75#define PESDR0_HSSL7STS 0x031d 76#define PESDR0_HSSCTLSET 0x031e 77#define PESDR0_LANE_ABCD 0x031f 78#define PESDR0_LANE_EFGH 0x0320 79 80#define PESDR1_UTLSET1 0x0340 81#define PESDR1_UTLSET2 0x0341 82#define PESDR1_DLPSET 0x0342 83#define PESDR1_LOOP 0x0343 84#define PESDR1_RCSSET 0x0344 85#define PESDR1_RCSSTS 0x0345 86#define PESDR1_HSSL0SET1 0x0346 87#define PESDR1_HSSL0SET2 0x0347 88#define PESDR1_HSSL0STS 0x0348 89#define PESDR1_HSSL1SET1 0x0349 90#define PESDR1_HSSL1SET2 0x034a 91#define PESDR1_HSSL1STS 0x034b 92#define PESDR1_HSSL2SET1 0x034c 93#define PESDR1_HSSL2SET2 0x034d 94#define PESDR1_HSSL2STS 0x034e 95#define PESDR1_HSSL3SET1 0x034f 96#define PESDR1_HSSL3SET2 0x0350 97#define PESDR1_HSSL3STS 0x0351 98#define PESDR1_HSSCTLSET 0x0352 99#define PESDR1_LANE_ABCD 0x0353 100 101#define PESDR2_UTLSET1 0x0370 102#define PESDR2_UTLSET2 0x0371 103#define PESDR2_DLPSET 0x0372 104#define PESDR2_LOOP 0x0373 105#define PESDR2_RCSSET 0x0374 106#define PESDR2_RCSSTS 0x0375 107#define PESDR2_HSSL0SET1 0x0376 108#define PESDR2_HSSL0SET2 0x0377 109#define PESDR2_HSSL0STS 0x0378 110#define PESDR2_HSSL1SET1 0x0379 111#define PESDR2_HSSL1SET2 0x037a 112#define PESDR2_HSSL1STS 0x037b 113#define PESDR2_HSSL2SET1 0x037c 114#define PESDR2_HSSL2SET2 0x037d 115#define PESDR2_HSSL2STS 0x037e 116#define PESDR2_HSSL3SET1 0x037f 117#define PESDR2_HSSL3SET2 0x0380 118#define PESDR2_HSSL3STS 0x0381 119#define PESDR2_HSSCTLSET 0x0382 120#define PESDR2_LANE_ABCD 0x0383 121 122/* 123 * UTL register offsets 124 */ 125#define PEUTL_PBBSZ 0x20 126#define PEUTL_OPDBSZ 0x68 127#define PEUTL_IPHBSZ 0x70 128#define PEUTL_IPDBSZ 0x78 129#define PEUTL_OUTTR 0x90 130#define PEUTL_INTR 0x98 131#define PEUTL_PCTL 0xa0 132#define PEUTL_RCIRQEN 0xb8 133 134/* 135 * Config space register offsets 136 */ 137#define PECFG_BAR0LMPA 0x210 138#define PECFG_BAR0HMPA 0x214 139#define PECFG_PIMEN 0x33c 140#define PECFG_PIM0LAL 0x340 141#define PECFG_PIM0LAH 0x344 142#define PECFG_POM0LAL 0x380 143#define PECFG_POM0LAH 0x384 144 145int ppc440spe_init_pcie(void); 146int ppc440spe_init_pcie_rootport(int port); 147void ppc440spe_setup_pcie(struct pci_controller *hose, int port); 148 149#endif /* __PPC_SYSLIB_PPC440SPE_PCIE_H */ 150