1/*
2 * Header file for IBM CPC700 Host Bridge, et. al.
3 *
4 * Author: Mark A. Greer
5 *         mgreer@mvista.com
6 *
7 * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
8 * the terms of the GNU General Public License version 2.  This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13/*
14 * This file contains the defines and macros for the IBM CPC700 host bridge,
15 * memory controller, PIC, UARTs, IIC, and Timers.
16 */
17
18#ifndef	__PPC_SYSLIB_CPC700_H__
19#define	__PPC_SYSLIB_CPC700_H__
20
21#include <linux/stddef.h>
22#include <linux/types.h>
23#include <linux/init.h>
24
25#define CPC700_OUT_32(a,d)  (*(u_int *)a = d)
26#define CPC700_IN_32(a)     (*(u_int *)a)
27
28/*
29 * PCI Section
30 */
31#define CPC700_PCI_CONFIG_ADDR          0xfec00000
32#define CPC700_PCI_CONFIG_DATA          0xfec00004
33
34/* CPU -> PCI memory window 0 */
35#define CPC700_PMM0_LOCAL		0xff400000	/* CPU physical addr */
36#define CPC700_PMM0_MASK_ATTR		0xff400004	/* size and attrs */
37#define CPC700_PMM0_PCI_LOW		0xff400008	/* PCI addr, low word */
38#define CPC700_PMM0_PCI_HIGH		0xff40000c	/* PCI addr, high wd */
39/* CPU -> PCI memory window 1 */
40#define CPC700_PMM1_LOCAL		0xff400010
41#define CPC700_PMM1_MASK_ATTR		0xff400014
42#define CPC700_PMM1_PCI_LOW		0xff400018
43#define CPC700_PMM1_PCI_HIGH		0xff40001c
44/* CPU -> PCI memory window 2 */
45#define CPC700_PMM2_LOCAL		0xff400020
46#define CPC700_PMM2_MASK_ATTR		0xff400024
47#define CPC700_PMM2_PCI_LOW		0xff400028
48#define CPC700_PMM2_PCI_HIGH		0xff40002c
49/* PCI memory -> CPU window 1 */
50#define CPC700_PTM1_MEMSIZE		0xff400030	/* window size */
51#define CPC700_PTM1_LOCAL		0xff400034	/* CPU phys addr */
52/* PCI memory -> CPU window 2 */
53#define CPC700_PTM2_MEMSIZE		0xff400038	/* size and enable */
54#define CPC700_PTM2_LOCAL		0xff40003c
55
56/*
57 * PIC Section
58 *
59 * IBM calls the CPC700's programmable interrupt controller the Universal
60 * Interrupt Controller or UIC.
61 */
62
63/*
64 * UIC Register Addresses.
65 */
66#define	CPC700_UIC_UICSR		0xff500880	/* Status Reg (Rd/Clr)*/
67#define	CPC700_UIC_UICSRS		0xff500884	/* Status Reg (Set) */
68#define	CPC700_UIC_UICER		0xff500888	/* Enable Reg */
69#define	CPC700_UIC_UICCR		0xff50088c	/* Critical Reg */
70#define	CPC700_UIC_UICPR		0xff500890	/* Polarity Reg */
71#define	CPC700_UIC_UICTR		0xff500894	/* Trigger Reg */
72#define	CPC700_UIC_UICMSR		0xff500898	/* Masked Status Reg */
73#define	CPC700_UIC_UICVR		0xff50089c	/* Vector Reg */
74#define	CPC700_UIC_UICVCR		0xff5008a0	/* Vector Config Reg */
75
76#define	CPC700_UIC_UICER_ENABLE		0x00000001	/* Enable an IRQ */
77
78#define	CPC700_UIC_UICVCR_31_HI		0x00000000	/* IRQ 31 hi priority */
79#define	CPC700_UIC_UICVCR_0_HI		0x00000001	/* IRQ 0 hi priority */
80#define CPC700_UIC_UICVCR_BASE_MASK	0xfffffffc
81#define CPC700_UIC_UICVCR_ORDER_MASK	0x00000001
82
83/* Specify value of a bit for an IRQ. */
84#define	CPC700_UIC_IRQ_BIT(i)		((0x00000001) << (31 - (i)))
85
86/*
87 * UIC Exports...
88 */
89extern struct hw_interrupt_type cpc700_pic;
90extern unsigned int cpc700_irq_assigns[32][2];
91
92extern void __init cpc700_init_IRQ(void);
93extern int cpc700_get_irq(void);
94
95#endif	/* __PPC_SYSLIB_CPC700_H__ */
96