1/*
2 * Definitions for Marvell EV-64360-BP Evaluation Board.
3 *
4 * Author: Lee Nicks <allinux@gmail.com>
5 *
6 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
7 * Based on code done by Mark A. Greer <mgreer@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15/*
16 * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
17 * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
18 * We'll only use one PCI MEM window on each PCI bus.
19 *
20 * This is the CPU physical memory map (windows must be at least 64KB and start
21 * on a boundary that is a multiple of the window size):
22 *
23 *    0x42000000-0x4203ffff      - Internal SRAM
24 *    0xf1000000-0xf100ffff      - MV64360 Registers (CONFIG_MV64X60_NEW_BASE)
25 *    0xfc800000-0xfcffffff      - RTC
26 *    0xff000000-0xffffffff      - Boot window, 16 MB flash
27 *    0xc0000000-0xc3ffffff      - PCI I/O (second hose)
28 *    0x80000000-0xbfffffff      - PCI MEM (second hose)
29 */
30
31#ifndef __PPC_PLATFORMS_EV64360_H
32#define __PPC_PLATFORMS_EV64360_H
33
34/* CPU Physical Memory Map setup. */
35#define EV64360_BOOT_WINDOW_BASE		0xff000000
36#define EV64360_BOOT_WINDOW_SIZE		0x01000000 /* 16 MB */
37#define EV64360_INTERNAL_SRAM_BASE		0x42000000
38#define EV64360_RTC_WINDOW_BASE			0xfc800000
39#define EV64360_RTC_WINDOW_SIZE			0x00800000 /* 8 MB */
40
41#define EV64360_PCI1_MEM_START_PROC_ADDR	0x80000000
42#define EV64360_PCI1_MEM_START_PCI_HI_ADDR	0x00000000
43#define EV64360_PCI1_MEM_START_PCI_LO_ADDR	0x80000000
44#define EV64360_PCI1_MEM_SIZE			0x40000000 /* 1 GB */
45#define EV64360_PCI1_IO_START_PROC_ADDR		0xc0000000
46#define EV64360_PCI1_IO_START_PCI_ADDR		0x00000000
47#define EV64360_PCI1_IO_SIZE			0x04000000 /* 64 MB */
48
49#define	EV64360_DEFAULT_BAUD			115200
50#define	EV64360_MPSC_CLK_SRC			8	  /* TCLK */
51#define EV64360_MPSC_CLK_FREQ			133333333
52
53#define	EV64360_MTD_RESERVED_SIZE		0x40000
54#define EV64360_MTD_JFFS2_SIZE			0xec0000
55#define EV64360_MTD_UBOOT_SIZE			0x100000
56
57#define	EV64360_ETH0_PHY_ADDR			8
58#define	EV64360_ETH1_PHY_ADDR			9
59#define	EV64360_ETH2_PHY_ADDR			10
60
61#define EV64360_ETH_TX_QUEUE_SIZE		800
62#define EV64360_ETH_RX_QUEUE_SIZE		400
63
64#define	EV64360_ETH_PORT_CONFIG_VALUE			\
65	ETH_UNICAST_NORMAL_MODE			|	\
66	ETH_DEFAULT_RX_QUEUE_0			|	\
67	ETH_DEFAULT_RX_ARP_QUEUE_0		|	\
68	ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP		|	\
69	ETH_RECEIVE_BC_IF_IP			|	\
70	ETH_RECEIVE_BC_IF_ARP			|	\
71	ETH_CAPTURE_TCP_FRAMES_DIS		|	\
72	ETH_CAPTURE_UDP_FRAMES_DIS		|	\
73	ETH_DEFAULT_RX_TCP_QUEUE_0		|	\
74	ETH_DEFAULT_RX_UDP_QUEUE_0		|	\
75	ETH_DEFAULT_RX_BPDU_QUEUE_0
76
77#define	EV64360_ETH_PORT_CONFIG_EXTEND_VALUE		\
78	ETH_SPAN_BPDU_PACKETS_AS_NORMAL		|	\
79	ETH_PARTITION_DISABLE
80
81#define	GT_ETH_IPG_INT_RX(value)			\
82	((value & 0x3fff) << 8)
83
84#define	EV64360_ETH_PORT_SDMA_CONFIG_VALUE		\
85	ETH_RX_BURST_SIZE_4_64BIT		|	\
86	GT_ETH_IPG_INT_RX(0)			|	\
87	ETH_TX_BURST_SIZE_4_64BIT
88
89#define	EV64360_ETH_PORT_SERIAL_CONTROL_VALUE		\
90	ETH_FORCE_LINK_PASS			|	\
91	ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
92	ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
93	ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
94	ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
95	ETH_FORCE_BP_MODE_NO_JAM		|	\
96	BIT9					|	\
97	ETH_DO_NOT_FORCE_LINK_FAIL		|	\
98	ETH_RETRANSMIT_16_ATTEMPTS		|	\
99	ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
100	ETH_DTE_ADV_0				|	\
101	ETH_DISABLE_AUTO_NEG_BYPASS		|	\
102	ETH_AUTO_NEG_NO_CHANGE			|	\
103	ETH_MAX_RX_PACKET_9700BYTE		|	\
104	ETH_CLR_EXT_LOOPBACK			|	\
105	ETH_SET_FULL_DUPLEX_MODE		|	\
106	ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
107
108static inline u32
109ev64360_bus_freq(void)
110{
111	return 133333333;
112}
113
114#endif	/* __PPC_PLATFORMS_EV64360_H */
115