1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Low-level exception handlers and MMU support 7 * rewritten by Paul Mackerras. 8 * Copyright (C) 1996 Paul Mackerras. 9 * MPC8xx modifications by Dan Malek 10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains low-level support and setup for PowerPC 8xx 13 * embedded processors, including trap and interrupt dispatch. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <asm/processor.h> 23#include <asm/page.h> 24#include <asm/mmu.h> 25#include <asm/cache.h> 26#include <asm/pgtable.h> 27#include <asm/cputable.h> 28#include <asm/thread_info.h> 29#include <asm/ppc_asm.h> 30#include <asm/asm-offsets.h> 31 32/* Macro to make the code more readable. */ 33#ifdef CONFIG_8xx_CPU6 34#define DO_8xx_CPU6(val, reg) \ 35 li reg, val; \ 36 stw reg, 12(r0); \ 37 lwz reg, 12(r0); 38#else 39#define DO_8xx_CPU6(val, reg) 40#endif 41 .text 42 .globl _stext 43_stext: 44 .text 45 .globl _start 46_start: 47 48/* MPC8xx 49 * This port was done on an MBX board with an 860. Right now I only 50 * support an ELF compressed (zImage) boot from EPPC-Bug because the 51 * code there loads up some registers before calling us: 52 * r3: ptr to board info data 53 * r4: initrd_start or if no initrd then 0 54 * r5: initrd_end - unused if r4 is 0 55 * r6: Start of command line string 56 * r7: End of command line string 57 * 58 * I decided to use conditional compilation instead of checking PVR and 59 * adding more processor specific branches around code I don't need. 60 * Since this is an embedded processor, I also appreciate any memory 61 * savings I can get. 62 * 63 * The MPC8xx does not have any BATs, but it supports large page sizes. 64 * We first initialize the MMU to support 8M byte pages, then load one 65 * entry into each of the instruction and data TLBs to map the first 66 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 67 * the "internal" processor registers before MMU_init is called. 68 * 69 * The TLB code currently contains a major hack. Since I use the condition 70 * code register, I have to save and restore it. I am out of registers, so 71 * I just store it in memory location 0 (the TLB handlers are not reentrant). 72 * To avoid making any decisions, I need to use the "segment" valid bit 73 * in the first level table, but that would require many changes to the 74 * Linux page directory/table functions that I don't want to do right now. 75 * 76 * I used to use SPRG2 for a temporary register in the TLB handler, but it 77 * has since been put to other uses. I now use a hack to save a register 78 * and the CCR at memory location 0.....Someday I'll fix this..... 79 * -- Dan 80 */ 81 .globl __start 82__start: 83 mr r31,r3 /* save parameters */ 84 mr r30,r4 85 mr r29,r5 86 mr r28,r6 87 mr r27,r7 88 89 /* We have to turn on the MMU right away so we get cache modes 90 * set correctly. 91 */ 92 bl initial_mmu 93 94/* We now have the lower 8 Meg mapped into TLB entries, and the caches 95 * ready to work. 96 */ 97 98turn_on_mmu: 99 mfmsr r0 100 ori r0,r0,MSR_DR|MSR_IR 101 mtspr SPRN_SRR1,r0 102 lis r0,start_here@h 103 ori r0,r0,start_here@l 104 mtspr SPRN_SRR0,r0 105 SYNC 106 rfi /* enables MMU */ 107 108/* 109 * Exception entry code. This code runs with address translation 110 * turned off, i.e. using physical addresses. 111 * We assume sprg3 has the physical address of the current 112 * task's thread_struct. 113 */ 114#define EXCEPTION_PROLOG \ 115 mtspr SPRN_SPRG0,r10; \ 116 mtspr SPRN_SPRG1,r11; \ 117 mfcr r10; \ 118 EXCEPTION_PROLOG_1; \ 119 EXCEPTION_PROLOG_2 120 121#define EXCEPTION_PROLOG_1 \ 122 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 123 andi. r11,r11,MSR_PR; \ 124 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 125 beq 1f; \ 126 mfspr r11,SPRN_SPRG3; \ 127 lwz r11,THREAD_INFO-THREAD(r11); \ 128 addi r11,r11,THREAD_SIZE; \ 129 tophys(r11,r11); \ 1301: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 131 132 133#define EXCEPTION_PROLOG_2 \ 134 CLR_TOP32(r11); \ 135 stw r10,_CCR(r11); /* save registers */ \ 136 stw r12,GPR12(r11); \ 137 stw r9,GPR9(r11); \ 138 mfspr r10,SPRN_SPRG0; \ 139 stw r10,GPR10(r11); \ 140 mfspr r12,SPRN_SPRG1; \ 141 stw r12,GPR11(r11); \ 142 mflr r10; \ 143 stw r10,_LINK(r11); \ 144 mfspr r12,SPRN_SRR0; \ 145 mfspr r9,SPRN_SRR1; \ 146 stw r1,GPR1(r11); \ 147 stw r1,0(r11); \ 148 tovirt(r1,r11); /* set new kernel sp */ \ 149 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 150 MTMSRD(r10); /* (except for mach check in rtas) */ \ 151 stw r0,GPR0(r11); \ 152 SAVE_4GPRS(3, r11); \ 153 SAVE_2GPRS(7, r11) 154 155/* 156 * Note: code which follows this uses cr0.eq (set if from kernel), 157 * r11, r12 (SRR0), and r9 (SRR1). 158 * 159 * Note2: once we have set r1 we are in a position to take exceptions 160 * again, and we could thus set MSR:RI at that point. 161 */ 162 163/* 164 * Exception vectors. 165 */ 166#define EXCEPTION(n, label, hdlr, xfer) \ 167 . = n; \ 168label: \ 169 EXCEPTION_PROLOG; \ 170 addi r3,r1,STACK_FRAME_OVERHEAD; \ 171 xfer(n, hdlr) 172 173#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 174 li r10,trap; \ 175 stw r10,TRAP(r11); \ 176 li r10,MSR_KERNEL; \ 177 copyee(r10, r9); \ 178 bl tfer; \ 179i##n: \ 180 .long hdlr; \ 181 .long ret 182 183#define COPY_EE(d, s) rlwimi d,s,0,16,16 184#define NOCOPY(d, s) 185 186#define EXC_XFER_STD(n, hdlr) \ 187 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 188 ret_from_except_full) 189 190#define EXC_XFER_LITE(n, hdlr) \ 191 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 192 ret_from_except) 193 194#define EXC_XFER_EE(n, hdlr) \ 195 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 196 ret_from_except_full) 197 198#define EXC_XFER_EE_LITE(n, hdlr) \ 199 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 200 ret_from_except) 201 202/* System reset */ 203 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) 204 205/* Machine check */ 206 . = 0x200 207MachineCheck: 208 EXCEPTION_PROLOG 209 mfspr r4,SPRN_DAR 210 stw r4,_DAR(r11) 211 mfspr r5,SPRN_DSISR 212 stw r5,_DSISR(r11) 213 addi r3,r1,STACK_FRAME_OVERHEAD 214 EXC_XFER_STD(0x200, machine_check_exception) 215 216/* Data access exception. 217 * This is "never generated" by the MPC8xx. We jump to it for other 218 * translation errors. 219 */ 220 . = 0x300 221DataAccess: 222 EXCEPTION_PROLOG 223 mfspr r10,SPRN_DSISR 224 stw r10,_DSISR(r11) 225 mr r5,r10 226 mfspr r4,SPRN_DAR 227 EXC_XFER_EE_LITE(0x300, handle_page_fault) 228 229/* Instruction access exception. 230 * This is "never generated" by the MPC8xx. We jump to it for other 231 * translation errors. 232 */ 233 . = 0x400 234InstructionAccess: 235 EXCEPTION_PROLOG 236 mr r4,r12 237 mr r5,r9 238 EXC_XFER_EE_LITE(0x400, handle_page_fault) 239 240/* External interrupt */ 241 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 242 243/* Alignment exception */ 244 . = 0x600 245Alignment: 246 EXCEPTION_PROLOG 247 mfspr r4,SPRN_DAR 248 stw r4,_DAR(r11) 249 mfspr r5,SPRN_DSISR 250 stw r5,_DSISR(r11) 251 addi r3,r1,STACK_FRAME_OVERHEAD 252 EXC_XFER_EE(0x600, alignment_exception) 253 254/* Program check exception */ 255 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 256 257/* No FPU on MPC8xx. This exception is not supposed to happen. 258*/ 259 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) 260 261/* Decrementer */ 262 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 263 264 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 265 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 266 267/* System call */ 268 . = 0xc00 269SystemCall: 270 EXCEPTION_PROLOG 271 EXC_XFER_EE_LITE(0xc00, DoSyscall) 272 273/* Single step - not used on 601 */ 274 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 275 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 276 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) 277 278/* On the MPC8xx, this is a software emulation interrupt. It occurs 279 * for all unimplemented and illegal instructions. 280 */ 281 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) 282 283 . = 0x1100 284/* 285 * For the MPC8xx, this is a software tablewalk to load the instruction 286 * TLB. It is modelled after the example in the Motorola manual. The task 287 * switch loads the M_TWB register with the pointer to the first level table. 288 * If we discover there is no second level table (value is zero) or if there 289 * is an invalid pte, we load that into the TLB, which causes another fault 290 * into the TLB Error interrupt where we can handle such problems. 291 * We have to use the MD_xxx registers for the tablewalk because the 292 * equivalent MI_xxx registers only perform the attribute functions. 293 */ 294InstructionTLBMiss: 295#ifdef CONFIG_8xx_CPU6 296 stw r3, 8(r0) 297#endif 298 DO_8xx_CPU6(0x3f80, r3) 299 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 300 mfcr r10 301 stw r10, 0(r0) 302 stw r11, 4(r0) 303 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 304 DO_8xx_CPU6(0x3780, r3) 305 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */ 306 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ 307 308 /* If we are faulting a kernel address, we have to use the 309 * kernel page tables. 310 */ 311 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */ 312 beq 3f 313 lis r11, swapper_pg_dir@h 314 ori r11, r11, swapper_pg_dir@l 315 rlwimi r10, r11, 0, 2, 19 3163: 317 lwz r11, 0(r10) /* Get the level 1 entry */ 318 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ 319 beq 2f /* If zero, don't try to find a pte */ 320 321 /* We have a pte table, so load the MI_TWC with the attributes 322 * for this "segment." 323 */ 324 ori r11,r11,1 /* Set valid bit */ 325 DO_8xx_CPU6(0x2b80, r3) 326 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ 327 DO_8xx_CPU6(0x3b80, r3) 328 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 329 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ 330 lwz r10, 0(r11) /* Get the pte */ 331 332 ori r10, r10, _PAGE_ACCESSED 333 stw r10, 0(r11) 334 335 /* The Linux PTE won't go exactly into the MMU TLB. 336 * Software indicator bits 21, 22 and 28 must be clear. 337 * Software indicator bits 24, 25, 26, and 27 must be 338 * set. All other Linux PTE bits control the behavior 339 * of the MMU. 340 */ 3412: li r11, 0x00f0 342 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 343 DO_8xx_CPU6(0x2d80, r3) 344 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 345 346 mfspr r10, SPRN_M_TW /* Restore registers */ 347 lwz r11, 0(r0) 348 mtcr r11 349 lwz r11, 4(r0) 350#ifdef CONFIG_8xx_CPU6 351 lwz r3, 8(r0) 352#endif 353 rfi 354 355 . = 0x1200 356DataStoreTLBMiss: 357 stw r3, 8(r0) 358 DO_8xx_CPU6(0x3f80, r3) 359 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 360 mfcr r10 361 stw r10, 0(r0) 362 stw r11, 4(r0) 363 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ 364 365 /* If we are faulting a kernel address, we have to use the 366 * kernel page tables. 367 */ 368 andi. r11, r10, 0x0800 369 beq 3f 370 lis r11, swapper_pg_dir@h 371 ori r11, r11, swapper_pg_dir@l 372 rlwimi r10, r11, 0, 2, 19 373 stw r12, 16(r0) 374 b LoadLargeDTLB 3753: 376 lwz r11, 0(r10) /* Get the level 1 entry */ 377 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ 378 beq 2f /* If zero, don't try to find a pte */ 379 380 /* We have a pte table, so load fetch the pte from the table. 381 */ 382 ori r11, r11, 1 /* Set valid bit in physical L2 page */ 383 DO_8xx_CPU6(0x3b80, r3) 384 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 385 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */ 386 lwz r10, 0(r10) /* Get the pte */ 387 388 /* Insert the Guarded flag into the TWC from the Linux PTE. 389 * It is bit 27 of both the Linux PTE and the TWC (at least 390 * I got that right :-). It will be better when we can put 391 * this into the Linux pgd/pmd and load it in the operation 392 * above. 393 */ 394 rlwimi r11, r10, 0, 27, 27 395 DO_8xx_CPU6(0x3b80, r3) 396 mtspr SPRN_MD_TWC, r11 397 398 mfspr r11, SPRN_MD_TWC /* get the pte address again */ 399 ori r10, r10, _PAGE_ACCESSED 400 stw r10, 0(r11) 401 402 /* The Linux PTE won't go exactly into the MMU TLB. 403 * Software indicator bits 21, 22 and 28 must be clear. 404 * Software indicator bits 24, 25, 26, and 27 must be 405 * set. All other Linux PTE bits control the behavior 406 * of the MMU. 407 */ 4082: li r11, 0x00f0 409 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 410 DO_8xx_CPU6(0x3d80, r3) 411 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 412 413 mfspr r10, SPRN_M_TW /* Restore registers */ 414 lwz r11, 0(r0) 415 mtcr r11 416 lwz r11, 4(r0) 417 lwz r3, 8(r0) 418 rfi 419 420/* This is an instruction TLB error on the MPC8xx. This could be due 421 * to many reasons, such as executing guarded memory or illegal instruction 422 * addresses. There is nothing to do but handle a big time error fault. 423 */ 424 . = 0x1300 425InstructionTLBError: 426 b InstructionAccess 427 428LoadLargeDTLB: 429 li r12, 0 430 lwz r11, 0(r10) /* Get the level 1 entry */ 431 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ 432 beq 3f /* If zero, don't try to find a pte */ 433 434 /* We have a pte table, so load fetch the pte from the table. 435 */ 436 ori r11, r11, 1 /* Set valid bit in physical L2 page */ 437 DO_8xx_CPU6(0x3b80, r3) 438 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 439 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */ 440 lwz r10, 0(r10) /* Get the pte */ 441 442 /* Insert the Guarded flag into the TWC from the Linux PTE. 443 * It is bit 27 of both the Linux PTE and the TWC (at least 444 * I got that right :-). It will be better when we can put 445 * this into the Linux pgd/pmd and load it in the operation 446 * above. 447 */ 448 rlwimi r11, r10, 0, 27, 27 449 450 rlwimi r12, r10, 0, 0, 9 /* extract phys. addr */ 451 mfspr r3, SPRN_MD_EPN 452 rlwinm r3, r3, 0, 0, 9 /* extract virtual address */ 453 tophys(r3, r3) 454 cmpw r3, r12 /* only use 8M page if it is a direct 455 kernel mapping */ 456 bne 1f 457 ori r11, r11, MD_PS8MEG 458 li r12, 1 459 b 2f 4601: 461 li r12, 0 /* can't use 8MB TLB, so zero r12. */ 4622: 463 DO_8xx_CPU6(0x3b80, r3) 464 mtspr SPRN_MD_TWC, r11 465 466 /* The Linux PTE won't go exactly into the MMU TLB. 467 * Software indicator bits 21, 22 and 28 must be clear. 468 * Software indicator bits 24, 25, 26, and 27 must be 469 * set. All other Linux PTE bits control the behavior 470 * of the MMU. 471 */ 4723: li r11, 0x00f0 473 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 474 cmpwi r12, 1 475 bne 4f 476 ori r10, r10, 0x8 477 478 mfspr r12, SPRN_MD_EPN 479 lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */ 480 ori r3, r3, 0x0fff 481 and r12, r3, r12 482 DO_8xx_CPU6(0x3780, r3) 483 mtspr SPRN_MD_EPN, r12 484 485 lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */ 486 ori r3, r3, 0x0fff 487 and r10, r3, r10 4884: 489 DO_8xx_CPU6(0x3d80, r3) 490 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 491 492 mfspr r10, SPRN_M_TW /* Restore registers */ 493 lwz r11, 0(r0) 494 mtcr r11 495 lwz r11, 4(r0) 496 497 lwz r12, 16(r0) 498#ifdef CONFIG_8xx_CPU6 499 lwz r3, 8(r0) 500#endif 501 rfi 502 503/* This is the data TLB error on the MPC8xx. This could be due to 504 * many reasons, including a dirty update to a pte. We can catch that 505 * one here, but anything else is an error. First, we track down the 506 * Linux pte. If it is valid, write access is allowed, but the 507 * page dirty bit is not set, we will set it and reload the TLB. For 508 * any other case, we bail out to a higher level function that can 509 * handle it. 510 */ 511 . = 0x1400 512DataTLBError: 513#ifdef CONFIG_8xx_CPU6 514 stw r3, 8(r0) 515#endif 516 DO_8xx_CPU6(0x3f80, r3) 517 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 518 mfcr r10 519 stw r10, 0(r0) 520 stw r11, 4(r0) 521 522 /* First, make sure this was a store operation. 523 */ 524 mfspr r10, SPRN_DSISR 525 andis. r11, r10, 0x0200 /* If set, indicates store op */ 526 beq 2f 527 528 mfspr r10, SPRN_DAR 529 rlwinm r11, r10, 0, 0, 19 530 ori r11, r11, MD_EVALID 531 mfspr r10, SPRN_M_CASID 532 rlwimi r11, r10, 0, 28, 31 533 DO_8xx_CPU6(0x3780, r3) 534 mtspr SPRN_MD_EPN, r11 535 536 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ 537 538 /* If we are faulting a kernel address, we have to use the 539 * kernel page tables. 540 */ 541 andi. r11, r10, 0x0800 542 beq 3f 543 lis r11, swapper_pg_dir@h 544 ori r11, r11, swapper_pg_dir@l 545 rlwimi r10, r11, 0, 2, 19 5463: 547 lwz r11, 0(r10) /* Get the level 1 entry */ 548 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ 549 beq 2f /* If zero, bail */ 550 551 /* We have a pte table, so fetch the pte from the table. 552 */ 553 ori r11, r11, 1 /* Set valid bit in physical L2 page */ 554 DO_8xx_CPU6(0x3b80, r3) 555 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 556 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ 557 lwz r10, 0(r11) /* Get the pte */ 558 559 andi. r11, r10, _PAGE_RW /* Is it writeable? */ 560 beq 2f /* Bail out if not */ 561 562 /* Update 'changed', among others. 563 */ 564 ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE 565 mfspr r11, SPRN_MD_TWC /* Get pte address again */ 566 stw r10, 0(r11) /* and update pte in table */ 567 568 /* The Linux PTE won't go exactly into the MMU TLB. 569 * Software indicator bits 21, 22 and 28 must be clear. 570 * Software indicator bits 24, 25, 26, and 27 must be 571 * set. All other Linux PTE bits control the behavior 572 * of the MMU. 573 */ 574 li r11, 0x00f0 575 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 576 DO_8xx_CPU6(0x3d80, r3) 577 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 578 579 mfspr r10, SPRN_M_TW /* Restore registers */ 580 lwz r11, 0(r0) 581 mtcr r11 582 lwz r11, 4(r0) 583#ifdef CONFIG_8xx_CPU6 584 lwz r3, 8(r0) 585#endif 586 rfi 5872: 588 mfspr r10, SPRN_M_TW /* Restore registers */ 589 lwz r11, 0(r0) 590 mtcr r11 591 lwz r11, 4(r0) 592#ifdef CONFIG_8xx_CPU6 593 lwz r3, 8(r0) 594#endif 595 b DataAccess 596 597 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 598 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 599 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 600 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 601 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 602 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 603 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 604 605/* On the MPC8xx, these next four traps are used for development 606 * support of breakpoints and such. Someday I will get around to 607 * using them. 608 */ 609 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) 610 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 611 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 612 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 613 614 . = 0x2000 615 616 .globl giveup_fpu 617giveup_fpu: 618 blr 619 620/* 621 * This is where the main kernel code starts. 622 */ 623start_here: 624 /* ptr to current */ 625 lis r2,init_task@h 626 ori r2,r2,init_task@l 627 628 /* ptr to phys current thread */ 629 tophys(r4,r2) 630 addi r4,r4,THREAD /* init task's THREAD */ 631 mtspr SPRN_SPRG3,r4 632 li r3,0 633 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */ 634 635 /* stack */ 636 lis r1,init_thread_union@ha 637 addi r1,r1,init_thread_union@l 638 li r0,0 639 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 640 641 bl early_init /* We have to do this with MMU on */ 642 643/* 644 * Decide what sort of machine this is and initialize the MMU. 645 */ 646 mr r3,r31 647 mr r4,r30 648 mr r5,r29 649 mr r6,r28 650 mr r7,r27 651 bl machine_init 652 bl MMU_init 653 654/* 655 * Go back to running unmapped so we can load up new values 656 * and change to using our exception vectors. 657 * On the 8xx, all we have to do is invalidate the TLB to clear 658 * the old 8M byte TLB mappings and load the page table base register. 659 */ 660 /* The right way to do this would be to track it down through 661 * init's THREAD like the context switch code does, but this is 662 * easier......until someone changes init's static structures. 663 */ 664 lis r6, swapper_pg_dir@h 665 ori r6, r6, swapper_pg_dir@l 666 tophys(r6,r6) 667#ifdef CONFIG_8xx_CPU6 668 lis r4, cpu6_errata_word@h 669 ori r4, r4, cpu6_errata_word@l 670 li r3, 0x3980 671 stw r3, 12(r4) 672 lwz r3, 12(r4) 673#endif 674 mtspr SPRN_M_TWB, r6 675 lis r4,2f@h 676 ori r4,r4,2f@l 677 tophys(r4,r4) 678 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 679 mtspr SPRN_SRR0,r4 680 mtspr SPRN_SRR1,r3 681 rfi 682/* Load up the kernel context */ 6832: 684 SYNC /* Force all PTE updates to finish */ 685 tlbia /* Clear all TLB entries */ 686 sync /* wait for tlbia/tlbie to finish */ 687 TLBSYNC /* ... on all CPUs */ 688 689 /* set up the PTE pointers for the Abatron bdiGDB. 690 */ 691 tovirt(r6,r6) 692 lis r5, abatron_pteptrs@h 693 ori r5, r5, abatron_pteptrs@l 694 stw r5, 0xf0(r0) /* Must match your Abatron config file */ 695 tophys(r5,r5) 696 stw r6, 0(r5) 697 698/* Now turn on the MMU for real! */ 699 li r4,MSR_KERNEL 700 lis r3,start_kernel@h 701 ori r3,r3,start_kernel@l 702 mtspr SPRN_SRR0,r3 703 mtspr SPRN_SRR1,r4 704 rfi /* enable MMU and jump to start_kernel */ 705 706/* Set up the initial MMU state so we can do the first level of 707 * kernel initialization. This maps the first 8 MBytes of memory 1:1 708 * virtual to physical. Also, set the cache mode since that is defined 709 * by TLB entries and perform any additional mapping (like of the IMMR). 710 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 711 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by 712 * these mappings is mapped by page tables. 713 */ 714initial_mmu: 715 tlbia /* Invalidate all TLB entries */ 716#ifdef CONFIG_PIN_TLB 717 lis r8, MI_RSV4I@h 718 ori r8, r8, 0x1c00 719#else 720 li r8, 0 721#endif 722 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 723 724#ifdef CONFIG_PIN_TLB 725 lis r10, (MD_RSV4I | MD_RESETVAL)@h 726 ori r10, r10, 0x1c00 727 mr r8, r10 728#else 729 lis r10, MD_RESETVAL@h 730#endif 731#ifndef CONFIG_8xx_COPYBACK 732 oris r10, r10, MD_WTDEF@h 733#endif 734 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ 735 736 /* Now map the lower 8 Meg into the TLBs. For this quick hack, 737 * we can load the instruction and data TLB registers with the 738 * same values. 739 */ 740 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 741 ori r8, r8, MI_EVALID /* Mark it valid */ 742 mtspr SPRN_MI_EPN, r8 743 mtspr SPRN_MD_EPN, r8 744 li r8, MI_PS8MEG /* Set 8M byte page */ 745 ori r8, r8, MI_SVALID /* Make it valid */ 746 mtspr SPRN_MI_TWC, r8 747 mtspr SPRN_MD_TWC, r8 748 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 749 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ 750 mtspr SPRN_MD_RPN, r8 751 lis r8, MI_Kp@h /* Set the protection mode */ 752 mtspr SPRN_MI_AP, r8 753 mtspr SPRN_MD_AP, r8 754 755 /* Map another 8 MByte at the IMMR to get the processor 756 * internal registers (among other things). 757 */ 758#ifdef CONFIG_PIN_TLB 759 addi r10, r10, 0x0100 760 mtspr SPRN_MD_CTR, r10 761#endif 762 mfspr r9, 638 /* Get current IMMR */ 763 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ 764 765 mr r8, r9 /* Create vaddr for TLB */ 766 ori r8, r8, MD_EVALID /* Mark it valid */ 767 mtspr SPRN_MD_EPN, r8 768 li r8, MD_PS8MEG /* Set 8M byte page */ 769 ori r8, r8, MD_SVALID /* Make it valid */ 770 mtspr SPRN_MD_TWC, r8 771 mr r8, r9 /* Create paddr for TLB */ 772 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ 773 mtspr SPRN_MD_RPN, r8 774 775#ifdef CONFIG_PIN_TLB 776 /* Map two more 8M kernel data pages. 777 */ 778 addi r10, r10, 0x0100 779 mtspr SPRN_MD_CTR, r10 780 781 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 782 addis r8, r8, 0x0080 /* Add 8M */ 783 ori r8, r8, MI_EVALID /* Mark it valid */ 784 mtspr SPRN_MD_EPN, r8 785 li r9, MI_PS8MEG /* Set 8M byte page */ 786 ori r9, r9, MI_SVALID /* Make it valid */ 787 mtspr SPRN_MD_TWC, r9 788 li r11, MI_BOOTINIT /* Create RPN for address 0 */ 789 addis r11, r11, 0x0080 /* Add 8M */ 790 mtspr SPRN_MD_RPN, r11 791 792 addi r10, r10, 0x0100 793 mtspr SPRN_MD_CTR, r10 794 795 addis r8, r8, 0x0080 /* Add 8M */ 796 mtspr SPRN_MD_EPN, r8 797 mtspr SPRN_MD_TWC, r9 798 addis r11, r11, 0x0080 /* Add 8M */ 799 mtspr SPRN_MD_RPN, r11 800#endif 801 802 /* Since the cache is enabled according to the information we 803 * just loaded into the TLB, invalidate and enable the caches here. 804 * We should probably check/set other modes....later. 805 */ 806 lis r8, IDC_INVALL@h 807 mtspr SPRN_IC_CST, r8 808 mtspr SPRN_DC_CST, r8 809 lis r8, IDC_ENABLE@h 810 mtspr SPRN_IC_CST, r8 811#ifdef CONFIG_8xx_COPYBACK 812 mtspr SPRN_DC_CST, r8 813#else 814 /* For a debug option, I left this here to easily enable 815 * the write through cache mode 816 */ 817 lis r8, DC_SFWT@h 818 mtspr SPRN_DC_CST, r8 819 lis r8, IDC_ENABLE@h 820 mtspr SPRN_DC_CST, r8 821#endif 822 blr 823 824 825/* 826 * Set up to use a given MMU context. 827 * r3 is context number, r4 is PGD pointer. 828 * 829 * We place the physical address of the new task page directory loaded 830 * into the MMU base register, and set the ASID compare register with 831 * the new "context." 832 */ 833_GLOBAL(set_context) 834 835#ifdef CONFIG_BDI_SWITCH 836 /* Context switch the PTE pointer for the Abatron BDI2000. 837 * The PGDIR is passed as second argument. 838 */ 839 lis r5, KERNELBASE@h 840 lwz r5, 0xf0(r5) 841 stw r4, 0x4(r5) 842#endif 843 844#ifdef CONFIG_8xx_CPU6 845 lis r6, cpu6_errata_word@h 846 ori r6, r6, cpu6_errata_word@l 847 tophys (r4, r4) 848 li r7, 0x3980 849 stw r7, 12(r6) 850 lwz r7, 12(r6) 851 mtspr SPRN_M_TWB, r4 /* Update MMU base address */ 852 li r7, 0x3380 853 stw r7, 12(r6) 854 lwz r7, 12(r6) 855 mtspr SPRN_M_CASID, r3 /* Update context */ 856#else 857 mtspr SPRN_M_CASID,r3 /* Update context */ 858 tophys (r4, r4) 859 mtspr SPRN_M_TWB, r4 /* and pgd */ 860#endif 861 SYNC 862 blr 863 864#ifdef CONFIG_8xx_CPU6 865/* It's here because it is unique to the 8xx. 866 * It is important we get called with interrupts disabled. I used to 867 * do that, but it appears that all code that calls this already had 868 * interrupt disabled. 869 */ 870 .globl set_dec_cpu6 871set_dec_cpu6: 872 lis r7, cpu6_errata_word@h 873 ori r7, r7, cpu6_errata_word@l 874 li r4, 0x2c00 875 stw r4, 8(r7) 876 lwz r4, 8(r7) 877 mtspr 22, r3 /* Update Decrementer */ 878 SYNC 879 blr 880#endif 881 882/* 883 * We put a few things here that have to be page-aligned. 884 * This stuff goes at the beginning of the data segment, 885 * which is page-aligned. 886 */ 887 .data 888 .globl sdata 889sdata: 890 .globl empty_zero_page 891empty_zero_page: 892 .space 4096 893 894 .globl swapper_pg_dir 895swapper_pg_dir: 896 .space 4096 897 898/* 899 * This space gets a copy of optional info passed to us by the bootstrap 900 * Used to pass parameters into the kernel like root=/dev/sda1, etc. 901 */ 902 .globl cmd_line 903cmd_line: 904 .space 512 905 906/* Room for two PTE table poiners, usually the kernel and current user 907 * pointer to their respective root page table (pgdir). 908 */ 909abatron_pteptrs: 910 .space 8 911 912#ifdef CONFIG_8xx_CPU6 913 .globl cpu6_errata_word 914cpu6_errata_word: 915 .space 16 916#endif 917