1/* 2 * This file contains sleep low-level functions for PowerBook G3. 3 * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org) 4 * and Paul Mackerras (paulus@samba.org). 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 */ 12 13#include <asm/processor.h> 14#include <asm/page.h> 15#include <asm/ppc_asm.h> 16#include <asm/cputable.h> 17#include <asm/cache.h> 18#include <asm/thread_info.h> 19#include <asm/asm-offsets.h> 20 21#define MAGIC 0x4c617273 /* 'Lars' */ 22 23/* 24 * Structure for storing CPU registers on the stack. 25 */ 26#define SL_SP 0 27#define SL_PC 4 28#define SL_MSR 8 29#define SL_SDR1 0xc 30#define SL_SPRG0 0x10 /* 4 sprg's */ 31#define SL_DBAT0 0x20 32#define SL_IBAT0 0x28 33#define SL_DBAT1 0x30 34#define SL_IBAT1 0x38 35#define SL_DBAT2 0x40 36#define SL_IBAT2 0x48 37#define SL_DBAT3 0x50 38#define SL_IBAT3 0x58 39#define SL_TB 0x60 40#define SL_R2 0x68 41#define SL_CR 0x6c 42#define SL_R12 0x70 /* r12 to r31 */ 43#define SL_SIZE (SL_R12 + 80) 44 45 .section .text 46 .align 5 47 48#if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) || (defined(CONFIG_HOTPLUG_CPU) \ 49 && defined(CONFIG_PPC32)) 50 51/* This gets called by via-pmu.c late during the sleep process. 52 * The PMU was already send the sleep command and will shut us down 53 * soon. We need to save all that is needed and setup the wakeup 54 * vector that will be called by the ROM on wakeup 55 */ 56_GLOBAL(low_sleep_handler) 57#ifndef CONFIG_6xx 58 blr 59#else 60 mflr r0 61 stw r0,4(r1) 62 stwu r1,-SL_SIZE(r1) 63 mfcr r0 64 stw r0,SL_CR(r1) 65 stw r2,SL_R2(r1) 66 stmw r12,SL_R12(r1) 67 68 /* Save MSR & SDR1 */ 69 mfmsr r4 70 stw r4,SL_MSR(r1) 71 mfsdr1 r4 72 stw r4,SL_SDR1(r1) 73 74 /* Get a stable timebase and save it */ 751: mftbu r4 76 stw r4,SL_TB(r1) 77 mftb r5 78 stw r5,SL_TB+4(r1) 79 mftbu r3 80 cmpw r3,r4 81 bne 1b 82 83 /* Save SPRGs */ 84 mfsprg r4,0 85 stw r4,SL_SPRG0(r1) 86 mfsprg r4,1 87 stw r4,SL_SPRG0+4(r1) 88 mfsprg r4,2 89 stw r4,SL_SPRG0+8(r1) 90 mfsprg r4,3 91 stw r4,SL_SPRG0+12(r1) 92 93 /* Save BATs */ 94 mfdbatu r4,0 95 stw r4,SL_DBAT0(r1) 96 mfdbatl r4,0 97 stw r4,SL_DBAT0+4(r1) 98 mfdbatu r4,1 99 stw r4,SL_DBAT1(r1) 100 mfdbatl r4,1 101 stw r4,SL_DBAT1+4(r1) 102 mfdbatu r4,2 103 stw r4,SL_DBAT2(r1) 104 mfdbatl r4,2 105 stw r4,SL_DBAT2+4(r1) 106 mfdbatu r4,3 107 stw r4,SL_DBAT3(r1) 108 mfdbatl r4,3 109 stw r4,SL_DBAT3+4(r1) 110 mfibatu r4,0 111 stw r4,SL_IBAT0(r1) 112 mfibatl r4,0 113 stw r4,SL_IBAT0+4(r1) 114 mfibatu r4,1 115 stw r4,SL_IBAT1(r1) 116 mfibatl r4,1 117 stw r4,SL_IBAT1+4(r1) 118 mfibatu r4,2 119 stw r4,SL_IBAT2(r1) 120 mfibatl r4,2 121 stw r4,SL_IBAT2+4(r1) 122 mfibatu r4,3 123 stw r4,SL_IBAT3(r1) 124 mfibatl r4,3 125 stw r4,SL_IBAT3+4(r1) 126 127 /* Backup various CPU config stuffs */ 128 bl __save_cpu_setup 129 130 /* The ROM can wake us up via 2 different vectors: 131 * - On wallstreet & lombard, we must write a magic 132 * value 'Lars' at address 4 and a pointer to a 133 * memory location containing the PC to resume from 134 * at address 0. 135 * - On Core99, we must store the wakeup vector at 136 * address 0x80 and eventually it's parameters 137 * at address 0x84. I've have some trouble with those 138 * parameters however and I no longer use them. 139 */ 140 lis r5,grackle_wake_up@ha 141 addi r5,r5,grackle_wake_up@l 142 tophys(r5,r5) 143 stw r5,SL_PC(r1) 144 lis r4,KERNELBASE@h 145 tophys(r5,r1) 146 addi r5,r5,SL_PC 147 lis r6,MAGIC@ha 148 addi r6,r6,MAGIC@l 149 stw r5,0(r4) 150 stw r6,4(r4) 151 /* Setup stuffs at 0x80-0x84 for Core99 */ 152 lis r3,core99_wake_up@ha 153 addi r3,r3,core99_wake_up@l 154 tophys(r3,r3) 155 stw r3,0x80(r4) 156 stw r5,0x84(r4) 157 /* Store a pointer to our backup storage into 158 * a kernel global 159 */ 160 lis r3,sleep_storage@ha 161 addi r3,r3,sleep_storage@l 162 stw r5,0(r3) 163 164 .globl low_cpu_die 165low_cpu_die: 166 /* Flush & disable all caches */ 167 bl flush_disable_caches 168 169 /* Turn off data relocation. */ 170 mfmsr r3 /* Save MSR in r7 */ 171 rlwinm r3,r3,0,28,26 /* Turn off DR bit */ 172 sync 173 mtmsr r3 174 isync 175 176BEGIN_FTR_SECTION 177 sync 178 lis r3,0xfff0 179 lwz r0,0(r3) /* perform cache-inhibited load to ROM */ 180 sync /* (caches are disabled at this point) */ 181END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) 182 183/* 184 * Set the HID0 and MSR for sleep. 185 */ 186 mfspr r2,SPRN_HID0 187 rlwinm r2,r2,0,10,7 /* clear doze, nap */ 188 oris r2,r2,HID0_SLEEP@h 189 sync 190 isync 191 mtspr SPRN_HID0,r2 192 sync 193 194/* This loop puts us back to sleep in case we have a spurrious 195 * wakeup so that the host bridge properly stays asleep. The 196 * CPU will be turned off, either after a known time (about 1 197 * second) on wallstreet & lombard, or as soon as the CPU enters 198 * SLEEP mode on core99 199 */ 200 mfmsr r2 201 oris r2,r2,MSR_POW@h 2021: sync 203 mtmsr r2 204 isync 205 b 1b 206 207/* 208 * Here is the resume code. 209 */ 210 211 212/* 213 * Core99 machines resume here 214 * r4 has the physical address of SL_PC(sp) (unused) 215 */ 216_GLOBAL(core99_wake_up) 217 /* Make sure HID0 no longer contains any sleep bit and that data cache 218 * is disabled 219 */ 220 mfspr r3,SPRN_HID0 221 rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */ 222 rlwinm 3,r3,0,18,15 /* clear DCE, ICE */ 223 mtspr SPRN_HID0,r3 224 sync 225 isync 226 227 /* sanitize MSR */ 228 mfmsr r3 229 ori r3,r3,MSR_EE|MSR_IP 230 xori r3,r3,MSR_EE|MSR_IP 231 sync 232 isync 233 mtmsr r3 234 sync 235 isync 236 237 /* Recover sleep storage */ 238 lis r3,sleep_storage@ha 239 addi r3,r3,sleep_storage@l 240 tophys(r3,r3) 241 lwz r1,0(r3) 242 243 /* Pass thru to older resume code ... */ 244/* 245 * Here is the resume code for older machines. 246 * r1 has the physical address of SL_PC(sp). 247 */ 248 249grackle_wake_up: 250 251 /* Restore the kernel's segment registers before 252 * we do any r1 memory access as we are not sure they 253 * are in a sane state above the first 256Mb region 254 */ 255 li r0,16 /* load up segment register values */ 256 mtctr r0 /* for context 0 */ 257 lis r3,0x2000 /* Ku = 1, VSID = 0 */ 258 li r4,0 2593: mtsrin r3,r4 260 addi r3,r3,0x111 /* increment VSID */ 261 addis r4,r4,0x1000 /* address of next segment */ 262 bdnz 3b 263 sync 264 isync 265 266 subi r1,r1,SL_PC 267 268 /* Restore various CPU config stuffs */ 269 bl __restore_cpu_setup 270 271 /* Make sure all FPRs have been initialized */ 272 bl reloc_offset 273 bl __init_fpu_registers 274 275 /* Invalidate & enable L1 cache, we don't care about 276 * whatever the ROM may have tried to write to memory 277 */ 278 bl __inval_enable_L1 279 280 /* Restore the BATs, and SDR1. Then we can turn on the MMU. */ 281 lwz r4,SL_SDR1(r1) 282 mtsdr1 r4 283 lwz r4,SL_SPRG0(r1) 284 mtsprg 0,r4 285 lwz r4,SL_SPRG0+4(r1) 286 mtsprg 1,r4 287 lwz r4,SL_SPRG0+8(r1) 288 mtsprg 2,r4 289 lwz r4,SL_SPRG0+12(r1) 290 mtsprg 3,r4 291 292 lwz r4,SL_DBAT0(r1) 293 mtdbatu 0,r4 294 lwz r4,SL_DBAT0+4(r1) 295 mtdbatl 0,r4 296 lwz r4,SL_DBAT1(r1) 297 mtdbatu 1,r4 298 lwz r4,SL_DBAT1+4(r1) 299 mtdbatl 1,r4 300 lwz r4,SL_DBAT2(r1) 301 mtdbatu 2,r4 302 lwz r4,SL_DBAT2+4(r1) 303 mtdbatl 2,r4 304 lwz r4,SL_DBAT3(r1) 305 mtdbatu 3,r4 306 lwz r4,SL_DBAT3+4(r1) 307 mtdbatl 3,r4 308 lwz r4,SL_IBAT0(r1) 309 mtibatu 0,r4 310 lwz r4,SL_IBAT0+4(r1) 311 mtibatl 0,r4 312 lwz r4,SL_IBAT1(r1) 313 mtibatu 1,r4 314 lwz r4,SL_IBAT1+4(r1) 315 mtibatl 1,r4 316 lwz r4,SL_IBAT2(r1) 317 mtibatu 2,r4 318 lwz r4,SL_IBAT2+4(r1) 319 mtibatl 2,r4 320 lwz r4,SL_IBAT3(r1) 321 mtibatu 3,r4 322 lwz r4,SL_IBAT3+4(r1) 323 mtibatl 3,r4 324 325BEGIN_FTR_SECTION 326 li r4,0 327 mtspr SPRN_DBAT4U,r4 328 mtspr SPRN_DBAT4L,r4 329 mtspr SPRN_DBAT5U,r4 330 mtspr SPRN_DBAT5L,r4 331 mtspr SPRN_DBAT6U,r4 332 mtspr SPRN_DBAT6L,r4 333 mtspr SPRN_DBAT7U,r4 334 mtspr SPRN_DBAT7L,r4 335 mtspr SPRN_IBAT4U,r4 336 mtspr SPRN_IBAT4L,r4 337 mtspr SPRN_IBAT5U,r4 338 mtspr SPRN_IBAT5L,r4 339 mtspr SPRN_IBAT6U,r4 340 mtspr SPRN_IBAT6L,r4 341 mtspr SPRN_IBAT7U,r4 342 mtspr SPRN_IBAT7L,r4 343END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) 344 345 /* Flush all TLBs */ 346 lis r4,0x1000 3471: addic. r4,r4,-0x1000 348 tlbie r4 349 blt 1b 350 sync 351 352 /* restore the MSR and turn on the MMU */ 353 lwz r3,SL_MSR(r1) 354 bl turn_on_mmu 355 356 /* get back the stack pointer */ 357 tovirt(r1,r1) 358 359 /* Restore TB */ 360 li r3,0 361 mttbl r3 362 lwz r3,SL_TB(r1) 363 lwz r4,SL_TB+4(r1) 364 mttbu r3 365 mttbl r4 366 367 /* Restore the callee-saved registers and return */ 368 lwz r0,SL_CR(r1) 369 mtcr r0 370 lwz r2,SL_R2(r1) 371 lmw r12,SL_R12(r1) 372 addi r1,r1,SL_SIZE 373 lwz r0,4(r1) 374 mtlr r0 375 blr 376 377turn_on_mmu: 378 mflr r4 379 tovirt(r4,r4) 380 mtsrr0 r4 381 mtsrr1 r3 382 sync 383 isync 384 rfi 385 386#endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */ 387 388 .section .data 389 .balign L1_CACHE_BYTES 390sleep_storage: 391 .long 0 392 .balign L1_CACHE_BYTES, 0 393 394#endif /* CONFIG_6xx */ 395 .section .text 396