1/* 2 * spu hypervisor abstraction for direct hardware access. 3 * 4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 5 * Copyright 2006 Sony Corp. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 21#include <linux/interrupt.h> 22#include <linux/list.h> 23#include <linux/module.h> 24#include <linux/ptrace.h> 25#include <linux/slab.h> 26#include <linux/wait.h> 27#include <linux/mm.h> 28#include <linux/io.h> 29#include <linux/mutex.h> 30#include <linux/device.h> 31 32#include <asm/spu.h> 33#include <asm/spu_priv1.h> 34#include <asm/firmware.h> 35#include <asm/prom.h> 36 37#include "interrupt.h" 38#include "spu_priv1_mmio.h" 39 40static void int_mask_and(struct spu *spu, int class, u64 mask) 41{ 42 u64 old_mask; 43 44 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); 45 out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); 46} 47 48static void int_mask_or(struct spu *spu, int class, u64 mask) 49{ 50 u64 old_mask; 51 52 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); 53 out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); 54} 55 56static void int_mask_set(struct spu *spu, int class, u64 mask) 57{ 58 out_be64(&spu->priv1->int_mask_RW[class], mask); 59} 60 61static u64 int_mask_get(struct spu *spu, int class) 62{ 63 return in_be64(&spu->priv1->int_mask_RW[class]); 64} 65 66static void int_stat_clear(struct spu *spu, int class, u64 stat) 67{ 68 out_be64(&spu->priv1->int_stat_RW[class], stat); 69} 70 71static u64 int_stat_get(struct spu *spu, int class) 72{ 73 return in_be64(&spu->priv1->int_stat_RW[class]); 74} 75 76static void cpu_affinity_set(struct spu *spu, int cpu) 77{ 78 u64 target = iic_get_target_id(cpu); 79 u64 route = target << 48 | target << 32 | target << 16; 80 out_be64(&spu->priv1->int_route_RW, route); 81} 82 83static u64 mfc_dar_get(struct spu *spu) 84{ 85 return in_be64(&spu->priv1->mfc_dar_RW); 86} 87 88static u64 mfc_dsisr_get(struct spu *spu) 89{ 90 return in_be64(&spu->priv1->mfc_dsisr_RW); 91} 92 93static void mfc_dsisr_set(struct spu *spu, u64 dsisr) 94{ 95 out_be64(&spu->priv1->mfc_dsisr_RW, dsisr); 96} 97 98static void mfc_sdr_setup(struct spu *spu) 99{ 100 out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1)); 101} 102 103static void mfc_sr1_set(struct spu *spu, u64 sr1) 104{ 105 out_be64(&spu->priv1->mfc_sr1_RW, sr1); 106} 107 108static u64 mfc_sr1_get(struct spu *spu) 109{ 110 return in_be64(&spu->priv1->mfc_sr1_RW); 111} 112 113static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id) 114{ 115 out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id); 116} 117 118static u64 mfc_tclass_id_get(struct spu *spu) 119{ 120 return in_be64(&spu->priv1->mfc_tclass_id_RW); 121} 122 123static void tlb_invalidate(struct spu *spu) 124{ 125 out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul); 126} 127 128static void resource_allocation_groupID_set(struct spu *spu, u64 id) 129{ 130 out_be64(&spu->priv1->resource_allocation_groupID_RW, id); 131} 132 133static u64 resource_allocation_groupID_get(struct spu *spu) 134{ 135 return in_be64(&spu->priv1->resource_allocation_groupID_RW); 136} 137 138static void resource_allocation_enable_set(struct spu *spu, u64 enable) 139{ 140 out_be64(&spu->priv1->resource_allocation_enable_RW, enable); 141} 142 143static u64 resource_allocation_enable_get(struct spu *spu) 144{ 145 return in_be64(&spu->priv1->resource_allocation_enable_RW); 146} 147 148const struct spu_priv1_ops spu_priv1_mmio_ops = 149{ 150 .int_mask_and = int_mask_and, 151 .int_mask_or = int_mask_or, 152 .int_mask_set = int_mask_set, 153 .int_mask_get = int_mask_get, 154 .int_stat_clear = int_stat_clear, 155 .int_stat_get = int_stat_get, 156 .cpu_affinity_set = cpu_affinity_set, 157 .mfc_dar_get = mfc_dar_get, 158 .mfc_dsisr_get = mfc_dsisr_get, 159 .mfc_dsisr_set = mfc_dsisr_set, 160 .mfc_sdr_setup = mfc_sdr_setup, 161 .mfc_sr1_set = mfc_sr1_set, 162 .mfc_sr1_get = mfc_sr1_get, 163 .mfc_tclass_id_set = mfc_tclass_id_set, 164 .mfc_tclass_id_get = mfc_tclass_id_get, 165 .tlb_invalidate = tlb_invalidate, 166 .resource_allocation_groupID_set = resource_allocation_groupID_set, 167 .resource_allocation_groupID_get = resource_allocation_groupID_get, 168 .resource_allocation_enable_set = resource_allocation_enable_set, 169 .resource_allocation_enable_get = resource_allocation_enable_get, 170}; 171