1/* 2 * cbe_regs.h 3 * 4 * This file is intended to hold the various register definitions for CBE 5 * on-chip system devices (memory controller, IO controller, etc...) 6 * 7 * (C) Copyright IBM Corporation 2001,2006 8 * 9 * Authors: Maximino Aguilar (maguilar@us.ibm.com) 10 * David J. Erb (djerb@us.ibm.com) 11 * 12 * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp. 13 */ 14 15#ifndef CBE_REGS_H 16#define CBE_REGS_H 17 18#include <asm/cell-pmu.h> 19 20/* 21 * 22 * Some HID register definitions 23 * 24 */ 25 26/* CBE specific HID0 bits */ 27#define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul 28#define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul 29#define HID0_CBE_THERM_INT_EN 0x0000000400000000ul 30#define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul 31 32#define MAX_CBE 2 33 34/* 35 * 36 * Pervasive unit register definitions 37 * 38 */ 39 40union spe_reg { 41 u64 val; 42 u8 spe[8]; 43}; 44 45union ppe_spe_reg { 46 u64 val; 47 struct { 48 u32 ppe; 49 u32 spe; 50 }; 51}; 52 53 54struct cbe_pmd_regs { 55 /* Debug Bus Control */ 56 u64 pad_0x0000; /* 0x0000 */ 57 58 u64 group_control; /* 0x0008 */ 59 60 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */ 61 62 u64 debug_bus_control; /* 0x00a8 */ 63 64 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */ 65 66 u64 trace_aux_data; /* 0x0100 */ 67 u64 trace_buffer_0_63; /* 0x0108 */ 68 u64 trace_buffer_64_127; /* 0x0110 */ 69 u64 trace_address; /* 0x0118 */ 70 u64 ext_tr_timer; /* 0x0120 */ 71 72 u8 pad_0x0128_0x0400 [0x0400 - 0x0128]; /* 0x0128 */ 73 74 /* Performance Monitor */ 75 u64 pm_status; /* 0x0400 */ 76 u64 pm_control; /* 0x0408 */ 77 u64 pm_interval; /* 0x0410 */ 78 u64 pm_ctr[4]; /* 0x0418 */ 79 u64 pm_start_stop; /* 0x0438 */ 80 u64 pm07_control[8]; /* 0x0440 */ 81 82 u8 pad_0x0480_0x0800 [0x0800 - 0x0480]; /* 0x0480 */ 83 84 /* Thermal Sensor Registers */ 85 union spe_reg ts_ctsr1; /* 0x0800 */ 86 u64 ts_ctsr2; /* 0x0808 */ 87 union spe_reg ts_mtsr1; /* 0x0810 */ 88 u64 ts_mtsr2; /* 0x0818 */ 89 union spe_reg ts_itr1; /* 0x0820 */ 90 u64 ts_itr2; /* 0x0828 */ 91 u64 ts_gitr; /* 0x0830 */ 92 u64 ts_isr; /* 0x0838 */ 93 u64 ts_imr; /* 0x0840 */ 94 union spe_reg tm_cr1; /* 0x0848 */ 95 u64 tm_cr2; /* 0x0850 */ 96 u64 tm_simr; /* 0x0858 */ 97 union ppe_spe_reg tm_tpr; /* 0x0860 */ 98 union spe_reg tm_str1; /* 0x0868 */ 99 u64 tm_str2; /* 0x0870 */ 100 union ppe_spe_reg tm_tsr; /* 0x0878 */ 101 102 /* Power Management */ 103 u64 pmcr; /* 0x0880 */ 104#define CBE_PMD_PAUSE_ZERO_CONTROL 0x10000 105 u64 pmsr; /* 0x0888 */ 106 107 /* Time Base Register */ 108 u64 tbr; /* 0x0890 */ 109 110 u8 pad_0x0898_0x0c00 [0x0c00 - 0x0898]; /* 0x0898 */ 111 112 /* Fault Isolation Registers */ 113 u64 checkstop_fir; /* 0x0c00 */ 114 u64 recoverable_fir; /* 0x0c08 */ 115 u64 spec_att_mchk_fir; /* 0x0c10 */ 116 u64 fir_mode_reg; /* 0x0c18 */ 117 u64 fir_enable_mask; /* 0x0c20 */ 118 119 u8 pad_0x0c28_0x1000 [0x1000 - 0x0c28]; /* 0x0c28 */ 120}; 121 122extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np); 123extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu); 124 125/* 126 * PMU shadow registers 127 * 128 * Many of the registers in the performance monitoring unit are write-only, 129 * so we need to save a copy of what we write to those registers. 130 * 131 * The actual data counters are read/write. However, writing to the counters 132 * only takes effect if the PMU is enabled. Otherwise the value is stored in 133 * a hardware latch until the next time the PMU is enabled. So we save a copy 134 * of the counter values if we need to read them back while the PMU is 135 * disabled. The counter_value_in_latch field is a bitmap indicating which 136 * counters currently have a value waiting to be written. 137 */ 138 139struct cbe_pmd_shadow_regs { 140 u32 group_control; 141 u32 debug_bus_control; 142 u32 trace_address; 143 u32 ext_tr_timer; 144 u32 pm_status; 145 u32 pm_control; 146 u32 pm_interval; 147 u32 pm_start_stop; 148 u32 pm07_control[NR_CTRS]; 149 150 u32 pm_ctr[NR_PHYS_CTRS]; 151 u32 counter_value_in_latch; 152}; 153 154extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np); 155extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu); 156 157/* 158 * 159 * IIC unit register definitions 160 * 161 */ 162 163struct cbe_iic_pending_bits { 164 u32 data; 165 u8 flags; 166 u8 class; 167 u8 source; 168 u8 prio; 169}; 170 171#define CBE_IIC_IRQ_VALID 0x80 172#define CBE_IIC_IRQ_IPI 0x40 173 174struct cbe_iic_thread_regs { 175 struct cbe_iic_pending_bits pending; 176 struct cbe_iic_pending_bits pending_destr; 177 u64 generate; 178 u64 prio; 179}; 180 181struct cbe_iic_regs { 182 u8 pad_0x0000_0x0400[0x0400 - 0x0000]; /* 0x0000 */ 183 184 /* IIC interrupt registers */ 185 struct cbe_iic_thread_regs thread[2]; /* 0x0400 */ 186 187 u64 iic_ir; /* 0x0440 */ 188#define CBE_IIC_IR_PRIO(x) (((x) & 0xf) << 12) 189#define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4) 190#define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf) 191#define CBE_IIC_IR_IOC_0 0x0 192#define CBE_IIC_IR_IOC_1S 0xb 193#define CBE_IIC_IR_PT_0 0xe 194#define CBE_IIC_IR_PT_1 0xf 195 196 u64 iic_is; /* 0x0448 */ 197#define CBE_IIC_IS_PMI 0x2 198 199 u8 pad_0x0450_0x0500[0x0500 - 0x0450]; /* 0x0450 */ 200 201 /* IOC FIR */ 202 u64 ioc_fir_reset; /* 0x0500 */ 203 u64 ioc_fir_set; /* 0x0508 */ 204 u64 ioc_checkstop_enable; /* 0x0510 */ 205 u64 ioc_fir_error_mask; /* 0x0518 */ 206 u64 ioc_syserr_enable; /* 0x0520 */ 207 u64 ioc_fir; /* 0x0528 */ 208 209 u8 pad_0x0530_0x1000[0x1000 - 0x0530]; /* 0x0530 */ 210}; 211 212extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np); 213extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu); 214 215 216struct cbe_mic_tm_regs { 217 u8 pad_0x0000_0x0040[0x0040 - 0x0000]; /* 0x0000 */ 218 219 u64 mic_ctl_cnfg2; /* 0x0040 */ 220#define CBE_MIC_ENABLE_AUX_TRC 0x8000000000000000LL 221#define CBE_MIC_DISABLE_PWR_SAV_2 0x0200000000000000LL 222#define CBE_MIC_DISABLE_AUX_TRC_WRAP 0x0100000000000000LL 223#define CBE_MIC_ENABLE_AUX_TRC_INT 0x0080000000000000LL 224 225 u64 pad_0x0048; /* 0x0048 */ 226 227 u64 mic_aux_trc_base; /* 0x0050 */ 228 u64 mic_aux_trc_max_addr; /* 0x0058 */ 229 u64 mic_aux_trc_cur_addr; /* 0x0060 */ 230 u64 mic_aux_trc_grf_addr; /* 0x0068 */ 231 u64 mic_aux_trc_grf_data; /* 0x0070 */ 232 233 u64 pad_0x0078; /* 0x0078 */ 234 235 u64 mic_ctl_cnfg_0; /* 0x0080 */ 236#define CBE_MIC_DISABLE_PWR_SAV_0 0x8000000000000000LL 237 238 u64 pad_0x0088; /* 0x0088 */ 239 240 u64 slow_fast_timer_0; /* 0x0090 */ 241 u64 slow_next_timer_0; /* 0x0098 */ 242 243 u8 pad_0x00a0_0x01c0[0x01c0 - 0x0a0]; /* 0x00a0 */ 244 245 u64 mic_ctl_cnfg_1; /* 0x01c0 */ 246#define CBE_MIC_DISABLE_PWR_SAV_1 0x8000000000000000LL 247 u64 pad_0x01c8; /* 0x01c8 */ 248 249 u64 slow_fast_timer_1; /* 0x01d0 */ 250 u64 slow_next_timer_1; /* 0x01d8 */ 251 252 u8 pad_0x01e0_0x1000[0x1000 - 0x01e0]; /* 0x01e0 */ 253}; 254 255extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np); 256extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu); 257 258/* some utility functions to deal with SMT */ 259extern u32 cbe_get_hw_thread_id(int cpu); 260extern u32 cbe_cpu_to_node(int cpu); 261extern u32 cbe_node_to_cpu(int node); 262 263/* Init this module early */ 264extern void cbe_regs_init(void); 265 266 267#endif /* CBE_REGS_H */ 268