1/* 2 * MPC8555 CDS Device Tree Source 3 * 4 * Copyright 2006 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12 13/ { 14 model = "MPC8548CDS"; 15 compatible = "MPC8548CDS", "MPC85xxCDS"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 PowerPC,8548@0 { 24 device_type = "cpu"; 25 reg = <0>; 26 d-cache-line-size = <20>; // 32 bytes 27 i-cache-line-size = <20>; // 32 bytes 28 d-cache-size = <8000>; // L1, 32K 29 i-cache-size = <8000>; // L1, 32K 30 timebase-frequency = <0>; // 33 MHz, from uboot 31 bus-frequency = <0>; // 166 MHz 32 clock-frequency = <0>; // 825 MHz, from uboot 33 32-bit; 34 }; 35 }; 36 37 memory { 38 device_type = "memory"; 39 reg = <00000000 08000000>; // 128M at 0x0 40 }; 41 42 soc8548@e0000000 { 43 #address-cells = <1>; 44 #size-cells = <1>; 45 #interrupt-cells = <2>; 46 device_type = "soc"; 47 ranges = <0 e0000000 00100000>; 48 reg = <e0000000 00100000>; // CCSRBAR 1M 49 bus-frequency = <0>; 50 51 memory-controller@2000 { 52 compatible = "fsl,8548-memory-controller"; 53 reg = <2000 1000>; 54 interrupt-parent = <&mpic>; 55 interrupts = <2 2>; 56 }; 57 58 l2-cache-controller@20000 { 59 compatible = "fsl,8548-l2-cache-controller"; 60 reg = <20000 1000>; 61 cache-line-size = <20>; // 32 bytes 62 cache-size = <80000>; // L2, 512K 63 interrupt-parent = <&mpic>; 64 interrupts = <0 2>; 65 }; 66 67 i2c@3000 { 68 device_type = "i2c"; 69 compatible = "fsl-i2c"; 70 reg = <3000 100>; 71 interrupts = <1b 2>; 72 interrupt-parent = <&mpic>; 73 dfsrr; 74 }; 75 76 mdio@24520 { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 device_type = "mdio"; 80 compatible = "gianfar"; 81 reg = <24520 20>; 82 phy0: ethernet-phy@0 { 83 interrupt-parent = <&mpic>; 84 interrupts = <35 0>; 85 reg = <0>; 86 device_type = "ethernet-phy"; 87 }; 88 phy1: ethernet-phy@1 { 89 interrupt-parent = <&mpic>; 90 interrupts = <35 0>; 91 reg = <1>; 92 device_type = "ethernet-phy"; 93 }; 94 phy2: ethernet-phy@2 { 95 interrupt-parent = <&mpic>; 96 interrupts = <35 0>; 97 reg = <2>; 98 device_type = "ethernet-phy"; 99 }; 100 phy3: ethernet-phy@3 { 101 interrupt-parent = <&mpic>; 102 interrupts = <35 0>; 103 reg = <3>; 104 device_type = "ethernet-phy"; 105 }; 106 }; 107 108 ethernet@24000 { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 device_type = "network"; 112 model = "eTSEC"; 113 compatible = "gianfar"; 114 reg = <24000 1000>; 115 local-mac-address = [ 00 E0 0C 00 73 00 ]; 116 interrupts = <d 2 e 2 12 2>; 117 interrupt-parent = <&mpic>; 118 phy-handle = <&phy0>; 119 }; 120 121 ethernet@25000 { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 device_type = "network"; 125 model = "eTSEC"; 126 compatible = "gianfar"; 127 reg = <25000 1000>; 128 local-mac-address = [ 00 E0 0C 00 73 01 ]; 129 interrupts = <13 2 14 2 18 2>; 130 interrupt-parent = <&mpic>; 131 phy-handle = <&phy1>; 132 }; 133 134/* eTSEC 3/4 are currently broken 135 ethernet@26000 { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 device_type = "network"; 139 model = "eTSEC"; 140 compatible = "gianfar"; 141 reg = <26000 1000>; 142 local-mac-address = [ 00 E0 0C 00 73 02 ]; 143 interrupts = <f 2 10 2 11 2>; 144 interrupt-parent = <&mpic>; 145 phy-handle = <&phy2>; 146 }; 147 148 ethernet@27000 { 149 #address-cells = <1>; 150 #size-cells = <0>; 151 device_type = "network"; 152 model = "eTSEC"; 153 compatible = "gianfar"; 154 reg = <27000 1000>; 155 local-mac-address = [ 00 E0 0C 00 73 03 ]; 156 interrupts = <15 2 16 2 17 2>; 157 interrupt-parent = <&mpic>; 158 phy-handle = <&phy3>; 159 }; 160 */ 161 162 serial@4500 { 163 device_type = "serial"; 164 compatible = "ns16550"; 165 reg = <4500 100>; // reg base, size 166 clock-frequency = <0>; // should we fill in in uboot? 167 interrupts = <1a 2>; 168 interrupt-parent = <&mpic>; 169 }; 170 171 serial@4600 { 172 device_type = "serial"; 173 compatible = "ns16550"; 174 reg = <4600 100>; // reg base, size 175 clock-frequency = <0>; // should we fill in in uboot? 176 interrupts = <1a 2>; 177 interrupt-parent = <&mpic>; 178 }; 179 180 pci1: pci@8000 { 181 interrupt-map-mask = <1f800 0 0 7>; 182 interrupt-map = < 183 184 /* IDSEL 0x10 */ 185 08000 0 0 1 &mpic 30 1 186 08000 0 0 2 &mpic 31 1 187 08000 0 0 3 &mpic 32 1 188 08000 0 0 4 &mpic 33 1 189 190 /* IDSEL 0x11 */ 191 08800 0 0 1 &mpic 30 1 192 08800 0 0 2 &mpic 31 1 193 08800 0 0 3 &mpic 32 1 194 08800 0 0 4 &mpic 33 1 195 196 /* IDSEL 0x12 (Slot 1) */ 197 09000 0 0 1 &mpic 30 1 198 09000 0 0 2 &mpic 31 1 199 09000 0 0 3 &mpic 32 1 200 09000 0 0 4 &mpic 33 1 201 202 /* IDSEL 0x13 (Slot 2) */ 203 09800 0 0 1 &mpic 31 1 204 09800 0 0 2 &mpic 32 1 205 09800 0 0 3 &mpic 33 1 206 09800 0 0 4 &mpic 30 1 207 208 /* IDSEL 0x14 (Slot 3) */ 209 0a000 0 0 1 &mpic 32 1 210 0a000 0 0 2 &mpic 33 1 211 0a000 0 0 3 &mpic 30 1 212 0a000 0 0 4 &mpic 31 1 213 214 /* IDSEL 0x15 (Slot 4) */ 215 0a800 0 0 1 &mpic 33 1 216 0a800 0 0 2 &mpic 30 1 217 0a800 0 0 3 &mpic 31 1 218 0a800 0 0 4 &mpic 32 1 219 220 /* Bus 1 (Tundra Bridge) */ 221 /* IDSEL 0x12 (ISA bridge) */ 222 19000 0 0 1 &mpic 30 1 223 19000 0 0 2 &mpic 31 1 224 19000 0 0 3 &mpic 32 1 225 19000 0 0 4 &mpic 33 1>; 226 interrupt-parent = <&mpic>; 227 interrupts = <08 2>; 228 bus-range = <0 0>; 229 ranges = <02000000 0 80000000 80000000 0 20000000 230 01000000 0 00000000 e2000000 0 00100000>; 231 clock-frequency = <3f940aa>; 232 #interrupt-cells = <1>; 233 #size-cells = <2>; 234 #address-cells = <3>; 235 reg = <8000 1000>; 236 compatible = "85xx"; 237 device_type = "pci"; 238 239 i8259@19000 { 240 clock-frequency = <0>; 241 interrupt-controller; 242 device_type = "interrupt-controller"; 243 reg = <19000 0 0 0 1>; 244 #address-cells = <0>; 245 #interrupt-cells = <2>; 246 built-in; 247 compatible = "chrp,iic"; 248 big-endian; 249 interrupts = <1>; 250 interrupt-parent = <&pci1>; 251 }; 252 }; 253 254 pci@9000 { 255 interrupt-map-mask = <f800 0 0 7>; 256 interrupt-map = < 257 258 /* IDSEL 0x15 */ 259 a800 0 0 1 &mpic 3b 1 260 a800 0 0 2 &mpic 3b 1 261 a800 0 0 3 &mpic 3b 1 262 a800 0 0 4 &mpic 3b 1>; 263 interrupt-parent = <&mpic>; 264 interrupts = <09 2>; 265 bus-range = <0 0>; 266 ranges = <02000000 0 a0000000 a0000000 0 20000000 267 01000000 0 00000000 e3000000 0 00100000>; 268 clock-frequency = <3f940aa>; 269 #interrupt-cells = <1>; 270 #size-cells = <2>; 271 #address-cells = <3>; 272 reg = <9000 1000>; 273 compatible = "85xx"; 274 device_type = "pci"; 275 }; 276 277 mpic: pic@40000 { 278 clock-frequency = <0>; 279 interrupt-controller; 280 #address-cells = <0>; 281 #interrupt-cells = <2>; 282 reg = <40000 40000>; 283 built-in; 284 compatible = "chrp,open-pic"; 285 device_type = "open-pic"; 286 big-endian; 287 }; 288 }; 289}; 290