1/*
2 *  PARISC TLB and cache flushing support
3 *  Copyright (C) 2000-2001 Hewlett-Packard (John Marvin)
4 *  Copyright (C) 2001 Matthew Wilcox (willy at parisc-linux.org)
5 *  Copyright (C) 2002 Richard Hirst (rhirst with parisc-linux.org)
6 *
7 *    This program is free software; you can redistribute it and/or modify
8 *    it under the terms of the GNU General Public License as published by
9 *    the Free Software Foundation; either version 2, or (at your option)
10 *    any later version.
11 *
12 *    This program is distributed in the hope that it will be useful,
13 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
14 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 *    GNU General Public License for more details.
16 *
17 *    You should have received a copy of the GNU General Public License
18 *    along with this program; if not, write to the Free Software
19 *    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20 */
21
22/*
23 * NOTE: fdc,fic, and pdc instructions that use base register modification
24 *       should only use index and base registers that are not shadowed,
25 *       so that the fast path emulation in the non access miss handler
26 *       can be used.
27 */
28
29#ifdef CONFIG_64BIT
30	.level	2.0w
31#else
32	.level	2.0
33#endif
34
35#include <asm/psw.h>
36#include <asm/assembly.h>
37#include <asm/pgtable.h>
38#include <asm/cache.h>
39#include <linux/linkage.h>
40
41	.text
42	.align	128
43
44ENTRY(flush_tlb_all_local)
45	.proc
46	.callinfo NO_CALLS
47	.entry
48
49	/*
50	 * The pitlbe and pdtlbe instructions should only be used to
51	 * flush the entire tlb. Also, there needs to be no intervening
52	 * tlb operations, e.g. tlb misses, so the operation needs
53	 * to happen in real mode with all interruptions disabled.
54	 */
55
56	/* pcxt_ssm_bug	- relied upon translation! PA 2.0 Arch. F-4 and F-5 */
57	rsm		PSW_SM_I, %r19		/* save I-bit state */
58	load32		PA(1f), %r1
59	nop
60	nop
61	nop
62	nop
63	nop
64
65	rsm		PSW_SM_Q, %r0		/* prep to load iia queue */
66	mtctl		%r0, %cr17		/* Clear IIASQ tail */
67	mtctl		%r0, %cr17		/* Clear IIASQ head */
68	mtctl		%r1, %cr18		/* IIAOQ head */
69	ldo		4(%r1), %r1
70	mtctl		%r1, %cr18		/* IIAOQ tail */
71	load32		REAL_MODE_PSW, %r1
72	mtctl           %r1, %ipsw
73	rfi
74	nop
75
761:      load32		PA(cache_info), %r1
77
78	/* Flush Instruction Tlb */
79
80	LDREG		ITLB_SID_BASE(%r1), %r20
81	LDREG		ITLB_SID_STRIDE(%r1), %r21
82	LDREG		ITLB_SID_COUNT(%r1), %r22
83	LDREG		ITLB_OFF_BASE(%r1), %arg0
84	LDREG		ITLB_OFF_STRIDE(%r1), %arg1
85	LDREG		ITLB_OFF_COUNT(%r1), %arg2
86	LDREG		ITLB_LOOP(%r1), %arg3
87
88	ADDIB=		-1, %arg3, fitoneloop	/* Preadjust and test */
89	movb,<,n	%arg3, %r31, fitdone	/* If loop < 0, skip */
90	copy		%arg0, %r28		/* Init base addr */
91
92fitmanyloop:					/* Loop if LOOP >= 2 */
93	mtsp		%r20, %sr1
94	add		%r21, %r20, %r20	/* increment space */
95	copy		%arg2, %r29		/* Init middle loop count */
96
97fitmanymiddle:					/* Loop if LOOP >= 2 */
98	ADDIB>		-1, %r31, fitmanymiddle	/* Adjusted inner loop decr */
99	pitlbe		0(%sr1, %r28)
100	pitlbe,m	%arg1(%sr1, %r28)	/* Last pitlbe and addr adjust */
101	ADDIB>		-1, %r29, fitmanymiddle	/* Middle loop decr */
102	copy		%arg3, %r31		/* Re-init inner loop count */
103
104	movb,tr		%arg0, %r28, fitmanyloop /* Re-init base addr */
105	ADDIB<=,n	-1, %r22, fitdone	/* Outer loop count decr */
106
107fitoneloop:					/* Loop if LOOP = 1 */
108	mtsp		%r20, %sr1
109	copy		%arg0, %r28		/* init base addr */
110	copy		%arg2, %r29		/* init middle loop count */
111
112fitonemiddle:					/* Loop if LOOP = 1 */
113	ADDIB>		-1, %r29, fitonemiddle	/* Middle loop count decr */
114	pitlbe,m	%arg1(%sr1, %r28)	/* pitlbe for one loop */
115
116	ADDIB>		-1, %r22, fitoneloop	/* Outer loop count decr */
117	add		%r21, %r20, %r20		/* increment space */
118
119fitdone:
120
121	/* Flush Data Tlb */
122
123	LDREG		DTLB_SID_BASE(%r1), %r20
124	LDREG		DTLB_SID_STRIDE(%r1), %r21
125	LDREG		DTLB_SID_COUNT(%r1), %r22
126	LDREG		DTLB_OFF_BASE(%r1), %arg0
127	LDREG		DTLB_OFF_STRIDE(%r1), %arg1
128	LDREG		DTLB_OFF_COUNT(%r1), %arg2
129	LDREG		DTLB_LOOP(%r1), %arg3
130
131	ADDIB=		-1, %arg3, fdtoneloop	/* Preadjust and test */
132	movb,<,n	%arg3, %r31, fdtdone	/* If loop < 0, skip */
133	copy		%arg0, %r28		/* Init base addr */
134
135fdtmanyloop:					/* Loop if LOOP >= 2 */
136	mtsp		%r20, %sr1
137	add		%r21, %r20, %r20	/* increment space */
138	copy		%arg2, %r29		/* Init middle loop count */
139
140fdtmanymiddle:					/* Loop if LOOP >= 2 */
141	ADDIB>		-1, %r31, fdtmanymiddle	/* Adjusted inner loop decr */
142	pdtlbe		0(%sr1, %r28)
143	pdtlbe,m	%arg1(%sr1, %r28)	/* Last pdtlbe and addr adjust */
144	ADDIB>		-1, %r29, fdtmanymiddle	/* Middle loop decr */
145	copy		%arg3, %r31		/* Re-init inner loop count */
146
147	movb,tr		%arg0, %r28, fdtmanyloop /* Re-init base addr */
148	ADDIB<=,n	-1, %r22,fdtdone	/* Outer loop count decr */
149
150fdtoneloop:					/* Loop if LOOP = 1 */
151	mtsp		%r20, %sr1
152	copy		%arg0, %r28		/* init base addr */
153	copy		%arg2, %r29		/* init middle loop count */
154
155fdtonemiddle:					/* Loop if LOOP = 1 */
156	ADDIB>		-1, %r29, fdtonemiddle	/* Middle loop count decr */
157	pdtlbe,m	%arg1(%sr1, %r28)	/* pdtlbe for one loop */
158
159	ADDIB>		-1, %r22, fdtoneloop	/* Outer loop count decr */
160	add		%r21, %r20, %r20	/* increment space */
161
162
163fdtdone:
164	/*
165	 * Switch back to virtual mode
166	 */
167	/* pcxt_ssm_bug */
168	rsm		PSW_SM_I, %r0
169	load32		2f, %r1
170	nop
171	nop
172	nop
173	nop
174	nop
175
176	rsm		PSW_SM_Q, %r0		/* prep to load iia queue */
177	mtctl		%r0, %cr17		/* Clear IIASQ tail */
178	mtctl		%r0, %cr17		/* Clear IIASQ head */
179	mtctl		%r1, %cr18		/* IIAOQ head */
180	ldo		4(%r1), %r1
181	mtctl		%r1, %cr18		/* IIAOQ tail */
182	load32		KERNEL_PSW, %r1
183	or		%r1, %r19, %r1	/* I-bit to state on entry */
184	mtctl		%r1, %ipsw	/* restore I-bit (entire PSW) */
185	rfi
186	nop
187
1882:      bv		%r0(%r2)
189	nop
190
191	.exit
192	.procend
193ENDPROC(flush_tlb_all_local)
194
195	.import cache_info,data
196
197ENTRY(flush_instruction_cache_local)
198	.proc
199	.callinfo NO_CALLS
200	.entry
201
202	mtsp		%r0, %sr1
203	load32		cache_info, %r1
204
205	/* Flush Instruction Cache */
206
207	LDREG		ICACHE_BASE(%r1), %arg0
208	LDREG		ICACHE_STRIDE(%r1), %arg1
209	LDREG		ICACHE_COUNT(%r1), %arg2
210	LDREG		ICACHE_LOOP(%r1), %arg3
211	rsm             PSW_SM_I, %r22		/* No mmgt ops during loop*/
212	ADDIB=		-1, %arg3, fioneloop	/* Preadjust and test */
213	movb,<,n	%arg3, %r31, fisync	/* If loop < 0, do sync */
214
215fimanyloop:					/* Loop if LOOP >= 2 */
216	ADDIB>		-1, %r31, fimanyloop	/* Adjusted inner loop decr */
217	fice            %r0(%sr1, %arg0)
218	fice,m		%arg1(%sr1, %arg0)	/* Last fice and addr adjust */
219	movb,tr		%arg3, %r31, fimanyloop	/* Re-init inner loop count */
220	ADDIB<=,n	-1, %arg2, fisync	/* Outer loop decr */
221
222fioneloop:					/* Loop if LOOP = 1 */
223	ADDIB>		-1, %arg2, fioneloop	/* Outer loop count decr */
224	fice,m		%arg1(%sr1, %arg0)	/* Fice for one loop */
225
226fisync:
227	sync
228	mtsm		%r22			/* restore I-bit */
229	bv		%r0(%r2)
230	nop
231	.exit
232
233	.procend
234ENDPROC(flush_instruction_cache_local)
235
236
237	.import cache_info, data
238ENTRY(flush_data_cache_local)
239	.proc
240	.callinfo NO_CALLS
241	.entry
242
243	mtsp		%r0, %sr1
244	load32 		cache_info, %r1
245
246	/* Flush Data Cache */
247
248	LDREG		DCACHE_BASE(%r1), %arg0
249	LDREG		DCACHE_STRIDE(%r1), %arg1
250	LDREG		DCACHE_COUNT(%r1), %arg2
251	LDREG		DCACHE_LOOP(%r1), %arg3
252	rsm		PSW_SM_I, %r22
253	ADDIB=		-1, %arg3, fdoneloop	/* Preadjust and test */
254	movb,<,n	%arg3, %r31, fdsync	/* If loop < 0, do sync */
255
256fdmanyloop:					/* Loop if LOOP >= 2 */
257	ADDIB>		-1, %r31, fdmanyloop	/* Adjusted inner loop decr */
258	fdce		%r0(%sr1, %arg0)
259	fdce,m		%arg1(%sr1, %arg0)	/* Last fdce and addr adjust */
260	movb,tr		%arg3, %r31, fdmanyloop	/* Re-init inner loop count */
261	ADDIB<=,n	-1, %arg2, fdsync	/* Outer loop decr */
262
263fdoneloop:					/* Loop if LOOP = 1 */
264	ADDIB>		-1, %arg2, fdoneloop	/* Outer loop count decr */
265	fdce,m		%arg1(%sr1, %arg0)	/* Fdce for one loop */
266
267fdsync:
268	syncdma
269	sync
270	mtsm		%r22			/* restore I-bit */
271	bv		%r0(%r2)
272	nop
273	.exit
274
275	.procend
276ENDPROC(flush_data_cache_local)
277
278	.align	16
279
280ENTRY(copy_user_page_asm)
281	.proc
282	.callinfo NO_CALLS
283	.entry
284
285#ifdef CONFIG_64BIT
286	/* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
287	 * Unroll the loop by hand and arrange insn appropriately.
288	 * GCC probably can do this just as well.
289	 */
290
291	ldd		0(%r25), %r19
292	ldi		ASM_PAGE_SIZE_DIV128, %r1
293
294	ldw		64(%r25), %r0		/* prefetch 1 cacheline ahead */
295	ldw		128(%r25), %r0		/* prefetch 2 */
296
2971:	ldd		8(%r25), %r20
298	ldw		192(%r25), %r0		/* prefetch 3 */
299	ldw		256(%r25), %r0		/* prefetch 4 */
300
301	ldd		16(%r25), %r21
302	ldd		24(%r25), %r22
303	std		%r19, 0(%r26)
304	std		%r20, 8(%r26)
305
306	ldd		32(%r25), %r19
307	ldd		40(%r25), %r20
308	std		%r21, 16(%r26)
309	std		%r22, 24(%r26)
310
311	ldd		48(%r25), %r21
312	ldd		56(%r25), %r22
313	std		%r19, 32(%r26)
314	std		%r20, 40(%r26)
315
316	ldd		64(%r25), %r19
317	ldd		72(%r25), %r20
318	std		%r21, 48(%r26)
319	std		%r22, 56(%r26)
320
321	ldd		80(%r25), %r21
322	ldd		88(%r25), %r22
323	std		%r19, 64(%r26)
324	std		%r20, 72(%r26)
325
326	ldd		 96(%r25), %r19
327	ldd		104(%r25), %r20
328	std		%r21, 80(%r26)
329	std		%r22, 88(%r26)
330
331	ldd		112(%r25), %r21
332	ldd		120(%r25), %r22
333	std		%r19, 96(%r26)
334	std		%r20, 104(%r26)
335
336	ldo		128(%r25), %r25
337	std		%r21, 112(%r26)
338	std		%r22, 120(%r26)
339	ldo		128(%r26), %r26
340
341	/* conditional branches nullify on forward taken branch, and on
342	 * non-taken backward branch. Note that .+4 is a backwards branch.
343	 * The ldd should only get executed if the branch is taken.
344	 */
345	ADDIB>,n	-1, %r1, 1b		/* bundle 10 */
346	ldd		0(%r25), %r19		/* start next loads */
347
348#else
349
350	/*
351	 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
352	 * bundles (very restricted rules for bundling).
353	 * Note that until (if) we start saving
354	 * the full 64 bit register values on interrupt, we can't
355	 * use ldd/std on a 32 bit kernel.
356	 */
357	ldw		0(%r25), %r19
358	ldi		ASM_PAGE_SIZE_DIV64, %r1
359
3601:
361	ldw		4(%r25), %r20
362	ldw		8(%r25), %r21
363	ldw		12(%r25), %r22
364	stw		%r19, 0(%r26)
365	stw		%r20, 4(%r26)
366	stw		%r21, 8(%r26)
367	stw		%r22, 12(%r26)
368	ldw		16(%r25), %r19
369	ldw		20(%r25), %r20
370	ldw		24(%r25), %r21
371	ldw		28(%r25), %r22
372	stw		%r19, 16(%r26)
373	stw		%r20, 20(%r26)
374	stw		%r21, 24(%r26)
375	stw		%r22, 28(%r26)
376	ldw		32(%r25), %r19
377	ldw		36(%r25), %r20
378	ldw		40(%r25), %r21
379	ldw		44(%r25), %r22
380	stw		%r19, 32(%r26)
381	stw		%r20, 36(%r26)
382	stw		%r21, 40(%r26)
383	stw		%r22, 44(%r26)
384	ldw		48(%r25), %r19
385	ldw		52(%r25), %r20
386	ldw		56(%r25), %r21
387	ldw		60(%r25), %r22
388	stw		%r19, 48(%r26)
389	stw		%r20, 52(%r26)
390	ldo		64(%r25), %r25
391	stw		%r21, 56(%r26)
392	stw		%r22, 60(%r26)
393	ldo		64(%r26), %r26
394	ADDIB>,n	-1, %r1, 1b
395	ldw		0(%r25), %r19
396#endif
397	bv		%r0(%r2)
398	nop
399	.exit
400
401	.procend
402ENDPROC(copy_user_page_asm)
403
404/*
405 * NOTE: Code in clear_user_page has a hard coded dependency on the
406 *       maximum alias boundary being 4 Mb. We've been assured by the
407 *       parisc chip designers that there will not ever be a parisc
408 *       chip with a larger alias boundary (Never say never :-) ).
409 *
410 *       Subtle: the dtlb miss handlers support the temp alias region by
411 *       "knowing" that if a dtlb miss happens within the temp alias
412 *       region it must have occurred while in clear_user_page. Since
413 *       this routine makes use of processor local translations, we
414 *       don't want to insert them into the kernel page table. Instead,
415 *       we load up some general registers (they need to be registers
416 *       which aren't shadowed) with the physical page numbers (preshifted
417 *       for tlb insertion) needed to insert the translations. When we
418 *       miss on the translation, the dtlb miss handler inserts the
419 *       translation into the tlb using these values:
420 *
421 *          %r26 physical page (shifted for tlb insert) of "to" translation
422 *          %r23 physical page (shifted for tlb insert) of "from" translation
423 */
424
425
426ENTRY(__clear_user_page_asm)
427	.proc
428	.callinfo NO_CALLS
429	.entry
430
431	tophys_r1	%r26
432
433	ldil		L%(TMPALIAS_MAP_START), %r28
434#ifdef CONFIG_64BIT
435#if (TMPALIAS_MAP_START >= 0x80000000)
436	depdi		0, 31,32, %r28		/* clear any sign extension */
437#endif
438	extrd,u		%r26, 56,32, %r26	/* convert phys addr to tlb insert format */
439	depd		%r25, 63,22, %r28	/* Form aliased virtual address 'to' */
440	depdi		0, 63,12, %r28		/* Clear any offset bits */
441#else
442	extrw,u		%r26, 24,25, %r26	/* convert phys addr to tlb insert format */
443	depw		%r25, 31,22, %r28	/* Form aliased virtual address 'to' */
444	depwi		0, 31,12, %r28		/* Clear any offset bits */
445#endif
446
447	/* Purge any old translation */
448
449	pdtlb		0(%r28)
450
451#ifdef CONFIG_64BIT
452	ldi		ASM_PAGE_SIZE_DIV128, %r1
453
454	/* PREFETCH (Write) has not (yet) been proven to help here */
455	/* #define	PREFETCHW_OP	ldd		256(%0), %r0 */
456
4571:	std		%r0, 0(%r28)
458	std		%r0, 8(%r28)
459	std		%r0, 16(%r28)
460	std		%r0, 24(%r28)
461	std		%r0, 32(%r28)
462	std		%r0, 40(%r28)
463	std		%r0, 48(%r28)
464	std		%r0, 56(%r28)
465	std		%r0, 64(%r28)
466	std		%r0, 72(%r28)
467	std		%r0, 80(%r28)
468	std		%r0, 88(%r28)
469	std		%r0, 96(%r28)
470	std		%r0, 104(%r28)
471	std		%r0, 112(%r28)
472	std		%r0, 120(%r28)
473	ADDIB>		-1, %r1, 1b
474	ldo		128(%r28), %r28
475
476#else	/* ! CONFIG_64BIT */
477	ldi		ASM_PAGE_SIZE_DIV64, %r1
478
4791:
480	stw		%r0, 0(%r28)
481	stw		%r0, 4(%r28)
482	stw		%r0, 8(%r28)
483	stw		%r0, 12(%r28)
484	stw		%r0, 16(%r28)
485	stw		%r0, 20(%r28)
486	stw		%r0, 24(%r28)
487	stw		%r0, 28(%r28)
488	stw		%r0, 32(%r28)
489	stw		%r0, 36(%r28)
490	stw		%r0, 40(%r28)
491	stw		%r0, 44(%r28)
492	stw		%r0, 48(%r28)
493	stw		%r0, 52(%r28)
494	stw		%r0, 56(%r28)
495	stw		%r0, 60(%r28)
496	ADDIB>		-1, %r1, 1b
497	ldo		64(%r28), %r28
498#endif	/* CONFIG_64BIT */
499
500	bv		%r0(%r2)
501	nop
502	.exit
503
504	.procend
505ENDPROC(__clear_user_page_asm)
506
507ENTRY(flush_kernel_dcache_page_asm)
508	.proc
509	.callinfo NO_CALLS
510	.entry
511
512	ldil		L%dcache_stride, %r1
513	ldw		R%dcache_stride(%r1), %r23
514
515#ifdef CONFIG_64BIT
516	depdi,z		1, 63-PAGE_SHIFT,1, %r25
517#else
518	depwi,z		1, 31-PAGE_SHIFT,1, %r25
519#endif
520	add		%r26, %r25, %r25
521	sub		%r25, %r23, %r25
522
523
5241:      fdc,m		%r23(%r26)
525	fdc,m		%r23(%r26)
526	fdc,m		%r23(%r26)
527	fdc,m		%r23(%r26)
528	fdc,m		%r23(%r26)
529	fdc,m		%r23(%r26)
530	fdc,m		%r23(%r26)
531	fdc,m		%r23(%r26)
532	fdc,m		%r23(%r26)
533	fdc,m		%r23(%r26)
534	fdc,m		%r23(%r26)
535	fdc,m		%r23(%r26)
536	fdc,m		%r23(%r26)
537	fdc,m		%r23(%r26)
538	fdc,m		%r23(%r26)
539	CMPB<<		%r26, %r25,1b
540	fdc,m		%r23(%r26)
541
542	sync
543	bv		%r0(%r2)
544	nop
545	.exit
546
547	.procend
548ENDPROC(flush_kernel_dcache_page_asm)
549
550ENTRY(flush_user_dcache_page)
551	.proc
552	.callinfo NO_CALLS
553	.entry
554
555	ldil		L%dcache_stride, %r1
556	ldw		R%dcache_stride(%r1), %r23
557
558#ifdef CONFIG_64BIT
559	depdi,z		1,63-PAGE_SHIFT,1, %r25
560#else
561	depwi,z		1,31-PAGE_SHIFT,1, %r25
562#endif
563	add		%r26, %r25, %r25
564	sub		%r25, %r23, %r25
565
566
5671:      fdc,m		%r23(%sr3, %r26)
568	fdc,m		%r23(%sr3, %r26)
569	fdc,m		%r23(%sr3, %r26)
570	fdc,m		%r23(%sr3, %r26)
571	fdc,m		%r23(%sr3, %r26)
572	fdc,m		%r23(%sr3, %r26)
573	fdc,m		%r23(%sr3, %r26)
574	fdc,m		%r23(%sr3, %r26)
575	fdc,m		%r23(%sr3, %r26)
576	fdc,m		%r23(%sr3, %r26)
577	fdc,m		%r23(%sr3, %r26)
578	fdc,m		%r23(%sr3, %r26)
579	fdc,m		%r23(%sr3, %r26)
580	fdc,m		%r23(%sr3, %r26)
581	fdc,m		%r23(%sr3, %r26)
582	CMPB<<		%r26, %r25,1b
583	fdc,m		%r23(%sr3, %r26)
584
585	sync
586	bv		%r0(%r2)
587	nop
588	.exit
589
590	.procend
591ENDPROC(flush_user_dcache_page)
592
593ENTRY(flush_user_icache_page)
594	.proc
595	.callinfo NO_CALLS
596	.entry
597
598	ldil		L%dcache_stride, %r1
599	ldw		R%dcache_stride(%r1), %r23
600
601#ifdef CONFIG_64BIT
602	depdi,z		1, 63-PAGE_SHIFT,1, %r25
603#else
604	depwi,z		1, 31-PAGE_SHIFT,1, %r25
605#endif
606	add		%r26, %r25, %r25
607	sub		%r25, %r23, %r25
608
609
6101:      fic,m		%r23(%sr3, %r26)
611	fic,m		%r23(%sr3, %r26)
612	fic,m		%r23(%sr3, %r26)
613	fic,m		%r23(%sr3, %r26)
614	fic,m		%r23(%sr3, %r26)
615	fic,m		%r23(%sr3, %r26)
616	fic,m		%r23(%sr3, %r26)
617	fic,m		%r23(%sr3, %r26)
618	fic,m		%r23(%sr3, %r26)
619	fic,m		%r23(%sr3, %r26)
620	fic,m		%r23(%sr3, %r26)
621	fic,m		%r23(%sr3, %r26)
622	fic,m		%r23(%sr3, %r26)
623	fic,m		%r23(%sr3, %r26)
624	fic,m		%r23(%sr3, %r26)
625	CMPB<<		%r26, %r25,1b
626	fic,m		%r23(%sr3, %r26)
627
628	sync
629	bv		%r0(%r2)
630	nop
631	.exit
632
633	.procend
634ENDPROC(flush_user_icache_page)
635
636
637ENTRY(purge_kernel_dcache_page)
638	.proc
639	.callinfo NO_CALLS
640	.entry
641
642	ldil		L%dcache_stride, %r1
643	ldw		R%dcache_stride(%r1), %r23
644
645#ifdef CONFIG_64BIT
646	depdi,z		1, 63-PAGE_SHIFT,1, %r25
647#else
648	depwi,z		1, 31-PAGE_SHIFT,1, %r25
649#endif
650	add		%r26, %r25, %r25
651	sub		%r25, %r23, %r25
652
6531:      pdc,m		%r23(%r26)
654	pdc,m		%r23(%r26)
655	pdc,m		%r23(%r26)
656	pdc,m		%r23(%r26)
657	pdc,m		%r23(%r26)
658	pdc,m		%r23(%r26)
659	pdc,m		%r23(%r26)
660	pdc,m		%r23(%r26)
661	pdc,m		%r23(%r26)
662	pdc,m		%r23(%r26)
663	pdc,m		%r23(%r26)
664	pdc,m		%r23(%r26)
665	pdc,m		%r23(%r26)
666	pdc,m		%r23(%r26)
667	pdc,m		%r23(%r26)
668	CMPB<<		%r26, %r25, 1b
669	pdc,m		%r23(%r26)
670
671	sync
672	bv		%r0(%r2)
673	nop
674	.exit
675
676	.procend
677ENDPROC(purge_kernel_dcache_page)
678
679
680	.export flush_user_dcache_range_asm
681
682flush_user_dcache_range_asm:
683	.proc
684	.callinfo NO_CALLS
685	.entry
686
687	ldil		L%dcache_stride, %r1
688	ldw		R%dcache_stride(%r1), %r23
689	ldo		-1(%r23), %r21
690	ANDCM		%r26, %r21, %r26
691
6921:      CMPB<<,n	%r26, %r25, 1b
693	fdc,m		%r23(%sr3, %r26)
694
695	sync
696	bv		%r0(%r2)
697	nop
698	.exit
699
700	.procend
701ENDPROC(flush_alias_page)
702
703ENTRY(flush_kernel_dcache_range_asm)
704	.proc
705	.callinfo NO_CALLS
706	.entry
707
708	ldil		L%dcache_stride, %r1
709	ldw		R%dcache_stride(%r1), %r23
710	ldo		-1(%r23), %r21
711	ANDCM		%r26, %r21, %r26
712
7131:      CMPB<<,n	%r26, %r25,1b
714	fdc,m		%r23(%r26)
715
716	sync
717	syncdma
718	bv		%r0(%r2)
719	nop
720	.exit
721
722	.procend
723ENDPROC(flush_kernel_dcache_range_asm)
724
725ENTRY(flush_user_icache_range_asm)
726	.proc
727	.callinfo NO_CALLS
728	.entry
729
730	ldil		L%icache_stride, %r1
731	ldw		R%icache_stride(%r1), %r23
732	ldo		-1(%r23), %r21
733	ANDCM		%r26, %r21, %r26
734
7351:      CMPB<<,n	%r26, %r25,1b
736	fic,m		%r23(%sr3, %r26)
737
738	sync
739	bv		%r0(%r2)
740	nop
741	.exit
742
743	.procend
744ENDPROC(flush_user_icache_range_asm)
745
746ENTRY(flush_kernel_icache_page)
747	.proc
748	.callinfo NO_CALLS
749	.entry
750
751	ldil		L%icache_stride, %r1
752	ldw		R%icache_stride(%r1), %r23
753
754#ifdef CONFIG_64BIT
755	depdi,z		1, 63-PAGE_SHIFT,1, %r25
756#else
757	depwi,z		1, 31-PAGE_SHIFT,1, %r25
758#endif
759	add		%r26, %r25, %r25
760	sub		%r25, %r23, %r25
761
762
7631:      fic,m		%r23(%sr4, %r26)
764	fic,m		%r23(%sr4, %r26)
765	fic,m		%r23(%sr4, %r26)
766	fic,m		%r23(%sr4, %r26)
767	fic,m		%r23(%sr4, %r26)
768	fic,m		%r23(%sr4, %r26)
769	fic,m		%r23(%sr4, %r26)
770	fic,m		%r23(%sr4, %r26)
771	fic,m		%r23(%sr4, %r26)
772	fic,m		%r23(%sr4, %r26)
773	fic,m		%r23(%sr4, %r26)
774	fic,m		%r23(%sr4, %r26)
775	fic,m		%r23(%sr4, %r26)
776	fic,m		%r23(%sr4, %r26)
777	fic,m		%r23(%sr4, %r26)
778	CMPB<<		%r26, %r25, 1b
779	fic,m		%r23(%sr4, %r26)
780
781	sync
782	bv		%r0(%r2)
783	nop
784	.exit
785
786	.procend
787ENDPROC(flush_kernel_icache_page)
788
789ENTRY(flush_kernel_icache_range_asm)
790	.proc
791	.callinfo NO_CALLS
792	.entry
793
794	ldil		L%icache_stride, %r1
795	ldw		R%icache_stride(%r1), %r23
796	ldo		-1(%r23), %r21
797	ANDCM		%r26, %r21, %r26
798
7991:      CMPB<<,n	%r26, %r25, 1b
800	fic,m		%r23(%sr4, %r26)
801
802	sync
803	bv		%r0(%r2)
804	nop
805	.exit
806	.procend
807ENDPROC(flush_kernel_icache_range_asm)
808
809	/* align should cover use of rfi in disable_sr_hashing_asm and
810	 * srdis_done.
811	 */
812	.align	256
813ENTRY(disable_sr_hashing_asm)
814	.proc
815	.callinfo NO_CALLS
816	.entry
817
818	/*
819	 * Switch to real mode
820	 */
821	/* pcxt_ssm_bug */
822	rsm		PSW_SM_I, %r0
823	load32		PA(1f), %r1
824	nop
825	nop
826	nop
827	nop
828	nop
829
830	rsm		PSW_SM_Q, %r0		/* prep to load iia queue */
831	mtctl		%r0, %cr17		/* Clear IIASQ tail */
832	mtctl		%r0, %cr17		/* Clear IIASQ head */
833	mtctl		%r1, %cr18		/* IIAOQ head */
834	ldo		4(%r1), %r1
835	mtctl		%r1, %cr18		/* IIAOQ tail */
836	load32		REAL_MODE_PSW, %r1
837	mtctl		%r1, %ipsw
838	rfi
839	nop
840
8411:      cmpib,=,n	SRHASH_PCXST, %r26,srdis_pcxs
842	cmpib,=,n	SRHASH_PCXL, %r26,srdis_pcxl
843	cmpib,=,n	SRHASH_PA20, %r26,srdis_pa20
844	b,n		srdis_done
845
846srdis_pcxs:
847
848	/* Disable Space Register Hashing for PCXS,PCXT,PCXT' */
849
850	.word		0x141c1a00		/* mfdiag %dr0, %r28 */
851	.word		0x141c1a00		/* must issue twice */
852	depwi		0,18,1, %r28		/* Clear DHE (dcache hash enable) */
853	depwi		0,20,1, %r28		/* Clear IHE (icache hash enable) */
854	.word		0x141c1600		/* mtdiag %r28, %dr0 */
855	.word		0x141c1600		/* must issue twice */
856	b,n		srdis_done
857
858srdis_pcxl:
859
860	/* Disable Space Register Hashing for PCXL */
861
862	.word		0x141c0600		/* mfdiag %dr0, %r28 */
863	depwi           0,28,2, %r28		/* Clear DHASH_EN & IHASH_EN */
864	.word		0x141c0240		/* mtdiag %r28, %dr0 */
865	b,n		srdis_done
866
867srdis_pa20:
868
869	/* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */
870
871	.word		0x144008bc		/* mfdiag %dr2, %r28 */
872	depdi		0, 54,1, %r28		/* clear DIAG_SPHASH_ENAB (bit 54) */
873	.word		0x145c1840		/* mtdiag %r28, %dr2 */
874
875
876srdis_done:
877	/* Switch back to virtual mode */
878	rsm		PSW_SM_I, %r0		/* prep to load iia queue */
879	load32 	   	2f, %r1
880	nop
881	nop
882	nop
883	nop
884	nop
885
886	rsm		PSW_SM_Q, %r0		/* prep to load iia queue */
887	mtctl		%r0, %cr17		/* Clear IIASQ tail */
888	mtctl		%r0, %cr17		/* Clear IIASQ head */
889	mtctl		%r1, %cr18		/* IIAOQ head */
890	ldo		4(%r1), %r1
891	mtctl		%r1, %cr18		/* IIAOQ tail */
892	load32		KERNEL_PSW, %r1
893	mtctl		%r1, %ipsw
894	rfi
895	nop
896
8972:      bv		%r0(%r2)
898	nop
899	.exit
900
901	.procend
902ENDPROC(disable_sr_hashing_asm)
903
904	.end
905