1/* 2 * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c 3 * 4 * Setup pointers to hardware-dependent routines. 5 * Copyright (C) 2000-2001 Toshiba Corporation 6 * 7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the 8 * terms of the GNU General Public License version 2. This program is 9 * licensed "as is" without any warranty of any kind, whether express 10 * or implied. 11 * 12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) 13 */ 14#include <linux/init.h> 15#include <linux/types.h> 16#include <linux/ioport.h> 17#include <linux/proc_fs.h> 18#include <linux/delay.h> 19#include <linux/interrupt.h> 20#include <linux/console.h> 21#include <linux/pci.h> 22#include <linux/pm.h> 23#include <linux/platform_device.h> 24 25#include <asm/wbflush.h> 26#include <asm/reboot.h> 27#include <asm/irq.h> 28#include <asm/time.h> 29#include <asm/uaccess.h> 30#include <asm/io.h> 31#include <asm/bootinfo.h> 32#include <asm/tx4938/rbtx4938.h> 33#ifdef CONFIG_SERIAL_TXX9 34#include <linux/tty.h> 35#include <linux/serial.h> 36#include <linux/serial_core.h> 37#endif 38 39extern void rbtx4938_time_init(void) __init; 40extern char * __init prom_getcmdline(void); 41static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); 42 43/* These functions are used for rebooting or halting the machine*/ 44extern void rbtx4938_machine_restart(char *command); 45extern void rbtx4938_machine_halt(void); 46extern void rbtx4938_machine_power_off(void); 47 48/* clocks */ 49unsigned int txx9_master_clock; 50unsigned int txx9_cpu_clock; 51unsigned int txx9_gbus_clock; 52 53unsigned long rbtx4938_ce_base[8]; 54unsigned long rbtx4938_ce_size[8]; 55int txboard_pci66_mode; 56static int tx4938_pcic_trdyto; /* default: disabled */ 57static int tx4938_pcic_retryto; /* default: disabled */ 58static int tx4938_ccfg_toeon = 1; 59 60struct tx4938_pcic_reg *pcicptrs[4] = { 61 tx4938_pcicptr /* default setting for TX4938 */ 62}; 63 64static struct { 65 unsigned long base; 66 unsigned long size; 67} phys_regions[16] __initdata; 68static int num_phys_regions __initdata; 69 70#define PHYS_REGION_MINSIZE 0x10000 71 72void rbtx4938_machine_halt(void) 73{ 74 printk(KERN_NOTICE "System Halted\n"); 75 local_irq_disable(); 76 77 while (1) 78 __asm__(".set\tmips3\n\t" 79 "wait\n\t" 80 ".set\tmips0"); 81} 82 83void rbtx4938_machine_power_off(void) 84{ 85 rbtx4938_machine_halt(); 86 /* no return */ 87} 88 89void rbtx4938_machine_restart(char *command) 90{ 91 local_irq_disable(); 92 93 printk("Rebooting..."); 94 *rbtx4938_softresetlock_ptr = 1; 95 *rbtx4938_sfvol_ptr = 1; 96 *rbtx4938_softreset_ptr = 1; 97 wbflush(); 98 99 while(1); 100} 101 102void __init 103txboard_add_phys_region(unsigned long base, unsigned long size) 104{ 105 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) { 106 printk("phys_region overflow\n"); 107 return; 108 } 109 phys_regions[num_phys_regions].base = base; 110 phys_regions[num_phys_regions].size = size; 111 num_phys_regions++; 112} 113unsigned long __init 114txboard_find_free_phys_region(unsigned long begin, unsigned long end, 115 unsigned long size) 116{ 117 unsigned long base; 118 int i; 119 120 for (base = begin / size * size; base < end; base += size) { 121 for (i = 0; i < num_phys_regions; i++) { 122 if (phys_regions[i].size && 123 base <= phys_regions[i].base + (phys_regions[i].size - 1) && 124 base + (size - 1) >= phys_regions[i].base) 125 break; 126 } 127 if (i == num_phys_regions) 128 return base; 129 } 130 return 0; 131} 132unsigned long __init 133txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end, 134 unsigned long *size) 135{ 136 unsigned long sz, base; 137 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) { 138 base = txboard_find_free_phys_region(begin, end, sz); 139 if (base) { 140 *size = sz; 141 return base; 142 } 143 } 144 return 0; 145} 146unsigned long __init 147txboard_request_phys_region_range(unsigned long begin, unsigned long end, 148 unsigned long size) 149{ 150 unsigned long base; 151 base = txboard_find_free_phys_region(begin, end, size); 152 if (base) 153 txboard_add_phys_region(base, size); 154 return base; 155} 156unsigned long __init 157txboard_request_phys_region(unsigned long size) 158{ 159 unsigned long base; 160 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ 161 base = txboard_find_free_phys_region(begin, end, size); 162 if (base) 163 txboard_add_phys_region(base, size); 164 return base; 165} 166unsigned long __init 167txboard_request_phys_region_shrink(unsigned long *size) 168{ 169 unsigned long base; 170 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ 171 base = txboard_find_free_phys_region_shrink(begin, end, size); 172 if (base) 173 txboard_add_phys_region(base, *size); 174 return base; 175} 176 177#ifdef CONFIG_PCI 178void __init 179tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, 180 struct pci_controller *channel, 181 unsigned long pci_io_base, 182 int extarb) 183{ 184 int i; 185 186 /* Disable All Initiator Space */ 187 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)| 188 TX4938_PCIC_PCICCFG_G2PMEN(1)| 189 TX4938_PCIC_PCICCFG_G2PMEN(2)| 190 TX4938_PCIC_PCICCFG_G2PIOEN); 191 192 /* GB->PCI mappings */ 193 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4; 194 pcicptr->g2piogbase = pci_io_base | 195#ifdef __BIG_ENDIAN 196 TX4938_PCIC_G2PIOGBASE_ECHG 197#else 198 TX4938_PCIC_G2PIOGBASE_BSDIS 199#endif 200 ; 201 pcicptr->g2piopbase = 0; 202 for (i = 0; i < 3; i++) { 203 pcicptr->g2pmmask[i] = 0; 204 pcicptr->g2pmgbase[i] = 0; 205 pcicptr->g2pmpbase[i] = 0; 206 } 207 if (channel->mem_resource->end) { 208 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4; 209 pcicptr->g2pmgbase[0] = channel->mem_resource->start | 210#ifdef __BIG_ENDIAN 211 TX4938_PCIC_G2PMnGBASE_ECHG 212#else 213 TX4938_PCIC_G2PMnGBASE_BSDIS 214#endif 215 ; 216 pcicptr->g2pmpbase[0] = channel->mem_resource->start; 217 } 218 /* PCI->GB mappings (I/O 256B) */ 219 pcicptr->p2giopbase = 0; /* 256B */ 220 pcicptr->p2giogbase = 0; 221 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ 222 pcicptr->p2gm0plbase = 0; 223 pcicptr->p2gm0pubase = 0; 224 pcicptr->p2gmgbase[0] = 0 | 225 TX4938_PCIC_P2GMnGBASE_TMEMEN | 226#ifdef __BIG_ENDIAN 227 TX4938_PCIC_P2GMnGBASE_TECHG 228#else 229 TX4938_PCIC_P2GMnGBASE_TBSDIS 230#endif 231 ; 232 /* PCI->GB mappings (MEM 16MB) */ 233 pcicptr->p2gm1plbase = 0xffffffff; 234 pcicptr->p2gm1pubase = 0xffffffff; 235 pcicptr->p2gmgbase[1] = 0; 236 /* PCI->GB mappings (MEM 1MB) */ 237 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */ 238 pcicptr->p2gmgbase[2] = 0; 239 240 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK; 241 /* Enable Initiator Memory Space */ 242 if (channel->mem_resource->end) 243 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0); 244 /* Enable Initiator I/O Space */ 245 if (channel->io_resource->end) 246 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN; 247 /* Enable Initiator Config */ 248 pcicptr->pciccfg |= 249 TX4938_PCIC_PCICCFG_ICAEN | 250 TX4938_PCIC_PCICCFG_TCAR; 251 252 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ 253 pcicptr->pcicfg1 = 0; 254 255 pcicptr->g2ptocnt &= ~0xffff; 256 257 if (tx4938_pcic_trdyto >= 0) { 258 pcicptr->g2ptocnt &= ~0xff; 259 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff); 260 } 261 262 if (tx4938_pcic_retryto >= 0) { 263 pcicptr->g2ptocnt &= ~0xff00; 264 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00); 265 } 266 267 /* Clear All Local Bus Status */ 268 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL; 269 /* Enable All Local Bus Interrupts */ 270 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL; 271 /* Clear All Initiator Status */ 272 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL; 273 /* Enable All Initiator Interrupts */ 274 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL; 275 /* Clear All PCI Status Error */ 276 pcicptr->pcistatus = 277 (pcicptr->pcistatus & 0x0000ffff) | 278 (TX4938_PCIC_PCISTATUS_ALL << 16); 279 /* Enable All PCI Status Error Interrupts */ 280 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL; 281 282 if (!extarb) { 283 /* Reset Bus Arbiter */ 284 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA; 285 pcicptr->pbabm = 0; 286 /* Enable Bus Arbiter */ 287 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN; 288 } 289 290 /* PCIC Int => IRC IRQ16 */ 291 pcicptr->pcicfg2 = 292 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC; 293 294 pcicptr->pcistatus = PCI_COMMAND_MASTER | 295 PCI_COMMAND_MEMORY | 296 PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 297} 298 299int __init 300tx4938_report_pciclk(void) 301{ 302 unsigned long pcode = TX4938_REV_PCODE(); 303 int pciclk = 0; 304 printk("TX%lx PCIC --%s PCICLK:", 305 pcode, 306 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : ""); 307 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { 308 309 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) { 310 case TX4938_CCFG_PCIDIVMODE_4: 311 pciclk = txx9_cpu_clock / 4; break; 312 case TX4938_CCFG_PCIDIVMODE_4_5: 313 pciclk = txx9_cpu_clock * 2 / 9; break; 314 case TX4938_CCFG_PCIDIVMODE_5: 315 pciclk = txx9_cpu_clock / 5; break; 316 case TX4938_CCFG_PCIDIVMODE_5_5: 317 pciclk = txx9_cpu_clock * 2 / 11; break; 318 case TX4938_CCFG_PCIDIVMODE_8: 319 pciclk = txx9_cpu_clock / 8; break; 320 case TX4938_CCFG_PCIDIVMODE_9: 321 pciclk = txx9_cpu_clock / 9; break; 322 case TX4938_CCFG_PCIDIVMODE_10: 323 pciclk = txx9_cpu_clock / 10; break; 324 case TX4938_CCFG_PCIDIVMODE_11: 325 pciclk = txx9_cpu_clock / 11; break; 326 } 327 printk("Internal(%dMHz)", pciclk / 1000000); 328 } else { 329 printk("External"); 330 pciclk = -1; 331 } 332 printk("\n"); 333 return pciclk; 334} 335 336void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr) 337{ 338 pcicptrs[ch] = pcicptr; 339} 340 341struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch) 342{ 343 return pcicptrs[ch]; 344} 345 346static struct pci_dev *fake_pci_dev(struct pci_controller *hose, 347 int top_bus, int busnr, int devfn) 348{ 349 static struct pci_dev dev; 350 static struct pci_bus bus; 351 352 dev.sysdata = (void *)hose; 353 dev.devfn = devfn; 354 bus.number = busnr; 355 bus.ops = hose->pci_ops; 356 bus.parent = NULL; 357 dev.bus = &bus; 358 359 return &dev; 360} 361 362#define EARLY_PCI_OP(rw, size, type) \ 363static int early_##rw##_config_##size(struct pci_controller *hose, \ 364 int top_bus, int bus, int devfn, int offset, type value) \ 365{ \ 366 return pci_##rw##_config_##size( \ 367 fake_pci_dev(hose, top_bus, bus, devfn), \ 368 offset, value); \ 369} 370 371EARLY_PCI_OP(read, word, u16 *) 372 373int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus) 374{ 375 u32 pci_devfn; 376 unsigned short vid; 377 int devfn_start = 0; 378 int devfn_stop = 0xff; 379 int cap66 = -1; 380 u16 stat; 381 382 printk("PCI: Checking 66MHz capabilities...\n"); 383 384 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) { 385 early_read_config_word(hose, top_bus, current_bus, pci_devfn, 386 PCI_VENDOR_ID, &vid); 387 388 if (vid == 0xffff) continue; 389 390 /* check 66MHz capability */ 391 if (cap66 < 0) 392 cap66 = 1; 393 if (cap66) { 394 early_read_config_word(hose, top_bus, current_bus, pci_devfn, 395 PCI_STATUS, &stat); 396 if (!(stat & PCI_STATUS_66MHZ)) { 397 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n", 398 current_bus, pci_devfn); 399 cap66 = 0; 400 break; 401 } 402 } 403 } 404 return cap66 > 0; 405} 406 407int __init 408tx4938_pciclk66_setup(void) 409{ 410 int pciclk; 411 412 /* Assert M66EN */ 413 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66; 414 /* Double PCICLK (if possible) */ 415 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { 416 unsigned int pcidivmode = 417 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK; 418 switch (pcidivmode) { 419 case TX4938_CCFG_PCIDIVMODE_8: 420 case TX4938_CCFG_PCIDIVMODE_4: 421 pcidivmode = TX4938_CCFG_PCIDIVMODE_4; 422 pciclk = txx9_cpu_clock / 4; 423 break; 424 case TX4938_CCFG_PCIDIVMODE_9: 425 case TX4938_CCFG_PCIDIVMODE_4_5: 426 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; 427 pciclk = txx9_cpu_clock * 2 / 9; 428 break; 429 case TX4938_CCFG_PCIDIVMODE_10: 430 case TX4938_CCFG_PCIDIVMODE_5: 431 pcidivmode = TX4938_CCFG_PCIDIVMODE_5; 432 pciclk = txx9_cpu_clock / 5; 433 break; 434 case TX4938_CCFG_PCIDIVMODE_11: 435 case TX4938_CCFG_PCIDIVMODE_5_5: 436 default: 437 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; 438 pciclk = txx9_cpu_clock * 2 / 11; 439 break; 440 } 441 tx4938_ccfgptr->ccfg = 442 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK) 443 | pcidivmode; 444 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", 445 (unsigned long)tx4938_ccfgptr->ccfg); 446 } else { 447 pciclk = -1; 448 } 449 return pciclk; 450} 451 452extern struct pci_controller tx4938_pci_controller[]; 453static int __init tx4938_pcibios_init(void) 454{ 455 unsigned long mem_base[2]; 456 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ 457 unsigned long io_base[2]; 458 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ 459 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ 460 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); 461 462 PCIBIOS_MIN_IO = 0x00001000UL; 463 PCIBIOS_MIN_MEM = 0x01000000UL; 464 465 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); 466 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); 467 468 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", 469 (unsigned short)(tx4938_pcicptr->pciid >> 16), 470 (unsigned short)(tx4938_pcicptr->pciid & 0xffff), 471 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff), 472 extarb ? "External" : "Internal"); 473 474 /* setup PCI area */ 475 tx4938_pci_controller[0].io_resource->start = io_base[0]; 476 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1; 477 tx4938_pci_controller[0].mem_resource->start = mem_base[0]; 478 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1; 479 480 set_tx4938_pcicptr(0, tx4938_pcicptr); 481 482 register_pci_controller(&tx4938_pci_controller[0]); 483 484 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) { 485 printk("TX4938_CCFG_PCI66 already configured\n"); 486 txboard_pci66_mode = -1; /* already configured */ 487 } 488 489 /* Reset PCI Bus */ 490 *rbtx4938_pcireset_ptr = 0; 491 /* Reset PCIC */ 492 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; 493 if (txboard_pci66_mode > 0) 494 tx4938_pciclk66_setup(); 495 mdelay(10); 496 /* clear PCIC reset */ 497 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; 498 *rbtx4938_pcireset_ptr = 1; 499 wbflush(); 500 tx4938_report_pcic_status1(tx4938_pcicptr); 501 502 tx4938_report_pciclk(); 503 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); 504 if (txboard_pci66_mode == 0 && 505 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { 506 /* Reset PCI Bus */ 507 *rbtx4938_pcireset_ptr = 0; 508 /* Reset PCIC */ 509 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; 510 tx4938_pciclk66_setup(); 511 mdelay(10); 512 /* clear PCIC reset */ 513 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; 514 *rbtx4938_pcireset_ptr = 1; 515 wbflush(); 516 /* Reinitialize PCIC */ 517 tx4938_report_pciclk(); 518 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); 519 } 520 521 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); 522 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); 523 /* Reset PCIC1 */ 524 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; 525 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ 526 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) 527 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; 528 else 529 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; 530 mdelay(10); 531 /* clear PCIC1 reset */ 532 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; 533 tx4938_report_pcic_status1(tx4938_pcic1ptr); 534 535 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", 536 (unsigned short)(tx4938_pcic1ptr->pciid >> 16), 537 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), 538 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); 539 printk("%s PCICLK:%dMHz\n", 540 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "", 541 txx9_gbus_clock / 542 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) / 543 1000000); 544 545 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */ 546 tx4938_pci_controller[1].io_resource->start = 547 io_base[1] - io_base[0]; 548 tx4938_pci_controller[1].io_resource->end = 549 io_base[1] - io_base[0] + io_size[1] - 1; 550 tx4938_pci_controller[1].mem_resource->start = mem_base[1]; 551 tx4938_pci_controller[1].mem_resource->end = 552 mem_base[1] + mem_size[1] - 1; 553 set_tx4938_pcicptr(1, tx4938_pcic1ptr); 554 555 register_pci_controller(&tx4938_pci_controller[1]); 556 557 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb); 558 559 /* map ioport 0 to PCI I/O space address 0 */ 560 set_io_port_base(KSEG1 + io_base[0]); 561 562 return 0; 563} 564 565arch_initcall(tx4938_pcibios_init); 566 567#endif /* CONFIG_PCI */ 568 569/* SPI support */ 570 571/* chip select for SPI devices */ 572#define SEEPROM1_CS 7 /* PIO7 */ 573#define SEEPROM2_CS 0 /* IOC */ 574#define SEEPROM3_CS 1 /* IOC */ 575#define SRTC_CS 2 /* IOC */ 576 577static int rbtx4938_spi_cs_func(int chipid, int on) 578{ 579 unsigned char bit; 580 switch (chipid) { 581 case RBTX4938_SEEPROM1_CHIPID: 582 if (on) 583 tx4938_pioptr->dout &= ~(1 << SEEPROM1_CS); 584 else 585 tx4938_pioptr->dout |= (1 << SEEPROM1_CS); 586 return 0; 587 break; 588 case RBTX4938_SEEPROM2_CHIPID: 589 bit = (1 << SEEPROM2_CS); 590 break; 591 case RBTX4938_SEEPROM3_CHIPID: 592 bit = (1 << SEEPROM3_CS); 593 break; 594 case RBTX4938_SRTC_CHIPID: 595 bit = (1 << SRTC_CS); 596 break; 597 default: 598 return -ENODEV; 599 } 600 /* bit1,2,4 are low active, bit3 is high active */ 601 *rbtx4938_spics_ptr = 602 (*rbtx4938_spics_ptr & ~bit) | 603 ((on ? (bit ^ 0x0b) : ~(bit ^ 0x0b)) & bit); 604 return 0; 605} 606 607#ifdef CONFIG_PCI 608extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); 609 610int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr) 611{ 612 struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata; 613 static unsigned char dat[17]; 614 static int read_dat = 0; 615 int ch = 0; 616 617 if (channel != &tx4938_pci_controller[1]) 618 return -ENODEV; 619 /* TX4938 PCIC1 */ 620 switch (PCI_SLOT(dev->devfn)) { 621 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): 622 ch = 0; 623 break; 624 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): 625 ch = 1; 626 break; 627 default: 628 return -ENODEV; 629 } 630 if (!read_dat) { 631 unsigned char sum; 632 int i; 633 read_dat = 1; 634 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */ 635 if (spi_eeprom_read(RBTX4938_SEEPROM1_CHIPID, 636 0, dat, sizeof(dat))) { 637 printk(KERN_ERR "seeprom: read error.\n"); 638 } else { 639 if (strcmp(dat, "MAC") != 0) 640 printk(KERN_WARNING "seeprom: bad signature.\n"); 641 for (i = 0, sum = 0; i < sizeof(dat); i++) 642 sum += dat[i]; 643 if (sum) 644 printk(KERN_WARNING "seeprom: bad checksum.\n"); 645 } 646 } 647 memcpy(addr, &dat[4 + 6 * ch], 6); 648 return 0; 649} 650#endif /* CONFIG_PCI */ 651 652extern void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)); 653static void __init rbtx4938_spi_setup(void) 654{ 655 /* set SPI_SEL */ 656 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; 657 /* chip selects for SPI devices */ 658 tx4938_pioptr->dout |= (1 << SEEPROM1_CS); 659 tx4938_pioptr->dir |= (1 << SEEPROM1_CS); 660 txx9_spi_init(TX4938_SPI_REG, rbtx4938_spi_cs_func); 661} 662 663static struct resource rbtx4938_fpga_resource; 664 665static char pcode_str[8]; 666static struct resource tx4938_reg_resource = { 667 .start = TX4938_REG_BASE, 668 .end = TX4938_REG_BASE + TX4938_REG_SIZE, 669 .name = pcode_str, 670 .flags = IORESOURCE_MEM 671}; 672 673void __init tx4938_board_setup(void) 674{ 675 int i; 676 unsigned long divmode; 677 int cpuclk = 0; 678 unsigned long pcode = TX4938_REV_PCODE(); 679 680 ioport_resource.start = 0x1000; 681 ioport_resource.end = 0xffffffff; 682 iomem_resource.start = 0x1000; 683 iomem_resource.end = 0xffffffff; /* expand to 4GB */ 684 685 sprintf(pcode_str, "TX%lx", pcode); 686 /* SDRAMC,EBUSC are configured by PROM */ 687 for (i = 0; i < 8; i++) { 688 if (!(tx4938_ebuscptr->cr[i] & 0x8)) 689 continue; /* disabled */ 690 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); 691 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); 692 } 693 694 /* clocks */ 695 if (txx9_master_clock) { 696 /* calculate gbus_clock and cpu_clock from master_clock */ 697 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; 698 switch (divmode) { 699 case TX4938_CCFG_DIVMODE_8: 700 case TX4938_CCFG_DIVMODE_10: 701 case TX4938_CCFG_DIVMODE_12: 702 case TX4938_CCFG_DIVMODE_16: 703 case TX4938_CCFG_DIVMODE_18: 704 txx9_gbus_clock = txx9_master_clock * 4; break; 705 default: 706 txx9_gbus_clock = txx9_master_clock; 707 } 708 switch (divmode) { 709 case TX4938_CCFG_DIVMODE_2: 710 case TX4938_CCFG_DIVMODE_8: 711 cpuclk = txx9_gbus_clock * 2; break; 712 case TX4938_CCFG_DIVMODE_2_5: 713 case TX4938_CCFG_DIVMODE_10: 714 cpuclk = txx9_gbus_clock * 5 / 2; break; 715 case TX4938_CCFG_DIVMODE_3: 716 case TX4938_CCFG_DIVMODE_12: 717 cpuclk = txx9_gbus_clock * 3; break; 718 case TX4938_CCFG_DIVMODE_4: 719 case TX4938_CCFG_DIVMODE_16: 720 cpuclk = txx9_gbus_clock * 4; break; 721 case TX4938_CCFG_DIVMODE_4_5: 722 case TX4938_CCFG_DIVMODE_18: 723 cpuclk = txx9_gbus_clock * 9 / 2; break; 724 } 725 txx9_cpu_clock = cpuclk; 726 } else { 727 if (txx9_cpu_clock == 0) { 728 txx9_cpu_clock = 300000000; /* 300MHz */ 729 } 730 /* calculate gbus_clock and master_clock from cpu_clock */ 731 cpuclk = txx9_cpu_clock; 732 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; 733 switch (divmode) { 734 case TX4938_CCFG_DIVMODE_2: 735 case TX4938_CCFG_DIVMODE_8: 736 txx9_gbus_clock = cpuclk / 2; break; 737 case TX4938_CCFG_DIVMODE_2_5: 738 case TX4938_CCFG_DIVMODE_10: 739 txx9_gbus_clock = cpuclk * 2 / 5; break; 740 case TX4938_CCFG_DIVMODE_3: 741 case TX4938_CCFG_DIVMODE_12: 742 txx9_gbus_clock = cpuclk / 3; break; 743 case TX4938_CCFG_DIVMODE_4: 744 case TX4938_CCFG_DIVMODE_16: 745 txx9_gbus_clock = cpuclk / 4; break; 746 case TX4938_CCFG_DIVMODE_4_5: 747 case TX4938_CCFG_DIVMODE_18: 748 txx9_gbus_clock = cpuclk * 2 / 9; break; 749 } 750 switch (divmode) { 751 case TX4938_CCFG_DIVMODE_8: 752 case TX4938_CCFG_DIVMODE_10: 753 case TX4938_CCFG_DIVMODE_12: 754 case TX4938_CCFG_DIVMODE_16: 755 case TX4938_CCFG_DIVMODE_18: 756 txx9_master_clock = txx9_gbus_clock / 4; break; 757 default: 758 txx9_master_clock = txx9_gbus_clock; 759 } 760 } 761 /* change default value to udelay/mdelay take reasonable time */ 762 loops_per_jiffy = txx9_cpu_clock / HZ / 2; 763 764 /* CCFG */ 765 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ 766 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; 767 /* clear PCIC1 reset */ 768 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) 769 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; 770 771 /* enable Timeout BusError */ 772 if (tx4938_ccfg_toeon) 773 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; 774 775 /* DMA selection */ 776 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; 777 778 /* Use external clock for external arbiter */ 779 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) 780 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; 781 782 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", 783 pcode_str, 784 cpuclk / 1000000, txx9_master_clock / 1000000, 785 (unsigned long)tx4938_ccfgptr->crir, 786 tx4938_ccfgptr->ccfg, 787 tx4938_ccfgptr->pcfg); 788 789 printk("%s SDRAMC --", pcode_str); 790 for (i = 0; i < 4; i++) { 791 unsigned long long cr = tx4938_sdramcptr->cr[i]; 792 unsigned long ram_base, ram_size; 793 if (!((unsigned long)cr & 0x00000400)) 794 continue; /* disabled */ 795 ram_base = (unsigned long)(cr >> 49) << 21; 796 ram_size = ((unsigned long)(cr >> 33) + 1) << 21; 797 if (ram_base >= 0x20000000) 798 continue; /* high memory (ignore) */ 799 printk(" CR%d:%016Lx", i, cr); 800 txboard_add_phys_region(ram_base, ram_size); 801 } 802 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); 803 804 /* SRAM */ 805 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { 806 unsigned int size = 0x800; 807 unsigned long base = 808 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); 809 txboard_add_phys_region(base, size); 810 } 811 812 /* IRC */ 813 /* disable interrupt control */ 814 tx4938_ircptr->cer = 0; 815 816 /* TMR */ 817 /* disable all timers */ 818 for (i = 0; i < TX4938_NR_TMR; i++) { 819 tx4938_tmrptr(i)->tcr = 0x00000020; 820 tx4938_tmrptr(i)->tisr = 0; 821 tx4938_tmrptr(i)->cpra = 0xffffffff; 822 tx4938_tmrptr(i)->itmr = 0; 823 tx4938_tmrptr(i)->ccdr = 0; 824 tx4938_tmrptr(i)->pgmr = 0; 825 } 826 827 /* enable DMA */ 828 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN); 829 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN); 830 831 /* PIO */ 832 tx4938_pioptr->maskcpu = 0; 833 tx4938_pioptr->maskext = 0; 834 835 /* TX4938 internal registers */ 836 if (request_resource(&iomem_resource, &tx4938_reg_resource)) 837 printk("request resource for internal registers failed\n"); 838} 839 840#ifdef CONFIG_PCI 841static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) 842{ 843 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16); 844 unsigned long g2pstatus = pcicptr->g2pstatus; 845 unsigned long pcicstatus = pcicptr->pcicstatus; 846 static struct { 847 unsigned long flag; 848 const char *str; 849 } pcistat_tbl[] = { 850 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, 851 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, 852 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, 853 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, 854 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, 855 { PCI_STATUS_PARITY, "MasterParityError" }, 856 }, g2pstat_tbl[] = { 857 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" }, 858 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" }, 859 }, pcicstat_tbl[] = { 860 { TX4938_PCIC_PCICSTATUS_PME, "PME" }, 861 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" }, 862 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" }, 863 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" }, 864 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" }, 865 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" }, 866 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" }, 867 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" }, 868 }; 869 int i; 870 871 printk("pcistat:%04x(", pcistatus); 872 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++) 873 if (pcistatus & pcistat_tbl[i].flag) 874 printk("%s ", pcistat_tbl[i].str); 875 printk("), g2pstatus:%08lx(", g2pstatus); 876 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) 877 if (g2pstatus & g2pstat_tbl[i].flag) 878 printk("%s ", g2pstat_tbl[i].str); 879 printk("), pcicstatus:%08lx(", pcicstatus); 880 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) 881 if (pcicstatus & pcicstat_tbl[i].flag) 882 printk("%s ", pcicstat_tbl[i].str); 883 printk(")\n"); 884} 885 886void tx4938_report_pcic_status(void) 887{ 888 int i; 889 struct tx4938_pcic_reg *pcicptr; 890 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++) 891 tx4938_report_pcic_status1(pcicptr); 892} 893 894#endif /* CONFIG_PCI */ 895 896/* We use onchip r4k counter or TMR timer as our system wide timer 897 * interrupt running at 100HZ. */ 898 899extern void __init rtc_rx5c348_init(int chipid); 900void __init rbtx4938_time_init(void) 901{ 902 rtc_rx5c348_init(RBTX4938_SRTC_CHIPID); 903 mips_hpt_frequency = txx9_cpu_clock / 2; 904} 905 906void __init toshiba_rbtx4938_setup(void) 907{ 908 unsigned long long pcfg; 909 char *argptr; 910 911 iomem_resource.end = 0xffffffff; /* 4GB */ 912 913 if (txx9_master_clock == 0) 914 txx9_master_clock = 25000000; /* 25MHz */ 915 tx4938_board_setup(); 916 /* setup irq stuff */ 917 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000000); /* irq trigger */ 918 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM1), 0x00000000); /* irq trigger */ 919 /* setup serial stuff */ 920 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */ 921 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */ 922 923#ifndef CONFIG_PCI 924 set_io_port_base(RBTX4938_ETHER_BASE); 925#endif 926 927#ifdef CONFIG_SERIAL_TXX9 928 { 929 extern int early_serial_txx9_setup(struct uart_port *port); 930 int i; 931 struct uart_port req; 932 for(i = 0; i < 2; i++) { 933 memset(&req, 0, sizeof(req)); 934 req.line = i; 935 req.iotype = UPIO_MEM; 936 req.membase = (char *)(0xff1ff300 + i * 0x100); 937 req.mapbase = 0xff1ff300 + i * 0x100; 938 req.irq = 32 + i; 939 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; 940 req.uartclk = 50000000; 941 early_serial_txx9_setup(&req); 942 } 943 } 944#ifdef CONFIG_SERIAL_TXX9_CONSOLE 945 argptr = prom_getcmdline(); 946 if (strstr(argptr, "console=") == NULL) { 947 strcat(argptr, " console=ttyS0,38400"); 948 } 949#endif 950#endif 951 952#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 953 printk("PIOSEL: disabling both ata and nand selection\n"); 954 local_irq_disable(); 955 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); 956#endif 957 958#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND 959 printk("PIOSEL: enabling nand selection\n"); 960 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; 961 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; 962#endif 963 964#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA 965 printk("PIOSEL: enabling ata selection\n"); 966 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; 967 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; 968#endif 969 970#ifdef CONFIG_IP_PNP 971 argptr = prom_getcmdline(); 972 if (strstr(argptr, "ip=") == NULL) { 973 strcat(argptr, " ip=any"); 974 } 975#endif 976 977 978#ifdef CONFIG_FB 979 { 980 conswitchp = &dummy_con; 981 } 982#endif 983 984 rbtx4938_spi_setup(); 985 pcfg = tx4938_ccfgptr->pcfg; /* updated */ 986 /* fixup piosel */ 987 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == 988 TX4938_PCFG_ATA_SEL) { 989 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04; 990 } 991 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == 992 TX4938_PCFG_NDF_SEL) { 993 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08; 994 } 995 else { 996 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04); 997 } 998 999 rbtx4938_fpga_resource.name = "FPGA Registers"; 1000 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); 1001 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; 1002 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; 1003 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource)) 1004 printk("request resource for fpga failed\n"); 1005 1006 /* disable all OnBoard I/O interrupts */ 1007 *rbtx4938_imask_ptr = 0; 1008 1009 _machine_restart = rbtx4938_machine_restart; 1010 _machine_halt = rbtx4938_machine_halt; 1011 pm_power_off = rbtx4938_machine_power_off; 1012 1013 *rbtx4938_led_ptr = 0xff; 1014 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr); 1015 printk(" DIPSW:%02x,%02x\n", 1016 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr); 1017} 1018 1019#ifdef CONFIG_PROC_FS 1020extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid); 1021static int __init tx4938_spi_proc_setup(void) 1022{ 1023 struct proc_dir_entry *tx4938_spi_eeprom_dir; 1024 1025 tx4938_spi_eeprom_dir = proc_mkdir("spi_eeprom", 0); 1026 1027 if (!tx4938_spi_eeprom_dir) 1028 return -ENOMEM; 1029 1030 /* don't allow user access to RBTX4938_SEEPROM1_CHIPID 1031 * as it contains eth0 and eth1 MAC addresses 1032 */ 1033 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM2_CHIPID); 1034 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM3_CHIPID); 1035 1036 return 0; 1037} 1038 1039__initcall(tx4938_spi_proc_setup); 1040#endif 1041 1042static int __init rbtx4938_ne_init(void) 1043{ 1044 struct resource res[] = { 1045 { 1046 .start = RBTX4938_RTL_8019_BASE, 1047 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1, 1048 .flags = IORESOURCE_IO, 1049 }, { 1050 .start = RBTX4938_RTL_8019_IRQ, 1051 .flags = IORESOURCE_IRQ, 1052 } 1053 }; 1054 struct platform_device *dev = 1055 platform_device_register_simple("ne", -1, 1056 res, ARRAY_SIZE(res)); 1057 return IS_ERR(dev) ? PTR_ERR(dev) : 0; 1058} 1059device_initcall(rbtx4938_ne_init); 1060